initial commit

verilog/ALU0.2/BinaryToBCD.vcd

@@ -0,0 +1,568 @@
+$date
+	Mon Dec 23 02:48:47 2024
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module BinaryToBCDTB $end
+$var wire 12 ! bcd [11:0] $end
+$var reg 8 " binary [7:0] $end
+$scope module uut $end
+$var wire 8 # binary [7:0] $end
+$var wire 1 $ empty1 $end
+$var wire 1 % empty2 $end
+$var wire 4 & dab5 [3:0] $end
+$var wire 4 ' dab4 [3:0] $end
+$var wire 4 ( dab3 [3:0] $end
+$var wire 4 ) dab2 [3:0] $end
+$var wire 4 * dab1 [3:0] $end
+$var wire 12 + bcd [11:0] $end
+$scope module d1t $end
+$var wire 1 $ A $end
+$var wire 1 , B $end
+$var wire 1 - C $end
+$var wire 1 . D $end
+$var wire 1 / E $end
+$var wire 1 0 X $end
+$var wire 1 1 Y $end
+$var wire 1 2 Z $end
+$var wire 1 3 nor1 $end
+$var wire 1 4 nor2 $end
+$var wire 1 5 nor3 $end
+$var wire 1 6 or1 $end
+$var wire 1 7 xor1 $end
+$var wire 1 8 xor2 $end
+$upscope $end
+$scope module d2u $end
+$var wire 1 9 A $end
+$var wire 1 : B $end
+$var wire 1 ; C $end
+$var wire 1 < D $end
+$var wire 1 = E $end
+$var wire 1 > X $end
+$var wire 1 ? Y $end
+$var wire 1 @ Z $end
+$var wire 1 A nor1 $end
+$var wire 1 B nor2 $end
+$var wire 1 C nor3 $end
+$var wire 1 D or1 $end
+$var wire 1 E xor1 $end
+$var wire 1 F xor2 $end
+$upscope $end
+$scope module d3v $end
+$var wire 1 G A $end
+$var wire 1 H B $end
+$var wire 1 I C $end
+$var wire 1 J D $end
+$var wire 1 K E $end
+$var wire 1 L X $end
+$var wire 1 M Y $end
+$var wire 1 N Z $end
+$var wire 1 O nor1 $end
+$var wire 1 P nor2 $end
+$var wire 1 Q nor3 $end
+$var wire 1 R or1 $end
+$var wire 1 S xor1 $end
+$var wire 1 T xor2 $end
+$upscope $end
+$scope module d4w $end
+$var wire 1 % A $end
+$var wire 1 U B $end
+$var wire 1 V C $end
+$var wire 1 W D $end
+$var wire 1 X E $end
+$var wire 1 Y X $end
+$var wire 1 Z Y $end
+$var wire 1 [ Z $end
+$var wire 1 \ nor1 $end
+$var wire 1 ] nor2 $end
+$var wire 1 ^ nor3 $end
+$var wire 1 _ or1 $end
+$var wire 1 ` xor1 $end
+$var wire 1 a xor2 $end
+$upscope $end
+$scope module d5x $end
+$var wire 1 b A $end
+$var wire 1 c B $end
+$var wire 1 d C $end
+$var wire 1 e D $end
+$var wire 1 f E $end
+$var wire 1 g X $end
+$var wire 1 h Y $end
+$var wire 1 i Z $end
+$var wire 1 j nor1 $end
+$var wire 1 k nor2 $end
+$var wire 1 l nor3 $end
+$var wire 1 m or1 $end
+$var wire 1 n xor1 $end
+$var wire 1 o xor2 $end
+$upscope $end
+$scope module d6y $end
+$var wire 1 p A $end
+$var wire 1 q B $end
+$var wire 1 r C $end
+$var wire 1 s D $end
+$var wire 1 t E $end
+$var wire 1 u X $end
+$var wire 1 v Y $end
+$var wire 1 w Z $end
+$var wire 1 x nor1 $end
+$var wire 1 y nor2 $end
+$var wire 1 z nor3 $end
+$var wire 1 { or1 $end
+$var wire 1 | xor1 $end
+$var wire 1 } xor2 $end
+$upscope $end
+$scope module d7z $end
+$var wire 1 ~ A $end
+$var wire 1 !" B $end
+$var wire 1 "" C $end
+$var wire 1 #" D $end
+$var wire 1 $" E $end
+$var wire 1 %" X $end
+$var wire 1 &" Y $end
+$var wire 1 '" Z $end
+$var wire 1 (" nor1 $end
+$var wire 1 )" nor2 $end
+$var wire 1 *" nor3 $end
+$var wire 1 +" or1 $end
+$var wire 1 ," xor1 $end
+$var wire 1 -" xor2 $end
+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
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+$end
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+b11111111 "
+b11111111 #
+#60