initial

chapter2/fibonacci.vcd

@@ -0,0 +1,155 @@
+$date
+	Sun Aug 17 18:49:30 2025
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module fibonacciTB $end
+$var wire 32 ! num [31:0] $end
+$var reg 1 " clk $end
+$var reg 1 # rst $end
+$scope module uut $end
+$var wire 1 " clk $end
+$var wire 1 # rst $end
+$var reg 32 $ num [31:0] $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+$comment Show the parameter values. $end
+$dumpall
+$end
+#0
+$dumpvars
+bx $
+1#
+0"
+bx !
+$end
+#1
+b1 !
+b1 $
+1"
+#2
+0"
+#3
+1"
+#4
+0"
+0#
+#5
+b0 !
+b0 $
+1"
+#6
+0"
+#7
+b1 !
+b1 $
+1"
+#8
+0"
+#9
+1"
+#10
+0"
+#11
+1"
+#12
+0"
+#13
+b10 !
+b10 $
+1"
+#14
+0"
+#15
+1"
+#16
+0"
+#17
+b11 !
+b11 $
+1"
+#18
+0"
+#19
+b100 !
+b100 $
+1"
+#20
+0"
+#21
+b101 !
+b101 $
+1"
+#22
+0"
+#23
+b111 !
+b111 $
+1"
+#24
+0"
+#25
+b1001 !
+b1001 $
+1"
+#26
+0"
+#27
+b1100 !
+b1100 $
+1"
+#28
+0"
+#29
+b10000 !
+b10000 $
+1"
+#30
+0"
+#31
+b10101 !
+b10101 $
+1"
+#32
+0"
+#33
+b11100 !
+b11100 $
+1"
+#34
+0"
+#35
+b100101 !
+b100101 $
+1"
+#36
+0"
+#37
+b110001 !
+b110001 $
+1"
+#38
+0"
+#39
+b1000001 !
+b1000001 $
+1"
+#40
+0"
+#41
+b1010110 !
+b1010110 $
+1"
+#42
+0"
+#43
+b1110010 !
+b1110010 $
+1"
+#44
+0"