initial

chapter4/pc.v

@@ -0,0 +1,19 @@
+module pc (
+  input rst,
+  input clk,
+  output reg [31:0] pc,
+  output reg [31:0] next_pc
+);
+
+
+always @(posedge clk) begin 
+  if(rst) begin
+    pc <= 0;
+  end
+  else begin 
+    next_pc <= pc;
+    pc <= pc + 1;
+  end
+end
+
+endmodule