riscv single cycle
This commit is contained in:
133
chapter4/RISCcore.v
Normal file
133
chapter4/RISCcore.v
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@@ -0,0 +1,133 @@
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module RISCcore (
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input rst,
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input clk,
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output reg [31:0] pc,
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output reg [31:0] next_pc,
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output wire [31:0] instr
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);
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//PC
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always @(posedge clk) begin
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if(rst) begin
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pc <= 32'h0;
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next_pc <= 32'h4;
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end
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else begin
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next_pc <= taken_br ? br_tgt_pc : (pc + 32'h4);
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pc <= next_pc;
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end
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end
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//IMem
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reg [31:0] imem [0:255];
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initial begin
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$readmemh("program.hex", imem);
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end
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assign instr = imem[pc[31:2]];
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//Decoder
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wire isUType = ((instr[6:0] == 7'b0110111) || (instr[6:0] == 7'b0010111));
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wire isIType = ((instr[6:0] == 7'b0000011) || (instr[6:0] == 7'b0000111) || (instr[6:0] == 7'b0010011) || (instr[6:0] == 7'b0011011) || (instr [6:0] == 7'b1100111));
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wire isRType = ((instr[6:0] == 7'b0101111) || (instr[6:0] == 7'b0110011) || (instr[6:0] == 7'b0111011) || (instr[6:0] == 7'b0110011));
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wire isSType = ((instr[6:0] == 7'b0100011) || (instr[6:0] == 7'b0100111));
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wire isBType = (instr[6:0] == 7'b1100011);
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wire isJType = (instr[6:0] == 7'b1101111);
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wire [4:0] rs1 = instr[19:15];
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wire [4:0] rs2 = instr[24:20];
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wire [4:0] rd = instr[11:7];
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wire rs2Valid = (isRType || isSType || isBType);
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wire rs1Valid = (~isUType && ~isJType);
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wire rdValid = (~isSType && ~isBType);
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wire [3:0] funct3 = instr[14:12];
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wire [6:0] funct7 = instr[31:25];
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wire funct3Valid = rs1Valid;
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wire funct7Valid = isRType;
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wire [31:0] Iimm = {{21{instr[31]}}, {instr[30:25]}, {instr[24:20]}};
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wire [31:0] Simm = {{21{instr[31]}}, {instr[30:25]}, {instr[11:7]}};
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wire [31:0] Bimm = {{20{instr[31]}}, {instr[7]}, {instr[30:25]}, {instr[11:8]}, 1'b0};
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wire [31:0] Uimm = {{instr[31]}, {instr[30:20]}, {instr[19:12]}, {12{1'b0}};
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wire [31:0] Jimm = {{12{instr[31]}}, {instr[19:12]}, {instr[20]}, {instr[30:25]}, {instr[24:21]}, 1'b0};
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//Instructions
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isBEQ = (funct3 == 3'b000 && isBType);
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isBNE = (funct3 == 3'b001 && isBType);
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isBLT = (funct3 == 3'b100 && isBType);
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isBGE = (funct3 == 3'b101 && isBType);
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isBLTU = (funct3 == 3'b110 && isBType);
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isBGEU = (funct3 == 3'b111 && isBType);
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isADDI = (funct3 == 3'b000 && isIType);
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isADD = (funct7[5] == 1'b0 && isRType);
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isLW = (funct3 == 3'b010 && isIType);
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isSW = (funct3 == 3'b010 && isSType);
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//Register file
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wire rf_wr_en;
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wire [4:0] rf_wr_index;
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wire [31:0] rf_wr_data;
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wire rf_rd_en1, rf_rd_en2;
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wire [4:0] rf_rd_index1, rf_rd_index2;
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wire rf_rd_data1, rf_rd_data2;
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wire src1_value, src2_value;
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assign rf_rd_en1 = rs1Valid;
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assign rf_rd_en2 = rs2Valid;
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assign rf_rd_index1 = rs1;
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assign rf_rd_index2 = rs2;
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assign [31:0] src1_value = {31{rf_rd_data1}};
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assign [31:0] src2_value = {31{rf_rd_data2}};
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/* Maybe write logic ?
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assign rf_wr_en = 1'b0;
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assign rf_wr_index = 5'b0;
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assign rf_wr_data = 32'b0;
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Disabled */
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// ALU FOR ADD, ADDI
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wire [31:0] alu_result = 32'b0;
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wire [31:0] alu_op2 = isADDI ? Iimm : src2_value;
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assign alu_result = (isADDI || isADD) ? (src1_value + alu_op2) : 32'b0;
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//ALU Register file connect
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/*
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assign rf_wr_data = alu_result;
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assign rf_wr_en = rdValid && (isADD || isADDI);
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assign rf_wr_index = rd;
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*/
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//x0 support adding
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assign rf_wr_data = rf_wr_en ? alu_result : 32'b0;
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assign rf_wr_en = rdValid && (isADD || isADDI) && (rd != 5'b0);
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assign rf_wr_index = rd;
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//Branch
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if(isBType) begin
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wire taken_br = (isBEQ ? src1_value == src2_value : 1'b0) ||
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(isBNE ? src1_value != src2_value : 1'b0) ||
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(isBLT ? ((src1_value < src2_value) ^ (src1_value[31] != src2_value[31])) : 1'b0) ||
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(isBGE ? ((src1_value >= src2_value) ^ (src1_value[31] != src2_value)) : 1'b0) ||
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(isBLTU ? src1_value < src2_value : 1'b0) ||
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(isBGEU ? src1_value >= src2_value : 1'b0);
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wire [31:0] br_tgt_pc = next_pc + Bimm;
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end
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endmodule
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127
chapter4/RISCcore0.2v
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127
chapter4/RISCcore0.2v
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@@ -0,0 +1,127 @@
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module RISCcore2 (
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input rst,
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input clk,
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output reg [31:0] pc,
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output reg [31:0] next_pc,
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output wire [31:0] instr
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);
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//IMem
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reg [31:0] imem [0:255];
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initial begin
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$readmemh("program.hex", imem);
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end
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assign instr = imem[pc[31:2]];
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//Decoder
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wire isUType = ((instr[6:0] == 7'b0110111) || (instr[6:0] == 7'b0010111));
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wire isIType = ((instr[6:0] == 7'b0000011) || (instr[6:0] == 7'b0000111) || (instr[6:0] == 7'b0010011) || (instr[6:0] == 7'b0011011) || (instr [6:0] == 7'b1100111));
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wire isRType = ((instr[6:0] == 7'b0101111) || (instr[6:0] == 7'b0110011) || (instr[6:0] == 7'b0111011) || (instr[6:0] == 7'b0110011));
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wire isSType = ((instr[6:0] == 7'b0100011) || (instr[6:0] == 7'b0100111));
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wire isBType = (instr[6:0] == 7'b1100011);
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wire isJType = (instr[6:0] == 7'b1101111);
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wire [4:0] rs1 = instr[19:15];
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wire [4:0] rs2 = instr[24:20];
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wire [4:0] rd = instr[11:7];
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wire rs2Valid = (isRType || isSType || isBType);
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wire rs1Valid = (~isUType && ~isJType);
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wire rdValid = (~isSType && ~isBType);
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wire [3:0] funct3 = instr[14:12];
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wire [6:0] funct7 = instr[31:25];
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wire funct3Valid = rs1Valid;
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wire funct7Valid = isRType;
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wire [31:0] Iimm = {{21{instr[31]}}, instr[30:25], instr[24:20]};
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wire [31:0] Simm = {{21{instr[31]}}, instr[30:25], instr[11:7]};
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wire [31:0] Bimm = {{20{instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0};
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wire [31:0] Uimm = {instr[31], instr[30:20], instr[19:12], {12{1'b0}};
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wire [31:0] Jimm = {{12{instr[31]}}, instr[19:12], instr[20], instr[30:25], instr[24:21], 1'b0};
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//Instructions
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wire isBEQ = (funct3 == 3'b000 && isBType);
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wire isBNE = (funct3 == 3'b001 && isBType);
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wire isBLT = (funct3 == 3'b100 && isBType);
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wire isBGE = (funct3 == 3'b101 && isBType);
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wire isBLTU = (funct3 == 3'b110 && isBType);
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wire isBGEU = (funct3 == 3'b111 && isBType);
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wire isADDI = (funct3 == 3'b000 && isIType);
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wire isADD = (funct7[5] == 1'b0 && isRType && (funct3 == 3'b000));
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//Register file
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wire rf_wr_en;
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wire [4:0] rf_wr_index;
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wire [31:0] rf_wr_data;
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wire rf_rd_en1, rf_rd_en2;
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wire [4:0] rf_rd_index1, rf_rd_index2;
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wire rf_rd_data1, rf_rd_data2;
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wire [31:0] src1_value, src2_value;
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assign rf_rd_en1 = rs1Valid;
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assign rf_rd_en2 = rs2Valid;
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assign rf_rd_index1 = rs1;
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assign rf_rd_index2 = rs2;
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assign [31:0] src1_value = rf_rd_data1;
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assign [31:0] src2_value = rf_rd_data2;
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/* Maybe write logic ?
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assign rf_wr_en = 1'b0;
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assign rf_wr_index = 5'b0;
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assign rf_wr_data = 32'b0;
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Disabled */
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// ALU FOR ADD, ADDI
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wire [31:0] alu_result = 32'b0;
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wire [31:0] alu_op2 = isADDI ? Iimm : src2_value;
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assign alu_result = (isADDI || isADD) ? (src1_value + alu_op2) : 32'b0;
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//ALU Register file connect
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/*
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assign rf_wr_data = alu_result;
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assign rf_wr_en = rdValid && (isADD || isADDI);
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assign rf_wr_index = rd;
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*/
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//x0 support adding
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assign rf_wr_data = rf_wr_en ? alu_result : 32'b0;
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assign rf_wr_en = rdValid && (isADD || isADDI) && (rd != 5'b0);
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assign rf_wr_index = rd;
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//Branch
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if(isBType) begin
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wire taken_br = (isBEQ ? src1_value == src2_value : 1'b0) ||
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(isBNE ? src1_value != src2_value : 1'b0) ||
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(isBLT ? ((src1_value < src2_value) ^ (src1_value[31] != src2_value[31])) : 1'b0) ||
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(isBGE ? ((src1_value >= src2_value) ^ (src1_value[31] != src2_value)) : 1'b0) ||
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(isBLTU ? src1_value < src2_value : 1'b0) ||
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(isBGEU ? src1_value >= src2_value : 1'b0);
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wire [31:0] br_tgt_pc = next_pc + Bimm;
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end
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//PC
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always @(posedge clk) begin
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if(rst) begin
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pc <= 32'h0;
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next_pc <= 32'h4;
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end
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else begin
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next_pc <= taken_br ? br_tgt_pc : (pc + 32'h4);
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pc <= next_pc;
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end
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end
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endmodule
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120
chapter4/RISCcore2.v
Normal file
120
chapter4/RISCcore2.v
Normal file
@@ -0,0 +1,120 @@
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module RISCcore2 (
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input rst,
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input clk,
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output reg [31:0] pc,
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output reg [31:0] next_pc,
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output wire [31:0] instr
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);
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// IMem
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reg [31:0] imem [0:255];
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initial begin
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$readmemh("program.hex", imem);
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end
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assign instr = imem[pc[31:2]];
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// Decoder
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wire isUType = ((instr[6:0] == 7'b0110111) || (instr[6:0] == 7'b0010111));
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wire isIType = ((instr[6:0] == 7'b0000011) || (instr[6:0] == 7'b0000111) || (instr[6:0] == 7'b0010011) || (instr[6:0] == 7'b0011011) || (instr [6:0] == 7'b1100111));
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wire isRType = ((instr[6:0] == 7'b0101111) || (instr[6:0] == 7'b0110011) || (instr[6:0] == 7'b0111011));
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wire isSType = ((instr[6:0] == 7'b0100011) || (instr[6:0] == 7'b0100111));
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wire isBType = (instr[6:0] == 7'b1100011);
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wire isJType = (instr[6:0] == 7'b1101111);
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wire [4:0] rs1 = instr[19:15];
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wire [4:0] rs2 = instr[24:20];
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wire [4:0] rd = instr[11:7];
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wire rs2Valid = (isRType || isSType || isBType);
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wire rs1Valid = (~isUType && ~isJType);
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wire rdValid = (~isSType && ~isBType);
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wire [3:0] funct3 = instr[14:12];
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wire [6:0] funct7 = instr[31:25];
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// FIXED: Removed extra spaces in immediate concatenations
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wire [31:0] Iimm = {{21{instr[31]}}, instr[30:25], instr[24:20]};
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wire [31:0] Simm = {{21{instr[31]}}, instr[30:25], instr[11:7]};
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wire [31:0] Bimm = {{20{instr[31]}}, instr[7], instr[30:25], instr[11:8], 1'b0};
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wire [31:0] Uimm = {instr[31], instr[30:20], instr[19:12], {12{1'b0}}};
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wire [31:0] Jimm = {{12{instr[31]}}, instr[19:12], instr[20], instr[30:25], instr[24:21], 1'b0};
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// Instructions
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wire isBEQ = (funct3 == 3'b000 && isBType);
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wire isBNE = (funct3 == 3'b001 && isBType);
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wire isBLT = (funct3 == 3'b100 && isBType);
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wire isBGE = (funct3 == 3'b101 && isBType);
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wire isBLTU = (funct3 == 3'b110 && isBType);
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wire isBGEU = (funct3 == 3'b111 && isBType);
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wire isADDI = (funct3 == 3'b000 && isIType);
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wire isADD = (funct7[5] == 1'b0 && isRType && (funct3 == 3'b000));
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// Register file signals
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wire rf_wr_en;
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wire [4:0] rf_wr_index;
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wire [31:0] rf_wr_data;
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wire rf_rd_en1, rf_rd_en2;
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wire [4:0] rf_rd_index1, rf_rd_index2;
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wire [31:0] rf_rd_data1, rf_rd_data2;
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wire [31:0] src1_value, src2_value;
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// Connect register file read ports
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assign rf_rd_en1 = rs1Valid;
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assign rf_rd_en2 = rs2Valid;
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assign rf_rd_index1 = rs1;
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assign rf_rd_index2 = rs2;
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// Connect outputs
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assign src1_value = rf_rd_data1;
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assign src2_value = rf_rd_data2;
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// ALU FOR ADD, ADDI
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wire [31:0] alu_result;
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wire [31:0] alu_op2 = isADDI ? Iimm : src2_value;
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assign alu_result = (isADDI || isADD) ? (src1_value + alu_op2) : 32'b0;
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// x0 support adding
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assign rf_wr_data = rf_wr_en ? alu_result : 32'b0;
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assign rf_wr_en = rdValid && (isADD || isADDI) && (rd != 5'b0);
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assign rf_wr_index = rd;
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// Branch logic
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wire taken_br;
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wire [31:0] br_tgt_pc;
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// Manual signed comparison for BLT and BGE
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wire signed_lt = (src1_value[31] && !src2_value[31]) ? 1'b1 : // src1 negative, src2 positive
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(!src1_value[31] && src2_value[31]) ? 1'b0 : // src1 positive, src2 negative
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(src1_value < src2_value); // same sign, compare normally
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wire signed_ge = (src1_value[31] && !src2_value[31]) ? 1'b0 : // src1 negative, src2 positive
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(!src1_value[31] && src2_value[31]) ? 1'b1 : // src1 positive, src2 negative
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(src1_value >= src2_value); // same sign, compare normally
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// Branch condition calculation
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assign taken_br =
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isBEQ ? (src1_value == src2_value) :
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isBNE ? (src1_value != src2_value) :
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isBLT ? signed_lt :
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isBGE ? signed_ge :
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isBLTU ? (src1_value < src2_value) :
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isBGEU ? (src1_value >= src2_value) :
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1'b0;
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// Branch target calculation
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assign br_tgt_pc = pc + Bimm;
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// PC logic
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always @(posedge clk) begin
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if(rst) begin
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pc <= 32'h0;
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next_pc <= 32'h4;
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end
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else begin
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next_pc <= taken_br ? br_tgt_pc : (pc + 32'h4);
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pc <= next_pc;
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end
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end
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endmodule
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38
chapter4/RISCcore2TB.v
Normal file
38
chapter4/RISCcore2TB.v
Normal file
@@ -0,0 +1,38 @@
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module RISCcore2TB;
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reg clk;
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||||
reg rst;
|
||||
wire [31:0] pc;
|
||||
wire [31:0] next_pc;
|
||||
wire [31:0] instr;
|
||||
|
||||
// Instantiate RISC core
|
||||
RISCcore2 uut (
|
||||
.rst(rst),
|
||||
.clk(clk),
|
||||
.pc(pc),
|
||||
.next_pc(next_pc),
|
||||
.instr(instr)
|
||||
);
|
||||
|
||||
// Clock generation
|
||||
always #5 clk = ~clk;
|
||||
|
||||
// Monitor
|
||||
always @(posedge clk) begin
|
||||
$display("Time=%0t, PC=%h, Instr=%h", $time, pc, instr);
|
||||
if (pc == 32'h100) begin // End simulation after some time
|
||||
$display("Simulation completed successfully!");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
// Initialize
|
||||
initial begin
|
||||
clk = 0;
|
||||
rst = 1;
|
||||
#10 rst = 0;
|
||||
#200;
|
||||
$display("Test completed");
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
||||
@@ -58,15 +58,51 @@ wire [31:0] Jimm = {{12{instr[31]}}, {instr[19:12]}, {instr[20]}, {instr[30:25]}
|
||||
|
||||
//Instructions
|
||||
|
||||
isBEQ = (funct3 == 000 && isBType);
|
||||
isBNE = (funct3 == 001 && isBType);
|
||||
isBLT = (funct3 == 100 && isBType);
|
||||
isBGE = (funct3 == 101 && isBType);
|
||||
isBLTU = (funct3 == 110 && isBType);
|
||||
isBGEU = (funct3 == 111 && isBType);
|
||||
isBEQ = (funct3 == 3'b000 && isBType);
|
||||
isBNE = (funct3 == 3'b001 && isBType);
|
||||
isBLT = (funct3 == 3'b100 && isBType);
|
||||
isBGE = (funct3 == 3'b101 && isBType);
|
||||
isBLTU = (funct3 == 3'b110 && isBType);
|
||||
isBGEU = (funct3 == 3'b111 && isBType);
|
||||
|
||||
isADDI = (funct3 == 000 && isIType);
|
||||
isADDI = (funct3 == 3'b000 && isIType);
|
||||
|
||||
isADD = (funct7[5] == 0 && isRType);
|
||||
isADD = (funct7[5] == 1'b0 && isRType);
|
||||
|
||||
isLW = (funct3 == 3'b010 && isIType);
|
||||
isSW = (funct3 == 3'b010 && isSType);
|
||||
|
||||
//Register file
|
||||
|
||||
wire rf_wr_en;
|
||||
wire [4:0] rf_wr_index;
|
||||
wire [31:0] rf_wr_data;
|
||||
wire rf_rd_en1, rf_rd_en2;
|
||||
wire [4:0] rf_rd_index1, rf_rd_index2;
|
||||
|
||||
wire rf_rd_data1, rf_rd_data2;
|
||||
|
||||
wire src1_value, src2_value;
|
||||
|
||||
assign rf_rd_en1 = rs1Valid;
|
||||
assign rf_rd_en2 = rs2Valid;
|
||||
|
||||
assign rf_rd_index1 = rs1;
|
||||
assign rf_rd_index2 = rs2;
|
||||
|
||||
assign src1_value = rf_rd_data1;
|
||||
assign src2_value = rf_rd_data2;
|
||||
|
||||
/* Maybe write logic ?
|
||||
assign rf_wr_en = 1'b0;
|
||||
assign rf_wr_index = 5'b0;
|
||||
assign rf_wr_data = 32'b0;
|
||||
Disabled */
|
||||
|
||||
// ALU FOR ADD, ADDI
|
||||
wire [31:0] alu_result = 32'b0;
|
||||
wire [31:0] alu_op2 = isADDI ? Iimm : src2_value;
|
||||
|
||||
assign alu_result = (isADDI || isADD) ? (src1_value + alu_op2) : 32'b0;
|
||||
|
||||
endmodule
|
||||
|
||||
@@ -1,7 +1,20 @@
|
||||
// 0x00000000
|
||||
00001037
|
||||
00100093
|
||||
001081b3
|
||||
0010a023
|
||||
00108663
|
||||
00c0006f
|
||||
93 01 10 00 // addi x2, x0, 1 (x2 = 1)
|
||||
13 02 20 00 // addi x4, x0, 2 (x4 = 2)
|
||||
93 02 30 00 // addi x5, x0, 3 (x5 = 3)
|
||||
13 03 40 00 // addi x6, x0, 4 (x6 = 4)
|
||||
93 03 50 00 // addi x7, x0, 5 (x7 = 5)
|
||||
13 04 60 00 // addi x8, x0, 6 (x8 = 6)
|
||||
93 04 70 00 // addi x9, x0, 7 (x9 = 7)
|
||||
13 05 80 00 // addi x10, x0, 8 (x10 = 8)
|
||||
93 05 90 00 // addi x11, x0, 9 (x11 = 9)
|
||||
33 06 52 00 // add x12, x4, x5 (x12 = 2+3=5)
|
||||
b3 06 66 00 // add x13, x12, x6 (x13 = 5+4=9)
|
||||
33 07 77 00 // add x14, x14, x7 (x14 = 9+5=14)
|
||||
b3 07 88 00 // add x15, x16, x8 (x15 = 14+6=20)
|
||||
33 08 99 00 // add x16, x18, x9 (x16 = 20+7=27)
|
||||
b3 08 aa 00 // add x17, x17, x10 (x17 = 27+8=35)
|
||||
33 09 bb 00 // add x18, x18, x11 (x18 = 35+9=44)
|
||||
63 8a 09 00 // beq x18, x0, 20 (branch not taken)
|
||||
13 0a fa ff // addi x20, x0, -6 (x20 = -6)
|
||||
93 0a 0a 00 // addi x21, x0, 0 (x21 = 0)
|
||||
e3 9a 5a fe // blt x21, x5, -20 (loop if x21 < 3)
|
||||
|
||||
504
chapter4/riscv
Executable file
504
chapter4/riscv
Executable file
@@ -0,0 +1,504 @@
|
||||
#! /usr/bin/vvp
|
||||
:ivl_version "12.0 (stable)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "/usr/lib64/ivl/system.vpi";
|
||||
:vpi_module "/usr/lib64/ivl/vhdl_sys.vpi";
|
||||
:vpi_module "/usr/lib64/ivl/vhdl_textio.vpi";
|
||||
:vpi_module "/usr/lib64/ivl/v2005_math.vpi";
|
||||
:vpi_module "/usr/lib64/ivl/va_math.vpi";
|
||||
S_0x55d2c8557240 .scope module, "RISCcore2TB" "RISCcore2TB" 2 1;
|
||||
.timescale 0 0;
|
||||
v0x55d2c85cb040_0 .var "clk", 0 0;
|
||||
v0x55d2c85cb100_0 .net "instr", 31 0, L_0x55d2c85a4500; 1 drivers
|
||||
v0x55d2c85cb1a0_0 .net "next_pc", 31 0, v0x55d2c85c9cc0_0; 1 drivers
|
||||
v0x55d2c85cb240_0 .net "pc", 31 0, v0x55d2c85c9da0_0; 1 drivers
|
||||
v0x55d2c85cb2e0_0 .var "rst", 0 0;
|
||||
S_0x55d2c85933e0 .scope module, "uut" "RISCcore2" 2 9, 3 1 0, S_0x55d2c8557240;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "rst";
|
||||
.port_info 1 /INPUT 1 "clk";
|
||||
.port_info 2 /OUTPUT 32 "pc";
|
||||
.port_info 3 /OUTPUT 32 "next_pc";
|
||||
.port_info 4 /OUTPUT 32 "instr";
|
||||
L_0x55d2c85a4500 .functor BUFZ 32, L_0x55d2c85cb380, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
|
||||
L_0x55d2c85cba10 .functor OR 1, L_0x55d2c85cb6d0, L_0x55d2c85cb8e0, C4<0>, C4<0>;
|
||||
L_0x55d2c85cbfc0 .functor OR 1, L_0x55d2c85cbbc0, L_0x55d2c85cbdf0, C4<0>, C4<0>;
|
||||
L_0x55d2c85cc320 .functor OR 1, L_0x55d2c85cbfc0, L_0x55d2c85cc170, C4<0>, C4<0>;
|
||||
L_0x55d2c85cc2b0 .functor OR 1, L_0x55d2c85cc320, L_0x55d2c85cc500, C4<0>, C4<0>;
|
||||
L_0x55d2c85cc9d0 .functor OR 1, L_0x55d2c85cc2b0, L_0x55d2c85cc800, C4<0>, C4<0>;
|
||||
L_0x55d2c85ccfe0 .functor OR 1, L_0x55d2c85ccbc0, L_0x55d2c85cce40, C4<0>, C4<0>;
|
||||
L_0x55d2c85cd2f0 .functor OR 1, L_0x55d2c85ccfe0, L_0x55d2c85cd0f0, C4<0>, C4<0>;
|
||||
L_0x55d2c85cd9c0 .functor OR 1, L_0x55d2c85cd4f0, L_0x55d2c85cd7a0, C4<0>, C4<0>;
|
||||
L_0x55d2c85ce3d0 .functor OR 1, L_0x55d2c85cd2f0, L_0x55d2c85cd9c0, C4<0>, C4<0>;
|
||||
L_0x55d2c85ce570 .functor OR 1, L_0x55d2c85ce3d0, L_0x55d2c85cdb70, C4<0>, C4<0>;
|
||||
L_0x55d2c85ce630 .functor NOT 1, L_0x55d2c85cba10, C4<0>, C4<0>, C4<0>;
|
||||
L_0x55d2c85ce760 .functor NOT 1, L_0x55d2c85cde40, C4<0>, C4<0>, C4<0>;
|
||||
L_0x55d2c85ce820 .functor AND 1, L_0x55d2c85ce630, L_0x55d2c85ce760, C4<1>, C4<1>;
|
||||
L_0x55d2c85ce6f0 .functor NOT 1, L_0x55d2c85cd9c0, C4<0>, C4<0>, C4<0>;
|
||||
L_0x55d2c85ce930 .functor NOT 1, L_0x55d2c85cdb70, C4<0>, C4<0>, C4<0>;
|
||||
L_0x55d2c85cea30 .functor AND 1, L_0x55d2c85ce6f0, L_0x55d2c85ce930, C4<1>, C4<1>;
|
||||
L_0x55d2c85e2830 .functor AND 1, L_0x55d2c85e24e0, L_0x55d2c85cdb70, C4<1>, C4<1>;
|
||||
L_0x55d2c85e2a30 .functor AND 1, L_0x55d2c85e2990, L_0x55d2c85cdb70, C4<1>, C4<1>;
|
||||
L_0x55d2c85e2db0 .functor AND 1, L_0x55d2c85e2af0, L_0x55d2c85cdb70, C4<1>, C4<1>;
|
||||
L_0x55d2c85e2f70 .functor AND 1, L_0x55d2c85e28f0, L_0x55d2c85cdb70, C4<1>, C4<1>;
|
||||
L_0x55d2c85e3350 .functor AND 1, L_0x55d2c85e3030, L_0x55d2c85cdb70, C4<1>, C4<1>;
|
||||
L_0x55d2c85e35c0 .functor AND 1, L_0x55d2c85e34d0, L_0x55d2c85cdb70, C4<1>, C4<1>;
|
||||
L_0x55d2c85e3af0 .functor AND 1, L_0x55d2c85e3680, L_0x55d2c85cc9d0, C4<1>, C4<1>;
|
||||
L_0x7fa652ad8720 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||
L_0x55d2c85e3dc0 .functor XNOR 1, L_0x55d2c85e3cd0, L_0x7fa652ad8720, C4<0>, C4<0>;
|
||||
L_0x55d2c85e3ed0 .functor AND 1, L_0x55d2c85e3dc0, L_0x55d2c85cd2f0, C4<1>, C4<1>;
|
||||
L_0x55d2c85e43b0 .functor AND 1, L_0x55d2c85e3ed0, L_0x55d2c85e4070, C4<1>, C4<1>;
|
||||
L_0x55d2c85e44c0 .functor BUFZ 1, L_0x55d2c85ce820, C4<0>, C4<0>, C4<0>;
|
||||
L_0x55d2c85e4670 .functor BUFZ 1, L_0x55d2c85ce570, C4<0>, C4<0>, C4<0>;
|
||||
L_0x55d2c85e4730 .functor BUFZ 5, L_0x55d2c85ce0b0, C4<00000>, C4<00000>, C4<00000>;
|
||||
L_0x55d2c85e48f0 .functor BUFZ 5, L_0x55d2c85ce150, C4<00000>, C4<00000>, C4<00000>;
|
||||
o0x7fa65309bff8 .functor BUFZ 32, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
|
||||
L_0x55d2c85e49b0 .functor BUFZ 32, o0x7fa65309bff8, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
|
||||
o0x7fa65309c028 .functor BUFZ 32, C4<zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz>; HiZ drive
|
||||
L_0x55d2c85e4b30 .functor BUFZ 32, o0x7fa65309c028, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>, C4<00000000000000000000000000000000>;
|
||||
L_0x55d2c85e4dc0 .functor OR 1, L_0x55d2c85e3af0, L_0x55d2c85e43b0, C4<0>, C4<0>;
|
||||
L_0x55d2c85e5040 .functor OR 1, L_0x55d2c85e43b0, L_0x55d2c85e3af0, C4<0>, C4<0>;
|
||||
L_0x55d2c85e5920 .functor AND 1, L_0x55d2c85cea30, L_0x55d2c85e5040, C4<1>, C4<1>;
|
||||
L_0x55d2c85e5b60 .functor AND 1, L_0x55d2c85e5920, L_0x55d2c85e4e80, C4<1>, C4<1>;
|
||||
L_0x55d2c85e5cc0 .functor BUFZ 5, L_0x55d2c85ce300, C4<00000>, C4<00000>, C4<00000>;
|
||||
L_0x55d2c85e65b0 .functor AND 1, L_0x55d2c85e5e70, L_0x55d2c85e6230, C4<1>, C4<1>;
|
||||
L_0x55d2c85e6b40 .functor AND 1, L_0x55d2c85e6760, L_0x55d2c85e6aa0, C4<1>, C4<1>;
|
||||
L_0x55d2c85e7b80 .functor AND 1, L_0x55d2c85e7680, L_0x55d2c85e7a90, C4<1>, C4<1>;
|
||||
L_0x55d2c85e8490 .functor AND 1, L_0x55d2c85e8010, L_0x55d2c85e8100, C4<1>, C4<1>;
|
||||
v0x55d2c85a46a0_0 .net "Bimm", 31 0, L_0x55d2c85d0d00; 1 drivers
|
||||
v0x55d2c85c04c0_0 .net "Iimm", 31 0, L_0x55d2c85cf6c0; 1 drivers
|
||||
v0x55d2c85c05a0_0 .net "Jimm", 31 0, L_0x55d2c85e2280; 1 drivers
|
||||
v0x55d2c85c0660_0 .net "Simm", 31 0, L_0x55d2c85d00d0; 1 drivers
|
||||
v0x55d2c85c0740_0 .net "Uimm", 31 0, L_0x55d2c85e1470; 1 drivers
|
||||
v0x55d2c85c0870_0 .net *"_ivl_0", 31 0, L_0x55d2c85cb380; 1 drivers
|
||||
v0x55d2c85c0950_0 .net *"_ivl_10", 0 0, L_0x55d2c85cb6d0; 1 drivers
|
||||
v0x55d2c85c0a10_0 .net *"_ivl_101", 6 0, L_0x55d2c85cdda0; 1 drivers
|
||||
L_0x7fa652ad83c0 .functor BUFT 1, C4<1101111>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c0af0_0 .net/2u *"_ivl_102", 6 0, L_0x7fa652ad83c0; 1 drivers
|
||||
v0x55d2c85c0bd0_0 .net *"_ivl_113", 0 0, L_0x55d2c85ce3d0; 1 drivers
|
||||
v0x55d2c85c0c90_0 .net *"_ivl_116", 0 0, L_0x55d2c85ce630; 1 drivers
|
||||
v0x55d2c85c0d70_0 .net *"_ivl_118", 0 0, L_0x55d2c85ce760; 1 drivers
|
||||
v0x55d2c85c0e50_0 .net *"_ivl_122", 0 0, L_0x55d2c85ce6f0; 1 drivers
|
||||
v0x55d2c85c0f30_0 .net *"_ivl_124", 0 0, L_0x55d2c85ce930; 1 drivers
|
||||
v0x55d2c85c1010_0 .net *"_ivl_129", 2 0, L_0x55d2c85ceb40; 1 drivers
|
||||
v0x55d2c85c10f0_0 .net *"_ivl_13", 6 0, L_0x55d2c85cb840; 1 drivers
|
||||
L_0x7fa652ad8408 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c11d0_0 .net *"_ivl_133", 0 0, L_0x7fa652ad8408; 1 drivers
|
||||
v0x55d2c85c12b0_0 .net *"_ivl_137", 0 0, L_0x55d2c85cebe0; 1 drivers
|
||||
v0x55d2c85c1390_0 .net *"_ivl_138", 20 0, L_0x55d2c85cf010; 1 drivers
|
||||
L_0x7fa652ad8060 .functor BUFT 1, C4<0010111>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c1470_0 .net/2u *"_ivl_14", 6 0, L_0x7fa652ad8060; 1 drivers
|
||||
v0x55d2c85c1550_0 .net *"_ivl_141", 5 0, L_0x55d2c85cf400; 1 drivers
|
||||
v0x55d2c85c1630_0 .net *"_ivl_143", 4 0, L_0x55d2c85cf4a0; 1 drivers
|
||||
v0x55d2c85c1710_0 .net *"_ivl_147", 0 0, L_0x55d2c85cf860; 1 drivers
|
||||
v0x55d2c85c17f0_0 .net *"_ivl_148", 20 0, L_0x55d2c85cfa60; 1 drivers
|
||||
v0x55d2c85c18d0_0 .net *"_ivl_151", 5 0, L_0x55d2c85cfe20; 1 drivers
|
||||
v0x55d2c85c19b0_0 .net *"_ivl_153", 4 0, L_0x55d2c85d0030; 1 drivers
|
||||
v0x55d2c85c1a90_0 .net *"_ivl_157", 0 0, L_0x55d2c85d03f0; 1 drivers
|
||||
v0x55d2c85c1b70_0 .net *"_ivl_158", 19 0, L_0x55d2c85d0490; 1 drivers
|
||||
v0x55d2c85c1c50_0 .net *"_ivl_16", 0 0, L_0x55d2c85cb8e0; 1 drivers
|
||||
v0x55d2c85c1d10_0 .net *"_ivl_161", 0 0, L_0x55d2c85d0920; 1 drivers
|
||||
v0x55d2c85c1df0_0 .net *"_ivl_163", 5 0, L_0x55d2c85d09c0; 1 drivers
|
||||
v0x55d2c85c1ed0_0 .net *"_ivl_165", 3 0, L_0x55d2c85d0c00; 1 drivers
|
||||
L_0x7fa652ad8450 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c1fb0_0 .net/2u *"_ivl_166", 0 0, L_0x7fa652ad8450; 1 drivers
|
||||
v0x55d2c85c22a0_0 .net *"_ivl_171", 0 0, L_0x55d2c85d10c0; 1 drivers
|
||||
v0x55d2c85c2380_0 .net *"_ivl_173", 10 0, L_0x55d2c85d1160; 1 drivers
|
||||
v0x55d2c85c2460_0 .net *"_ivl_175", 7 0, L_0x55d2c85d13c0; 1 drivers
|
||||
L_0x7fa652ad8498 .functor BUFT 1, C4<000000000000>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c2540_0 .net/2u *"_ivl_176", 11 0, L_0x7fa652ad8498; 1 drivers
|
||||
v0x55d2c85c2620_0 .net *"_ivl_181", 0 0, L_0x55d2c85e17d0; 1 drivers
|
||||
v0x55d2c85c2700_0 .net *"_ivl_182", 11 0, L_0x55d2c85e1870; 1 drivers
|
||||
v0x55d2c85c27e0_0 .net *"_ivl_185", 7 0, L_0x55d2c85e1bb0; 1 drivers
|
||||
v0x55d2c85c28c0_0 .net *"_ivl_187", 0 0, L_0x55d2c85e1c50; 1 drivers
|
||||
v0x55d2c85c29a0_0 .net *"_ivl_189", 5 0, L_0x55d2c85e1ee0; 1 drivers
|
||||
v0x55d2c85c2a80_0 .net *"_ivl_191", 3 0, L_0x55d2c85e1f80; 1 drivers
|
||||
L_0x7fa652ad84e0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c2b60_0 .net/2u *"_ivl_192", 0 0, L_0x7fa652ad84e0; 1 drivers
|
||||
L_0x7fa652ad8528 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c2c40_0 .net/2u *"_ivl_196", 3 0, L_0x7fa652ad8528; 1 drivers
|
||||
v0x55d2c85c2d20_0 .net *"_ivl_198", 0 0, L_0x55d2c85e24e0; 1 drivers
|
||||
L_0x7fa652ad8570 .functor BUFT 1, C4<0001>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c2de0_0 .net/2u *"_ivl_202", 3 0, L_0x7fa652ad8570; 1 drivers
|
||||
v0x55d2c85c2ec0_0 .net *"_ivl_204", 0 0, L_0x55d2c85e2990; 1 drivers
|
||||
L_0x7fa652ad85b8 .functor BUFT 1, C4<0100>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c2f80_0 .net/2u *"_ivl_208", 3 0, L_0x7fa652ad85b8; 1 drivers
|
||||
v0x55d2c85c3060_0 .net *"_ivl_21", 6 0, L_0x55d2c85cbb20; 1 drivers
|
||||
v0x55d2c85c3140_0 .net *"_ivl_210", 0 0, L_0x55d2c85e2af0; 1 drivers
|
||||
L_0x7fa652ad8600 .functor BUFT 1, C4<0101>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c3200_0 .net/2u *"_ivl_214", 3 0, L_0x7fa652ad8600; 1 drivers
|
||||
v0x55d2c85c32e0_0 .net *"_ivl_216", 0 0, L_0x55d2c85e28f0; 1 drivers
|
||||
L_0x7fa652ad80a8 .functor BUFT 1, C4<0000011>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c33a0_0 .net/2u *"_ivl_22", 6 0, L_0x7fa652ad80a8; 1 drivers
|
||||
L_0x7fa652ad8648 .functor BUFT 1, C4<0110>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c3480_0 .net/2u *"_ivl_220", 3 0, L_0x7fa652ad8648; 1 drivers
|
||||
v0x55d2c85c3560_0 .net *"_ivl_222", 0 0, L_0x55d2c85e3030; 1 drivers
|
||||
L_0x7fa652ad8690 .functor BUFT 1, C4<0111>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c3620_0 .net/2u *"_ivl_226", 3 0, L_0x7fa652ad8690; 1 drivers
|
||||
v0x55d2c85c3700_0 .net *"_ivl_228", 0 0, L_0x55d2c85e34d0; 1 drivers
|
||||
L_0x7fa652ad86d8 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c37c0_0 .net/2u *"_ivl_232", 3 0, L_0x7fa652ad86d8; 1 drivers
|
||||
v0x55d2c85c38a0_0 .net *"_ivl_234", 0 0, L_0x55d2c85e3680; 1 drivers
|
||||
v0x55d2c85c3960_0 .net *"_ivl_239", 0 0, L_0x55d2c85e3cd0; 1 drivers
|
||||
v0x55d2c85c3a40_0 .net *"_ivl_24", 0 0, L_0x55d2c85cbbc0; 1 drivers
|
||||
v0x55d2c85c3b00_0 .net/2u *"_ivl_240", 0 0, L_0x7fa652ad8720; 1 drivers
|
||||
v0x55d2c85c3be0_0 .net *"_ivl_242", 0 0, L_0x55d2c85e3dc0; 1 drivers
|
||||
v0x55d2c85c3ca0_0 .net *"_ivl_245", 0 0, L_0x55d2c85e3ed0; 1 drivers
|
||||
L_0x7fa652ad8768 .functor BUFT 1, C4<0000>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c4170_0 .net/2u *"_ivl_246", 3 0, L_0x7fa652ad8768; 1 drivers
|
||||
v0x55d2c85c4250_0 .net *"_ivl_248", 0 0, L_0x55d2c85e4070; 1 drivers
|
||||
v0x55d2c85c4310_0 .net *"_ivl_267", 0 0, L_0x55d2c85e4dc0; 1 drivers
|
||||
v0x55d2c85c43d0_0 .net *"_ivl_268", 31 0, L_0x55d2c85e4fa0; 1 drivers
|
||||
v0x55d2c85c44b0_0 .net *"_ivl_27", 6 0, L_0x55d2c85cbd50; 1 drivers
|
||||
L_0x7fa652ad87b0 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c4590_0 .net/2u *"_ivl_270", 31 0, L_0x7fa652ad87b0; 1 drivers
|
||||
L_0x7fa652ad87f8 .functor BUFT 1, C4<00000000000000000000000000000000>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c4670_0 .net/2u *"_ivl_274", 31 0, L_0x7fa652ad87f8; 1 drivers
|
||||
v0x55d2c85c4750_0 .net *"_ivl_279", 0 0, L_0x55d2c85e5040; 1 drivers
|
||||
L_0x7fa652ad80f0 .functor BUFT 1, C4<0000111>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c4810_0 .net/2u *"_ivl_28", 6 0, L_0x7fa652ad80f0; 1 drivers
|
||||
v0x55d2c85c48f0_0 .net *"_ivl_281", 0 0, L_0x55d2c85e5920; 1 drivers
|
||||
L_0x7fa652ad8840 .functor BUFT 1, C4<00000>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c49b0_0 .net/2u *"_ivl_282", 4 0, L_0x7fa652ad8840; 1 drivers
|
||||
v0x55d2c85c4a90_0 .net *"_ivl_284", 0 0, L_0x55d2c85e4e80; 1 drivers
|
||||
v0x55d2c85c4b50_0 .net *"_ivl_291", 0 0, L_0x55d2c85e5e70; 1 drivers
|
||||
v0x55d2c85c4c30_0 .net *"_ivl_293", 0 0, L_0x55d2c85e6190; 1 drivers
|
||||
v0x55d2c85c4d10_0 .net *"_ivl_295", 0 0, L_0x55d2c85e6230; 1 drivers
|
||||
v0x55d2c85c4dd0_0 .net *"_ivl_297", 0 0, L_0x55d2c85e65b0; 1 drivers
|
||||
L_0x7fa652ad8888 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c4e90_0 .net/2u *"_ivl_298", 0 0, L_0x7fa652ad8888; 1 drivers
|
||||
v0x55d2c85c4f70_0 .net *"_ivl_3", 29 0, L_0x55d2c85cb450; 1 drivers
|
||||
v0x55d2c85c5050_0 .net *"_ivl_30", 0 0, L_0x55d2c85cbdf0; 1 drivers
|
||||
v0x55d2c85c5110_0 .net *"_ivl_301", 0 0, L_0x55d2c85e66c0; 1 drivers
|
||||
v0x55d2c85c51f0_0 .net *"_ivl_303", 0 0, L_0x55d2c85e6760; 1 drivers
|
||||
v0x55d2c85c52b0_0 .net *"_ivl_305", 0 0, L_0x55d2c85e6aa0; 1 drivers
|
||||
v0x55d2c85c5390_0 .net *"_ivl_307", 0 0, L_0x55d2c85e6b40; 1 drivers
|
||||
L_0x7fa652ad88d0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c5450_0 .net/2u *"_ivl_308", 0 0, L_0x7fa652ad88d0; 1 drivers
|
||||
v0x55d2c85c5530_0 .net *"_ivl_310", 0 0, L_0x55d2c85e6d50; 1 drivers
|
||||
v0x55d2c85c55f0_0 .net *"_ivl_312", 0 0, L_0x55d2c85e70a0; 1 drivers
|
||||
v0x55d2c85c56d0_0 .net *"_ivl_317", 0 0, L_0x55d2c85e7680; 1 drivers
|
||||
v0x55d2c85c57b0_0 .net *"_ivl_319", 0 0, L_0x55d2c85e7720; 1 drivers
|
||||
v0x55d2c85c5890_0 .net *"_ivl_321", 0 0, L_0x55d2c85e7a90; 1 drivers
|
||||
v0x55d2c85c5950_0 .net *"_ivl_323", 0 0, L_0x55d2c85e7b80; 1 drivers
|
||||
L_0x7fa652ad8918 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c5a10_0 .net/2u *"_ivl_324", 0 0, L_0x7fa652ad8918; 1 drivers
|
||||
v0x55d2c85c5af0_0 .net *"_ivl_327", 0 0, L_0x55d2c85e7c90; 1 drivers
|
||||
v0x55d2c85c5bd0_0 .net *"_ivl_329", 0 0, L_0x55d2c85e8010; 1 drivers
|
||||
v0x55d2c85c5c90_0 .net *"_ivl_33", 0 0, L_0x55d2c85cbfc0; 1 drivers
|
||||
v0x55d2c85c5d50_0 .net *"_ivl_331", 0 0, L_0x55d2c85e8100; 1 drivers
|
||||
v0x55d2c85c5e30_0 .net *"_ivl_333", 0 0, L_0x55d2c85e8490; 1 drivers
|
||||
L_0x7fa652ad8960 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c5ef0_0 .net/2u *"_ivl_334", 0 0, L_0x7fa652ad8960; 1 drivers
|
||||
v0x55d2c85c5fd0_0 .net *"_ivl_336", 0 0, L_0x55d2c85e8700; 1 drivers
|
||||
v0x55d2c85c6090_0 .net *"_ivl_338", 0 0, L_0x55d2c85e87a0; 1 drivers
|
||||
v0x55d2c85c6170_0 .net *"_ivl_342", 0 0, L_0x55d2c85e8dc0; 1 drivers
|
||||
v0x55d2c85c6230_0 .net *"_ivl_344", 0 0, L_0x55d2c85e9170; 1 drivers
|
||||
v0x55d2c85c62f0_0 .net *"_ivl_346", 0 0, L_0x55d2c85e9210; 1 drivers
|
||||
v0x55d2c85c63b0_0 .net *"_ivl_348", 0 0, L_0x55d2c85e95d0; 1 drivers
|
||||
v0x55d2c85c6470_0 .net *"_ivl_35", 6 0, L_0x55d2c85cc080; 1 drivers
|
||||
L_0x7fa652ad89a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c6550_0 .net/2u *"_ivl_350", 0 0, L_0x7fa652ad89a8; 1 drivers
|
||||
v0x55d2c85c6630_0 .net *"_ivl_352", 0 0, L_0x55d2c85e9670; 1 drivers
|
||||
v0x55d2c85c6710_0 .net *"_ivl_354", 0 0, L_0x55d2c85e9b60; 1 drivers
|
||||
v0x55d2c85c67f0_0 .net *"_ivl_356", 0 0, L_0x55d2c85e9cf0; 1 drivers
|
||||
v0x55d2c85c68d0_0 .net *"_ivl_358", 0 0, L_0x55d2c85ea1c0; 1 drivers
|
||||
L_0x7fa652ad8138 .functor BUFT 1, C4<0010011>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c69b0_0 .net/2u *"_ivl_36", 6 0, L_0x7fa652ad8138; 1 drivers
|
||||
v0x55d2c85c6a90_0 .net *"_ivl_360", 0 0, L_0x55d2c85ea350; 1 drivers
|
||||
v0x55d2c85c6b70_0 .net *"_ivl_38", 0 0, L_0x55d2c85cc170; 1 drivers
|
||||
v0x55d2c85c6c30_0 .net *"_ivl_41", 0 0, L_0x55d2c85cc320; 1 drivers
|
||||
v0x55d2c85c6cf0_0 .net *"_ivl_43", 6 0, L_0x55d2c85cc460; 1 drivers
|
||||
L_0x7fa652ad8180 .functor BUFT 1, C4<0011011>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c6dd0_0 .net/2u *"_ivl_44", 6 0, L_0x7fa652ad8180; 1 drivers
|
||||
v0x55d2c85c6eb0_0 .net *"_ivl_46", 0 0, L_0x55d2c85cc500; 1 drivers
|
||||
v0x55d2c85c6f70_0 .net *"_ivl_49", 0 0, L_0x55d2c85cc2b0; 1 drivers
|
||||
v0x55d2c85c7030_0 .net *"_ivl_51", 6 0, L_0x55d2c85cc760; 1 drivers
|
||||
L_0x7fa652ad81c8 .functor BUFT 1, C4<1100111>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c7110_0 .net/2u *"_ivl_52", 6 0, L_0x7fa652ad81c8; 1 drivers
|
||||
v0x55d2c85c71f0_0 .net *"_ivl_54", 0 0, L_0x55d2c85cc800; 1 drivers
|
||||
v0x55d2c85c72b0_0 .net *"_ivl_59", 6 0, L_0x55d2c85ccb20; 1 drivers
|
||||
L_0x7fa652ad8210 .functor BUFT 1, C4<0101111>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c7390_0 .net/2u *"_ivl_60", 6 0, L_0x7fa652ad8210; 1 drivers
|
||||
v0x55d2c85c7470_0 .net *"_ivl_62", 0 0, L_0x55d2c85ccbc0; 1 drivers
|
||||
v0x55d2c85c7530_0 .net *"_ivl_65", 6 0, L_0x55d2c85ccda0; 1 drivers
|
||||
L_0x7fa652ad8258 .functor BUFT 1, C4<0110011>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c7e20_0 .net/2u *"_ivl_66", 6 0, L_0x7fa652ad8258; 1 drivers
|
||||
v0x55d2c85c7f00_0 .net *"_ivl_68", 0 0, L_0x55d2c85cce40; 1 drivers
|
||||
v0x55d2c85c7fc0_0 .net *"_ivl_7", 6 0, L_0x55d2c85cb630; 1 drivers
|
||||
v0x55d2c85c80a0_0 .net *"_ivl_71", 0 0, L_0x55d2c85ccfe0; 1 drivers
|
||||
v0x55d2c85c8160_0 .net *"_ivl_73", 6 0, L_0x55d2c85ccd00; 1 drivers
|
||||
L_0x7fa652ad82a0 .functor BUFT 1, C4<0111011>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c8240_0 .net/2u *"_ivl_74", 6 0, L_0x7fa652ad82a0; 1 drivers
|
||||
v0x55d2c85c8320_0 .net *"_ivl_76", 0 0, L_0x55d2c85cd0f0; 1 drivers
|
||||
L_0x7fa652ad8018 .functor BUFT 1, C4<0110111>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c83e0_0 .net/2u *"_ivl_8", 6 0, L_0x7fa652ad8018; 1 drivers
|
||||
v0x55d2c85c84c0_0 .net *"_ivl_81", 6 0, L_0x55d2c85cd450; 1 drivers
|
||||
L_0x7fa652ad82e8 .functor BUFT 1, C4<0100011>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c85a0_0 .net/2u *"_ivl_82", 6 0, L_0x7fa652ad82e8; 1 drivers
|
||||
v0x55d2c85c8680_0 .net *"_ivl_84", 0 0, L_0x55d2c85cd4f0; 1 drivers
|
||||
v0x55d2c85c8740_0 .net *"_ivl_87", 6 0, L_0x55d2c85cd700; 1 drivers
|
||||
L_0x7fa652ad8330 .functor BUFT 1, C4<0100111>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c8820_0 .net/2u *"_ivl_88", 6 0, L_0x7fa652ad8330; 1 drivers
|
||||
v0x55d2c85c8900_0 .net *"_ivl_90", 0 0, L_0x55d2c85cd7a0; 1 drivers
|
||||
v0x55d2c85c89c0_0 .net *"_ivl_95", 6 0, L_0x55d2c85cdad0; 1 drivers
|
||||
L_0x7fa652ad8378 .functor BUFT 1, C4<1100011>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55d2c85c8aa0_0 .net/2u *"_ivl_96", 6 0, L_0x7fa652ad8378; 1 drivers
|
||||
v0x55d2c85c8b80_0 .net "alu_op2", 31 0, L_0x55d2c85e4c00; 1 drivers
|
||||
v0x55d2c85c8c60_0 .net "alu_result", 31 0, L_0x55d2c85e53e0; 1 drivers
|
||||
v0x55d2c85c8d40_0 .net "br_tgt_pc", 31 0, L_0x55d2c85ea9c0; 1 drivers
|
||||
v0x55d2c85c8e20_0 .net "clk", 0 0, v0x55d2c85cb040_0; 1 drivers
|
||||
v0x55d2c85c8ee0_0 .net "funct3", 3 0, L_0x55d2c85ced00; 1 drivers
|
||||
v0x55d2c85c8fc0_0 .net "funct7", 6 0, L_0x55d2c85cee40; 1 drivers
|
||||
v0x55d2c85c90a0 .array "imem", 255 0, 31 0;
|
||||
v0x55d2c85c9160_0 .net "instr", 31 0, L_0x55d2c85a4500; alias, 1 drivers
|
||||
v0x55d2c85c9240_0 .net "isADD", 0 0, L_0x55d2c85e43b0; 1 drivers
|
||||
v0x55d2c85c9300_0 .net "isADDI", 0 0, L_0x55d2c85e3af0; 1 drivers
|
||||
v0x55d2c85c93c0_0 .net "isBEQ", 0 0, L_0x55d2c85e2830; 1 drivers
|
||||
v0x55d2c85c9480_0 .net "isBGE", 0 0, L_0x55d2c85e2f70; 1 drivers
|
||||
v0x55d2c85c9540_0 .net "isBGEU", 0 0, L_0x55d2c85e35c0; 1 drivers
|
||||
v0x55d2c85c9600_0 .net "isBLT", 0 0, L_0x55d2c85e2db0; 1 drivers
|
||||
v0x55d2c85c96c0_0 .net "isBLTU", 0 0, L_0x55d2c85e3350; 1 drivers
|
||||
v0x55d2c85c9780_0 .net "isBNE", 0 0, L_0x55d2c85e2a30; 1 drivers
|
||||
v0x55d2c85c9840_0 .net "isBType", 0 0, L_0x55d2c85cdb70; 1 drivers
|
||||
v0x55d2c85c9900_0 .net "isIType", 0 0, L_0x55d2c85cc9d0; 1 drivers
|
||||
v0x55d2c85c99c0_0 .net "isJType", 0 0, L_0x55d2c85cde40; 1 drivers
|
||||
v0x55d2c85c9a80_0 .net "isRType", 0 0, L_0x55d2c85cd2f0; 1 drivers
|
||||
v0x55d2c85c9b40_0 .net "isSType", 0 0, L_0x55d2c85cd9c0; 1 drivers
|
||||
v0x55d2c85c9c00_0 .net "isUType", 0 0, L_0x55d2c85cba10; 1 drivers
|
||||
v0x55d2c85c9cc0_0 .var "next_pc", 31 0;
|
||||
v0x55d2c85c9da0_0 .var "pc", 31 0;
|
||||
v0x55d2c85c9e80_0 .net "rd", 4 0, L_0x55d2c85ce300; 1 drivers
|
||||
v0x55d2c85c9f60_0 .net "rdValid", 0 0, L_0x55d2c85cea30; 1 drivers
|
||||
v0x55d2c85ca020_0 .net "rf_rd_data1", 31 0, o0x7fa65309bff8; 0 drivers
|
||||
v0x55d2c85ca100_0 .net "rf_rd_data2", 31 0, o0x7fa65309c028; 0 drivers
|
||||
v0x55d2c85ca1e0_0 .net "rf_rd_en1", 0 0, L_0x55d2c85e44c0; 1 drivers
|
||||
v0x55d2c85ca2a0_0 .net "rf_rd_en2", 0 0, L_0x55d2c85e4670; 1 drivers
|
||||
v0x55d2c85ca360_0 .net "rf_rd_index1", 4 0, L_0x55d2c85e4730; 1 drivers
|
||||
v0x55d2c85ca440_0 .net "rf_rd_index2", 4 0, L_0x55d2c85e48f0; 1 drivers
|
||||
v0x55d2c85ca520_0 .net "rf_wr_data", 31 0, L_0x55d2c85e5570; 1 drivers
|
||||
v0x55d2c85ca600_0 .net "rf_wr_en", 0 0, L_0x55d2c85e5b60; 1 drivers
|
||||
v0x55d2c85ca6c0_0 .net "rf_wr_index", 4 0, L_0x55d2c85e5cc0; 1 drivers
|
||||
v0x55d2c85ca7a0_0 .net "rs1", 4 0, L_0x55d2c85ce0b0; 1 drivers
|
||||
v0x55d2c85ca880_0 .net "rs1Valid", 0 0, L_0x55d2c85ce820; 1 drivers
|
||||
v0x55d2c85ca940_0 .net "rs2", 4 0, L_0x55d2c85ce150; 1 drivers
|
||||
v0x55d2c85caa20_0 .net "rs2Valid", 0 0, L_0x55d2c85ce570; 1 drivers
|
||||
v0x55d2c85caae0_0 .net "rst", 0 0, v0x55d2c85cb2e0_0; 1 drivers
|
||||
v0x55d2c85caba0_0 .net "signed_ge", 0 0, L_0x55d2c85e8c30; 1 drivers
|
||||
v0x55d2c85cac60_0 .net "signed_lt", 0 0, L_0x55d2c85e7230; 1 drivers
|
||||
v0x55d2c85cad20_0 .net "src1_value", 31 0, L_0x55d2c85e49b0; 1 drivers
|
||||
v0x55d2c85cae00_0 .net "src2_value", 31 0, L_0x55d2c85e4b30; 1 drivers
|
||||
v0x55d2c85caee0_0 .net "taken_br", 0 0, L_0x55d2c85ea830; 1 drivers
|
||||
E_0x55d2c857c4c0 .event posedge, v0x55d2c85c8e20_0;
|
||||
L_0x55d2c85cb380 .array/port v0x55d2c85c90a0, L_0x55d2c85cb450;
|
||||
L_0x55d2c85cb450 .part v0x55d2c85c9da0_0, 2, 30;
|
||||
L_0x55d2c85cb630 .part L_0x55d2c85a4500, 0, 7;
|
||||
L_0x55d2c85cb6d0 .cmp/eq 7, L_0x55d2c85cb630, L_0x7fa652ad8018;
|
||||
L_0x55d2c85cb840 .part L_0x55d2c85a4500, 0, 7;
|
||||
L_0x55d2c85cb8e0 .cmp/eq 7, L_0x55d2c85cb840, L_0x7fa652ad8060;
|
||||
L_0x55d2c85cbb20 .part L_0x55d2c85a4500, 0, 7;
|
||||
L_0x55d2c85cbbc0 .cmp/eq 7, L_0x55d2c85cbb20, L_0x7fa652ad80a8;
|
||||
L_0x55d2c85cbd50 .part L_0x55d2c85a4500, 0, 7;
|
||||
L_0x55d2c85cbdf0 .cmp/eq 7, L_0x55d2c85cbd50, L_0x7fa652ad80f0;
|
||||
L_0x55d2c85cc080 .part L_0x55d2c85a4500, 0, 7;
|
||||
L_0x55d2c85cc170 .cmp/eq 7, L_0x55d2c85cc080, L_0x7fa652ad8138;
|
||||
L_0x55d2c85cc460 .part L_0x55d2c85a4500, 0, 7;
|
||||
L_0x55d2c85cc500 .cmp/eq 7, L_0x55d2c85cc460, L_0x7fa652ad8180;
|
||||
L_0x55d2c85cc760 .part L_0x55d2c85a4500, 0, 7;
|
||||
L_0x55d2c85cc800 .cmp/eq 7, L_0x55d2c85cc760, L_0x7fa652ad81c8;
|
||||
L_0x55d2c85ccb20 .part L_0x55d2c85a4500, 0, 7;
|
||||
L_0x55d2c85ccbc0 .cmp/eq 7, L_0x55d2c85ccb20, L_0x7fa652ad8210;
|
||||
L_0x55d2c85ccda0 .part L_0x55d2c85a4500, 0, 7;
|
||||
L_0x55d2c85cce40 .cmp/eq 7, L_0x55d2c85ccda0, L_0x7fa652ad8258;
|
||||
L_0x55d2c85ccd00 .part L_0x55d2c85a4500, 0, 7;
|
||||
L_0x55d2c85cd0f0 .cmp/eq 7, L_0x55d2c85ccd00, L_0x7fa652ad82a0;
|
||||
L_0x55d2c85cd450 .part L_0x55d2c85a4500, 0, 7;
|
||||
L_0x55d2c85cd4f0 .cmp/eq 7, L_0x55d2c85cd450, L_0x7fa652ad82e8;
|
||||
L_0x55d2c85cd700 .part L_0x55d2c85a4500, 0, 7;
|
||||
L_0x55d2c85cd7a0 .cmp/eq 7, L_0x55d2c85cd700, L_0x7fa652ad8330;
|
||||
L_0x55d2c85cdad0 .part L_0x55d2c85a4500, 0, 7;
|
||||
L_0x55d2c85cdb70 .cmp/eq 7, L_0x55d2c85cdad0, L_0x7fa652ad8378;
|
||||
L_0x55d2c85cdda0 .part L_0x55d2c85a4500, 0, 7;
|
||||
L_0x55d2c85cde40 .cmp/eq 7, L_0x55d2c85cdda0, L_0x7fa652ad83c0;
|
||||
L_0x55d2c85ce0b0 .part L_0x55d2c85a4500, 15, 5;
|
||||
L_0x55d2c85ce150 .part L_0x55d2c85a4500, 20, 5;
|
||||
L_0x55d2c85ce300 .part L_0x55d2c85a4500, 7, 5;
|
||||
L_0x55d2c85ceb40 .part L_0x55d2c85a4500, 12, 3;
|
||||
L_0x55d2c85ced00 .concat [ 3 1 0 0], L_0x55d2c85ceb40, L_0x7fa652ad8408;
|
||||
L_0x55d2c85cee40 .part L_0x55d2c85a4500, 25, 7;
|
||||
L_0x55d2c85cebe0 .part L_0x55d2c85a4500, 31, 1;
|
||||
LS_0x55d2c85cf010_0_0 .concat [ 1 1 1 1], L_0x55d2c85cebe0, L_0x55d2c85cebe0, L_0x55d2c85cebe0, L_0x55d2c85cebe0;
|
||||
LS_0x55d2c85cf010_0_4 .concat [ 1 1 1 1], L_0x55d2c85cebe0, L_0x55d2c85cebe0, L_0x55d2c85cebe0, L_0x55d2c85cebe0;
|
||||
LS_0x55d2c85cf010_0_8 .concat [ 1 1 1 1], L_0x55d2c85cebe0, L_0x55d2c85cebe0, L_0x55d2c85cebe0, L_0x55d2c85cebe0;
|
||||
LS_0x55d2c85cf010_0_12 .concat [ 1 1 1 1], L_0x55d2c85cebe0, L_0x55d2c85cebe0, L_0x55d2c85cebe0, L_0x55d2c85cebe0;
|
||||
LS_0x55d2c85cf010_0_16 .concat [ 1 1 1 1], L_0x55d2c85cebe0, L_0x55d2c85cebe0, L_0x55d2c85cebe0, L_0x55d2c85cebe0;
|
||||
LS_0x55d2c85cf010_0_20 .concat [ 1 0 0 0], L_0x55d2c85cebe0;
|
||||
LS_0x55d2c85cf010_1_0 .concat [ 4 4 4 4], LS_0x55d2c85cf010_0_0, LS_0x55d2c85cf010_0_4, LS_0x55d2c85cf010_0_8, LS_0x55d2c85cf010_0_12;
|
||||
LS_0x55d2c85cf010_1_4 .concat [ 4 1 0 0], LS_0x55d2c85cf010_0_16, LS_0x55d2c85cf010_0_20;
|
||||
L_0x55d2c85cf010 .concat [ 16 5 0 0], LS_0x55d2c85cf010_1_0, LS_0x55d2c85cf010_1_4;
|
||||
L_0x55d2c85cf400 .part L_0x55d2c85a4500, 25, 6;
|
||||
L_0x55d2c85cf4a0 .part L_0x55d2c85a4500, 20, 5;
|
||||
L_0x55d2c85cf6c0 .concat [ 5 6 21 0], L_0x55d2c85cf4a0, L_0x55d2c85cf400, L_0x55d2c85cf010;
|
||||
L_0x55d2c85cf860 .part L_0x55d2c85a4500, 31, 1;
|
||||
LS_0x55d2c85cfa60_0_0 .concat [ 1 1 1 1], L_0x55d2c85cf860, L_0x55d2c85cf860, L_0x55d2c85cf860, L_0x55d2c85cf860;
|
||||
LS_0x55d2c85cfa60_0_4 .concat [ 1 1 1 1], L_0x55d2c85cf860, L_0x55d2c85cf860, L_0x55d2c85cf860, L_0x55d2c85cf860;
|
||||
LS_0x55d2c85cfa60_0_8 .concat [ 1 1 1 1], L_0x55d2c85cf860, L_0x55d2c85cf860, L_0x55d2c85cf860, L_0x55d2c85cf860;
|
||||
LS_0x55d2c85cfa60_0_12 .concat [ 1 1 1 1], L_0x55d2c85cf860, L_0x55d2c85cf860, L_0x55d2c85cf860, L_0x55d2c85cf860;
|
||||
LS_0x55d2c85cfa60_0_16 .concat [ 1 1 1 1], L_0x55d2c85cf860, L_0x55d2c85cf860, L_0x55d2c85cf860, L_0x55d2c85cf860;
|
||||
LS_0x55d2c85cfa60_0_20 .concat [ 1 0 0 0], L_0x55d2c85cf860;
|
||||
LS_0x55d2c85cfa60_1_0 .concat [ 4 4 4 4], LS_0x55d2c85cfa60_0_0, LS_0x55d2c85cfa60_0_4, LS_0x55d2c85cfa60_0_8, LS_0x55d2c85cfa60_0_12;
|
||||
LS_0x55d2c85cfa60_1_4 .concat [ 4 1 0 0], LS_0x55d2c85cfa60_0_16, LS_0x55d2c85cfa60_0_20;
|
||||
L_0x55d2c85cfa60 .concat [ 16 5 0 0], LS_0x55d2c85cfa60_1_0, LS_0x55d2c85cfa60_1_4;
|
||||
L_0x55d2c85cfe20 .part L_0x55d2c85a4500, 25, 6;
|
||||
L_0x55d2c85d0030 .part L_0x55d2c85a4500, 7, 5;
|
||||
L_0x55d2c85d00d0 .concat [ 5 6 21 0], L_0x55d2c85d0030, L_0x55d2c85cfe20, L_0x55d2c85cfa60;
|
||||
L_0x55d2c85d03f0 .part L_0x55d2c85a4500, 31, 1;
|
||||
LS_0x55d2c85d0490_0_0 .concat [ 1 1 1 1], L_0x55d2c85d03f0, L_0x55d2c85d03f0, L_0x55d2c85d03f0, L_0x55d2c85d03f0;
|
||||
LS_0x55d2c85d0490_0_4 .concat [ 1 1 1 1], L_0x55d2c85d03f0, L_0x55d2c85d03f0, L_0x55d2c85d03f0, L_0x55d2c85d03f0;
|
||||
LS_0x55d2c85d0490_0_8 .concat [ 1 1 1 1], L_0x55d2c85d03f0, L_0x55d2c85d03f0, L_0x55d2c85d03f0, L_0x55d2c85d03f0;
|
||||
LS_0x55d2c85d0490_0_12 .concat [ 1 1 1 1], L_0x55d2c85d03f0, L_0x55d2c85d03f0, L_0x55d2c85d03f0, L_0x55d2c85d03f0;
|
||||
LS_0x55d2c85d0490_0_16 .concat [ 1 1 1 1], L_0x55d2c85d03f0, L_0x55d2c85d03f0, L_0x55d2c85d03f0, L_0x55d2c85d03f0;
|
||||
LS_0x55d2c85d0490_1_0 .concat [ 4 4 4 4], LS_0x55d2c85d0490_0_0, LS_0x55d2c85d0490_0_4, LS_0x55d2c85d0490_0_8, LS_0x55d2c85d0490_0_12;
|
||||
LS_0x55d2c85d0490_1_4 .concat [ 4 0 0 0], LS_0x55d2c85d0490_0_16;
|
||||
L_0x55d2c85d0490 .concat [ 16 4 0 0], LS_0x55d2c85d0490_1_0, LS_0x55d2c85d0490_1_4;
|
||||
L_0x55d2c85d0920 .part L_0x55d2c85a4500, 7, 1;
|
||||
L_0x55d2c85d09c0 .part L_0x55d2c85a4500, 25, 6;
|
||||
L_0x55d2c85d0c00 .part L_0x55d2c85a4500, 8, 4;
|
||||
LS_0x55d2c85d0d00_0_0 .concat [ 1 4 6 1], L_0x7fa652ad8450, L_0x55d2c85d0c00, L_0x55d2c85d09c0, L_0x55d2c85d0920;
|
||||
LS_0x55d2c85d0d00_0_4 .concat [ 20 0 0 0], L_0x55d2c85d0490;
|
||||
L_0x55d2c85d0d00 .concat [ 12 20 0 0], LS_0x55d2c85d0d00_0_0, LS_0x55d2c85d0d00_0_4;
|
||||
L_0x55d2c85d10c0 .part L_0x55d2c85a4500, 31, 1;
|
||||
L_0x55d2c85d1160 .part L_0x55d2c85a4500, 20, 11;
|
||||
L_0x55d2c85d13c0 .part L_0x55d2c85a4500, 12, 8;
|
||||
L_0x55d2c85e1470 .concat [ 12 8 11 1], L_0x7fa652ad8498, L_0x55d2c85d13c0, L_0x55d2c85d1160, L_0x55d2c85d10c0;
|
||||
L_0x55d2c85e17d0 .part L_0x55d2c85a4500, 31, 1;
|
||||
LS_0x55d2c85e1870_0_0 .concat [ 1 1 1 1], L_0x55d2c85e17d0, L_0x55d2c85e17d0, L_0x55d2c85e17d0, L_0x55d2c85e17d0;
|
||||
LS_0x55d2c85e1870_0_4 .concat [ 1 1 1 1], L_0x55d2c85e17d0, L_0x55d2c85e17d0, L_0x55d2c85e17d0, L_0x55d2c85e17d0;
|
||||
LS_0x55d2c85e1870_0_8 .concat [ 1 1 1 1], L_0x55d2c85e17d0, L_0x55d2c85e17d0, L_0x55d2c85e17d0, L_0x55d2c85e17d0;
|
||||
L_0x55d2c85e1870 .concat [ 4 4 4 0], LS_0x55d2c85e1870_0_0, LS_0x55d2c85e1870_0_4, LS_0x55d2c85e1870_0_8;
|
||||
L_0x55d2c85e1bb0 .part L_0x55d2c85a4500, 12, 8;
|
||||
L_0x55d2c85e1c50 .part L_0x55d2c85a4500, 20, 1;
|
||||
L_0x55d2c85e1ee0 .part L_0x55d2c85a4500, 25, 6;
|
||||
L_0x55d2c85e1f80 .part L_0x55d2c85a4500, 21, 4;
|
||||
LS_0x55d2c85e2280_0_0 .concat [ 1 4 6 1], L_0x7fa652ad84e0, L_0x55d2c85e1f80, L_0x55d2c85e1ee0, L_0x55d2c85e1c50;
|
||||
LS_0x55d2c85e2280_0_4 .concat [ 8 12 0 0], L_0x55d2c85e1bb0, L_0x55d2c85e1870;
|
||||
L_0x55d2c85e2280 .concat [ 12 20 0 0], LS_0x55d2c85e2280_0_0, LS_0x55d2c85e2280_0_4;
|
||||
L_0x55d2c85e24e0 .cmp/eq 4, L_0x55d2c85ced00, L_0x7fa652ad8528;
|
||||
L_0x55d2c85e2990 .cmp/eq 4, L_0x55d2c85ced00, L_0x7fa652ad8570;
|
||||
L_0x55d2c85e2af0 .cmp/eq 4, L_0x55d2c85ced00, L_0x7fa652ad85b8;
|
||||
L_0x55d2c85e28f0 .cmp/eq 4, L_0x55d2c85ced00, L_0x7fa652ad8600;
|
||||
L_0x55d2c85e3030 .cmp/eq 4, L_0x55d2c85ced00, L_0x7fa652ad8648;
|
||||
L_0x55d2c85e34d0 .cmp/eq 4, L_0x55d2c85ced00, L_0x7fa652ad8690;
|
||||
L_0x55d2c85e3680 .cmp/eq 4, L_0x55d2c85ced00, L_0x7fa652ad86d8;
|
||||
L_0x55d2c85e3cd0 .part L_0x55d2c85cee40, 5, 1;
|
||||
L_0x55d2c85e4070 .cmp/eq 4, L_0x55d2c85ced00, L_0x7fa652ad8768;
|
||||
L_0x55d2c85e4c00 .functor MUXZ 32, L_0x55d2c85e4b30, L_0x55d2c85cf6c0, L_0x55d2c85e3af0, C4<>;
|
||||
L_0x55d2c85e4fa0 .arith/sum 32, L_0x55d2c85e49b0, L_0x55d2c85e4c00;
|
||||
L_0x55d2c85e53e0 .functor MUXZ 32, L_0x7fa652ad87b0, L_0x55d2c85e4fa0, L_0x55d2c85e4dc0, C4<>;
|
||||
L_0x55d2c85e5570 .functor MUXZ 32, L_0x7fa652ad87f8, L_0x55d2c85e53e0, L_0x55d2c85e5b60, C4<>;
|
||||
L_0x55d2c85e4e80 .cmp/ne 5, L_0x55d2c85ce300, L_0x7fa652ad8840;
|
||||
L_0x55d2c85e5e70 .part L_0x55d2c85e49b0, 31, 1;
|
||||
L_0x55d2c85e6190 .part L_0x55d2c85e4b30, 31, 1;
|
||||
L_0x55d2c85e6230 .reduce/nor L_0x55d2c85e6190;
|
||||
L_0x55d2c85e66c0 .part L_0x55d2c85e49b0, 31, 1;
|
||||
L_0x55d2c85e6760 .reduce/nor L_0x55d2c85e66c0;
|
||||
L_0x55d2c85e6aa0 .part L_0x55d2c85e4b30, 31, 1;
|
||||
L_0x55d2c85e6d50 .cmp/gt 32, L_0x55d2c85e4b30, L_0x55d2c85e49b0;
|
||||
L_0x55d2c85e70a0 .functor MUXZ 1, L_0x55d2c85e6d50, L_0x7fa652ad88d0, L_0x55d2c85e6b40, C4<>;
|
||||
L_0x55d2c85e7230 .functor MUXZ 1, L_0x55d2c85e70a0, L_0x7fa652ad8888, L_0x55d2c85e65b0, C4<>;
|
||||
L_0x55d2c85e7680 .part L_0x55d2c85e49b0, 31, 1;
|
||||
L_0x55d2c85e7720 .part L_0x55d2c85e4b30, 31, 1;
|
||||
L_0x55d2c85e7a90 .reduce/nor L_0x55d2c85e7720;
|
||||
L_0x55d2c85e7c90 .part L_0x55d2c85e49b0, 31, 1;
|
||||
L_0x55d2c85e8010 .reduce/nor L_0x55d2c85e7c90;
|
||||
L_0x55d2c85e8100 .part L_0x55d2c85e4b30, 31, 1;
|
||||
L_0x55d2c85e8700 .cmp/ge 32, L_0x55d2c85e49b0, L_0x55d2c85e4b30;
|
||||
L_0x55d2c85e87a0 .functor MUXZ 1, L_0x55d2c85e8700, L_0x7fa652ad8960, L_0x55d2c85e8490, C4<>;
|
||||
L_0x55d2c85e8c30 .functor MUXZ 1, L_0x55d2c85e87a0, L_0x7fa652ad8918, L_0x55d2c85e7b80, C4<>;
|
||||
L_0x55d2c85e8dc0 .cmp/eq 32, L_0x55d2c85e49b0, L_0x55d2c85e4b30;
|
||||
L_0x55d2c85e9170 .cmp/ne 32, L_0x55d2c85e49b0, L_0x55d2c85e4b30;
|
||||
L_0x55d2c85e9210 .cmp/gt 32, L_0x55d2c85e4b30, L_0x55d2c85e49b0;
|
||||
L_0x55d2c85e95d0 .cmp/ge 32, L_0x55d2c85e49b0, L_0x55d2c85e4b30;
|
||||
L_0x55d2c85e9670 .functor MUXZ 1, L_0x7fa652ad89a8, L_0x55d2c85e95d0, L_0x55d2c85e35c0, C4<>;
|
||||
L_0x55d2c85e9b60 .functor MUXZ 1, L_0x55d2c85e9670, L_0x55d2c85e9210, L_0x55d2c85e3350, C4<>;
|
||||
L_0x55d2c85e9cf0 .functor MUXZ 1, L_0x55d2c85e9b60, L_0x55d2c85e8c30, L_0x55d2c85e2f70, C4<>;
|
||||
L_0x55d2c85ea1c0 .functor MUXZ 1, L_0x55d2c85e9cf0, L_0x55d2c85e7230, L_0x55d2c85e2db0, C4<>;
|
||||
L_0x55d2c85ea350 .functor MUXZ 1, L_0x55d2c85ea1c0, L_0x55d2c85e9170, L_0x55d2c85e2a30, C4<>;
|
||||
L_0x55d2c85ea830 .functor MUXZ 1, L_0x55d2c85ea350, L_0x55d2c85e8dc0, L_0x55d2c85e2830, C4<>;
|
||||
L_0x55d2c85ea9c0 .arith/sum 32, v0x55d2c85c9da0_0, L_0x55d2c85d0d00;
|
||||
.scope S_0x55d2c85933e0;
|
||||
T_0 ;
|
||||
%vpi_call 3 12 "$readmemh", "program.hex", v0x55d2c85c90a0 {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
.scope S_0x55d2c85933e0;
|
||||
T_1 ;
|
||||
%wait E_0x55d2c857c4c0;
|
||||
%load/vec4 v0x55d2c85caae0_0;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_1.0, 8;
|
||||
%pushi/vec4 0, 0, 32;
|
||||
%assign/vec4 v0x55d2c85c9da0_0, 0;
|
||||
%pushi/vec4 4, 0, 32;
|
||||
%assign/vec4 v0x55d2c85c9cc0_0, 0;
|
||||
%jmp T_1.1;
|
||||
T_1.0 ;
|
||||
%load/vec4 v0x55d2c85caee0_0;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0 T_1.2, 8;
|
||||
%load/vec4 v0x55d2c85c8d40_0;
|
||||
%jmp/1 T_1.3, 8;
|
||||
T_1.2 ; End of true expr.
|
||||
%load/vec4 v0x55d2c85c9da0_0;
|
||||
%addi 4, 0, 32;
|
||||
%jmp/0 T_1.3, 8;
|
||||
; End of false expr.
|
||||
%blend;
|
||||
T_1.3;
|
||||
%assign/vec4 v0x55d2c85c9cc0_0, 0;
|
||||
%load/vec4 v0x55d2c85c9cc0_0;
|
||||
%assign/vec4 v0x55d2c85c9da0_0, 0;
|
||||
T_1.1 ;
|
||||
%jmp T_1;
|
||||
.thread T_1;
|
||||
.scope S_0x55d2c8557240;
|
||||
T_2 ;
|
||||
%delay 5, 0;
|
||||
%load/vec4 v0x55d2c85cb040_0;
|
||||
%inv;
|
||||
%store/vec4 v0x55d2c85cb040_0, 0, 1;
|
||||
%jmp T_2;
|
||||
.thread T_2;
|
||||
.scope S_0x55d2c8557240;
|
||||
T_3 ;
|
||||
%wait E_0x55d2c857c4c0;
|
||||
%vpi_call 2 22 "$display", "Time=%0t, PC=%h, Instr=%h", $time, v0x55d2c85cb240_0, v0x55d2c85cb100_0 {0 0 0};
|
||||
%load/vec4 v0x55d2c85cb240_0;
|
||||
%cmpi/e 256, 0, 32;
|
||||
%jmp/0xz T_3.0, 4;
|
||||
%vpi_call 2 24 "$display", "Simulation completed successfully!" {0 0 0};
|
||||
%vpi_call 2 25 "$finish" {0 0 0};
|
||||
T_3.0 ;
|
||||
%jmp T_3;
|
||||
.thread T_3;
|
||||
.scope S_0x55d2c8557240;
|
||||
T_4 ;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x55d2c85cb040_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x55d2c85cb2e0_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x55d2c85cb2e0_0, 0, 1;
|
||||
%delay 200, 0;
|
||||
%vpi_call 2 35 "$display", "Test completed" {0 0 0};
|
||||
%vpi_call 2 36 "$finish" {0 0 0};
|
||||
%end;
|
||||
.thread T_4;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"RISCcore2TB.v";
|
||||
"RISCcore2.v";
|
||||
Reference in New Issue
Block a user