module pcIMemDec (
  input rst,
  input clk,
  output reg [31:0] pc,
  output reg [31:0] next_pc,
  output wire [31:0] instr
);


//PC
always @(posedge clk) begin 
  if(rst) begin
    pc <= 32'h0;
  end
  else begin 
    next_pc <= pc;
    pc <= pc + 32'h4;
  end
end

//IMem
reg [31:0] imem [0:255];

initial begin
  $readmemh("program.hex", imem);
end

assign instr = imem[pc[31:2]];

//Decoder

wire isUType = ((instr[6:0] == 7'b0110111) || (instr[6:0] == 7'b0010111));
wire isIType = ((instr[6:0] == 7'b0000011) || (instr[6:0] == 7'b0000111) || (instr[6:0] == 7'b0010011) || (instr[6:0] == 7'b0011011) || (instr [6:0] == 7'b1100111));
wire isRType = ((instr[6:0] == 7'b0101111) || (instr[6:0] == 7'b0110011) || (instr[6:0] == 7'b0111011) || (instr[6:0] == 7'b0110011));
wire isSType = ((instr[6:0] == 7'b0100011) || (instr[6:0] == 7'b0100111));
wire isBType = (instr[6:0] == 7'b1100011);
wire isJType = (instr[6:0] == 7'b1101111);

wire [4:0] rs1 = instr[19:15];
wire [4:0] rs2 = instr[24:20];
wire [4:0] rd = instr[11:7];

wire rs2Valid = (isRType || isSType || isBType);
wire rs1Valid = (~isUType && ~isJType);
wire rdValid = (~isSType && ~isBType);

wire [3:0] funct3 = instr[14:12];
wire [6:0] funct7 = instr[31:25];

wire funct3Valid = rs1Valid;
wire funct7Valid = isRType;

wire [31:0] Iimm = {{21{instr[31]}}, {instr[30:25]}, {instr[24:20]}};
wire [31:0] Simm = {{21{instr[31]}}, {instr[30:25]}, {instr[11:7]}};
wire [31:0] Bimm = {{20{instr[31]}}, {instr[7]}, {instr[30:25]}, {instr[11:8]}, 1'b0};
wire [31:0] Uimm = {{instr[31]}, {instr[30:20]}, {instr[19:12]}, {12{1'b0}};
wire [31:0] Jimm = {{12{instr[31]}}, {instr[19:12]}, {instr[20]}, {instr[30:25]}, {instr[24:21]}, 1'b0};

//Instructions

isBEQ = (funct3 == 000 && isBType);
isBNE = (funct3 == 001 && isBType);
isBLT = (funct3 == 100 && isBType);
isBGE = (funct3 == 101 && isBType);
isBLTU = (funct3 == 110 && isBType);
isBGEU = (funct3 == 111 && isBType);

isADDI = (funct3 == 000 && isIType);

isADD = (funct7[5] == 0 && isRType);

endmodule