module fibonacci (
  input clk,
  input rst,
  output reg [31:0] num
);

reg [31:0] nums [1:0];

always @(posedge clk) begin 
  if (rst) begin 
    num <= 32'd1;
    nums[0] <= 32'd0;
    nums[1] <= 32'd0;
  end
  else begin 
    nums[1] <= nums[0];
    nums[0] <= num;
    num <= nums[0] + nums[1];
  end
end

endmodule