`timescale 1ns/1ps module RISCCore_tb; reg clk; reg rst; wire [31:0] pc; wire [31:0] next_pc; wire [31:0] instr; // Instantiate the RISC-V core RISCCore uut ( .rst(rst), .clk(clk), .pc(pc), .next_pc(next_pc), .instr(instr) ); // Clock generation always #5 clk = ~clk; // Initialize signals initial begin clk = 0; rst = 1; // Reset sequence #10 rst = 0; // Run for enough clock cycles #500; // Display final register values $display("\n=== FINAL REGISTER STATE ==="); $display("x1 (ra) = %h", uut.rf[1]); $display("x2 (sp) = %h", uut.rf[2]); $display("x3 (gp) = %h", uut.rf[3]); $display("x4 (tp) = %h", uut.rf[4]); $display("x5 (t0) = %h", uut.rf[5]); $display("x6 (t1) = %h", uut.rf[6]); $display("x7 (t2) = %h", uut.rf[7]); $display("x8 (s0) = %h", uut.rf[8]); $display("x10 (a0) = %h", uut.rf[10]); // Display memory contents $display("\n=== MEMORY STATE ==="); begin : memory_display integer i; for (i = 0; i < 10; i = i + 1) begin $display("mem[%0d] = %h", i, uut.dmem[i]); end end $finish; end // Simple monitor initial begin $monitor("Time=%0t: PC=%h, Instr=%h", $time, uut.pc, uut.instr); end endmodule