module RISCcore2TB;
  reg clk;
  reg rst;
  wire [31:0] pc;
  wire [31:0] next_pc;
  wire [31:0] instr;
  
  // Instantiate RISC core
  RISCcore2 uut (
    .rst(rst),
    .clk(clk),
    .pc(pc),
    .next_pc(next_pc),
    .instr(instr)
  );
  
  // Clock generation
  always #5 clk = ~clk;
  
  // Monitor
  always @(posedge clk) begin
    $display("Time=%0t, PC=%h, Instr=%h", $time, pc, instr);
    if (pc == 32'h100) begin // End simulation after some time
      $display("Simulation completed successfully!");
      $finish;
    end
  end
  
  // Initialize
  initial begin
    clk = 0;
    rst = 1;
    #10 rst = 0;
    #200;
    $display("Test completed");
    $finish;
  end
endmodule