module fibonacciTB();

reg clk, rst;
wire [31:0] num;

fibonacci uut (
  .clk(clk),
  .rst(rst),
  .num(num)
);

always begin
  clk = ~clk; #1;
end

initial begin
  $dumpfile("fibonacci.vcd");
  $dumpvars;
  clk = 1'b0; rst = 1'b1; #4;
  rst = 1'b0; #40;
  $finish;
end
endmodule