$date
	Mon Aug 18 06:14:05 2025
$end
$version
	Icarus Verilog
$end
$timescale
	1s
$end
$scope module pcIMemTB $end
$var wire 32 ! pc [31:0] $end
$var wire 32 " next_pc [31:0] $end
$var wire 32 # instr [31:0] $end
$var reg 1 $ clk $end
$var reg 1 % rst $end
$scope module dut $end
$var wire 1 $ clk $end
$var wire 32 & instr [31:0] $end
$var wire 1 % rst $end
$var reg 32 ' next_pc [31:0] $end
$var reg 32 ( pc [31:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
$end
#0
$dumpvars
bx (
bx '
bx &
1%
0$
bx #
bx "
bx !
$end
#2
b10011 #
b10011 &
b0 !
b0 (
1$
#4
0$
0%
#6
b100000000000010010011 #
b100000000000010010011 &
b100 !
b100 (
b0 "
b0 '
1$
#8
0$
#10
b1000000000000100010011 #
b1000000000000100010011 &
b1000 !
b1000 (
b100 "
b100 '
1$
#12
0$
#14
b1100001000000110010011 #
b1100001000000110010011 &
b1100 !
b1100 (
b1000 "
b1000 '
1$
#16
0$
#18
b10000001000001000010011 #
b10000001000001000010011 &
b10000 !
b10000 (
b1100 "
b1100 '
1$
#20
0$
#22
b10100010000001010010011 #
b10100010000001010010011 &
b10100 !
b10100 (
b10000 "
b10000 '
1$
#24
0$
#26
b11000010000001100010011 #
b11000010000001100010011 &
b11000 !
b11000 (
b10100 "
b10100 '
1$
#28
0$
#30
b110000011000001110010011 #
b110000011000001110010011 &
b11100 !
b11100 (
b11000 "
b11000 '
1$
#32
0$
#34
b110100101000010000010011 #
b110100101000010000010011 &
b100000 !
b100000 (
b11100 "
b11100 '
1$
#36
0$
#38
b11111111111111111111011100110111 #
b11111111111111111111011100110111 &
b100100 !
b100100 (
b100000 "
b100000 '
1$
#40
0$
#42
bx #
bx &
b101000 !
b101000 (
b100100 "
b100100 '
1$