20 lines
231 B
Verilog
20 lines
231 B
Verilog
module pc (
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input rst,
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input clk,
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output reg [31:0] pc,
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output reg [31:0] next_pc
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);
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always @(posedge clk) begin
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if(rst) begin
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pc <= 0;
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end
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else begin
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next_pc <= pc;
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pc <= pc + 1;
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end
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end
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endmodule
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