57 lines
1.4 KiB
Verilog
57 lines
1.4 KiB
Verilog
`timescale 1ns/1ps
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module pcIMemDecTB();
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// Inputs
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reg clk;
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reg rst;
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// Outputs
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wire [31:0] pc;
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wire [31:0] next_pc;
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wire [31:0] instr;
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// Create test memory and program.hex FIRST
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reg [31:0] test_mem [0:5];
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initial begin
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test_mem[0] = 32'h00001037; // lui x0, 1
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test_mem[1] = 32'h00100093; // addi x1, x0, 1
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test_mem[2] = 32'h001081b3; // add x3, x1, x1
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test_mem[3] = 32'h0010a023; // sw x1, 0(x1)
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test_mem[4] = 32'h00108663; // beq x1, x1, 12
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test_mem[5] = 32'h00c0006f; // jal x0, 12
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$writememh("program.hex", test_mem);
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#1; // Small delay to ensure file creation
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end
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// Instantiate DUT AFTER file creation
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pcIMemDec dut (
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.clk(clk),
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.rst(rst),
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.pc(pc),
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.next_pc(next_pc),
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.instr(instr)
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);
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// Clock generation (100MHz)
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initial begin
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clk = 0;
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forever #5 clk = ~clk;
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end
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// Test sequence
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initial begin
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$dumpfile("pcIMemDec.vcd");
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$dumpvars(0, pcIMemDecTB);
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rst = 1;
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#20 rst = 0;
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$monitor("Time=%0t PC=%h Instr=%h Types: U=%b I=%b R=%b S=%b B=%b J=%b",
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$time, pc, instr,
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dut.isUType, dut.isIType, dut.isRType, dut.isSType, dut.isBType, dut.isJType);
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#200 $finish;
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end
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endmodule
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