63 lines
1.3 KiB
Verilog
63 lines
1.3 KiB
Verilog
`timescale 1ns/1ps
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module RISCCore_tb;
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reg clk;
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reg rst;
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wire [31:0] pc;
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wire [31:0] next_pc;
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wire [31:0] instr;
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// Instantiate the RISC-V core
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RISCCore uut (
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.rst(rst),
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.clk(clk),
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.pc(pc),
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.next_pc(next_pc),
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.instr(instr)
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);
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// Clock generation
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always #5 clk = ~clk;
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// Initialize signals
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initial begin
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clk = 0;
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rst = 1;
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// Reset sequence
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#10 rst = 0;
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// Run for enough clock cycles
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#500;
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// Display final register values
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$display("\n=== FINAL REGISTER STATE ===");
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$display("x1 (ra) = %h", uut.rf[1]);
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$display("x2 (sp) = %h", uut.rf[2]);
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$display("x3 (gp) = %h", uut.rf[3]);
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$display("x4 (tp) = %h", uut.rf[4]);
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$display("x5 (t0) = %h", uut.rf[5]);
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$display("x6 (t1) = %h", uut.rf[6]);
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$display("x7 (t2) = %h", uut.rf[7]);
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$display("x8 (s0) = %h", uut.rf[8]);
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$display("x10 (a0) = %h", uut.rf[10]);
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// Display memory contents
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$display("\n=== MEMORY STATE ===");
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begin : memory_display
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integer i;
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for (i = 0; i < 10; i = i + 1) begin
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$display("mem[%0d] = %h", i, uut.dmem[i]);
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end
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end
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$finish;
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end
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// Simple monitor
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initial begin
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$monitor("Time=%0t: PC=%h, Instr=%h", $time, uut.pc, uut.instr);
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end
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endmodule
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