initial commit

2025-08-02 06:09:31 +03:00
commit 00015ffc03
85 changed files with 62051 additions and 0 deletions
--- a/BOARDS/arty.xdc
+++ b/BOARDS/arty.xdc
@@ -0,0 +1,27 @@
+# Clock pin
+set_property PACKAGE_PIN E3 [get_ports CLK]
+set_property IOSTANDARD LVCMOS33 [get_ports CLK]
+
+# LEDs
+set_property PACKAGE_PIN H5  [get_ports LEDS[0]]
+set_property PACKAGE_PIN J5  [get_ports LEDS[1]]
+set_property PACKAGE_PIN T9  [get_ports LEDS[2]]
+set_property PACKAGE_PIN T10 [get_ports LEDS[3]]
+set_property IOSTANDARD LVCMOS33 [get_ports LEDS[0]]
+set_property IOSTANDARD LVCMOS33 [get_ports LEDS[1]]
+set_property IOSTANDARD LVCMOS33 [get_ports LEDS[2]]
+set_property IOSTANDARD LVCMOS33 [get_ports LEDS[3]]
+
+# Clock constraints
+create_clock -period 10.0 [get_ports CLK]
+
+# UART
+set_property LOC D10 [get_ports TXD]
+set_property LOC A9 [get_ports RXD]
+set_property IOSTANDARD LVCMOS33 [get_ports RXD]
+set_property IOSTANDARD LVCMOS33 [get_ports TXD]
+
+# reset button
+set_property LOC C2 [get_ports RESET]
+set_property IOSTANDARD LVCMOS33 [get_ports RESET]
+
--- a/BOARDS/cmod_a7.xdc
+++ b/BOARDS/cmod_a7.xdc
@@ -0,0 +1,29 @@
+# Clock pin
+set_property PACKAGE_PIN L17 [get_ports CLK]
+set_property IOSTANDARD LVCMOS33 [get_ports CLK]
+
+# LEDs
+set_property PACKAGE_PIN A17 [get_ports LEDS[0]]
+set_property PACKAGE_PIN C16 [get_ports LEDS[1]]
+set_property PACKAGE_PIN B17 [get_ports LEDS[2]]
+set_property PACKAGE_PIN B16 [get_ports LEDS[3]]
+set_property PACKAGE_PIN C17 [get_ports LEDS[4]]
+set_property IOSTANDARD LVCMOS33 [get_ports LEDS[0]]
+set_property IOSTANDARD LVCMOS33 [get_ports LEDS[1]]
+set_property IOSTANDARD LVCMOS33 [get_ports LEDS[2]]
+set_property IOSTANDARD LVCMOS33 [get_ports LEDS[3]]
+set_property IOSTANDARD LVCMOS33 [get_ports LEDS[4]]
+
+# Clock constraints
+create_clock -period 83.33 [get_ports CLK]
+
+# UART
+set_property LOC G17 [get_ports TXD]
+set_property LOC G19 [get_ports RXD]
+set_property IOSTANDARD LVCMOS33 [get_ports RXD]
+set_property IOSTANDARD LVCMOS33 [get_ports TXD]
+
+# reset button
+set_property LOC A18 [get_ports RESET]
+set_property IOSTANDARD LVCMOS33 [get_ports RESET]
+
--- a/BOARDS/ecp5_evn.lpf
+++ b/BOARDS/ecp5_evn.lpf
@@ -0,0 +1,35 @@
+# See https://github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf
+
+## Clock #########################################
+
+LOCATE COMP "CLK" SITE "A10";
+IOBUF PORT "CLK" IO_TYPE=LVCMOS33;
+FREQUENCY PORT "CLK" 12 MHZ;
+
+## RESET button ##################################
+
+LOCATE COMP "RESET" SITE "P4"; 
+IOBUF PORT "RESET" IO_TYPE=LVCMOS33;
+
+## LEDs ##########################################
+
+LOCATE COMP "LEDS[0]" SITE "B17";
+LOCATE COMP "LEDS[1]" SITE "A17";
+LOCATE COMP "LEDS[2]" SITE "C17";
+LOCATE COMP "LEDS[3]" SITE "B18";
+LOCATE COMP "LEDS[4]" SITE "A18";
+
+IOBUF PORT "LEDS[0]"  IO_TYPE=LVCMOS33;
+IOBUF PORT "LEDS[1]"  IO_TYPE=LVCMOS33;
+IOBUF PORT "LEDS[2]"  IO_TYPE=LVCMOS33;
+IOBUF PORT "LEDS[3]"  IO_TYPE=LVCMOS33;
+IOBUF PORT "LEDS[4]"  IO_TYPE=LVCMOS33;
+
+## UART ######################################################
+
+LOCATE COMP "TXD"   SITE "D11"; 
+LOCATE COMP "RXD"   SITE "D12"; 
+
+IOBUF PORT "TXD" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "RXD" PULLMODE=UP IO_TYPE=LVCMOS33;
+
--- a/BOARDS/icebreaker.pcf
+++ b/BOARDS/icebreaker.pcf
@@ -0,0 +1,13 @@
+set_io CLK 35
+
+set_io LEDS[0] 27
+set_io LEDS[1] 21
+set_io LEDS[2] 25
+set_io LEDS[3] 23
+set_io LEDS[4] 26
+
+set_io TXD 9
+set_io RXD 6
+
+set_io RESET 10
+
--- a/BOARDS/icestick.pcf
+++ b/BOARDS/icestick.pcf
@@ -0,0 +1,21 @@
+set_io CLK 21
+
+set_io LEDS[0] 99
+set_io LEDS[1] 98
+set_io LEDS[2] 97
+set_io LEDS[3] 96
+set_io LEDS[4] 95
+
+set_io TXD  8
+set_io RXD  9
+
+set_io SPIFLASH_CLK  70
+set_io SPIFLASH_CS_N 71
+
+set_io SPIFLASH_MOSI 67
+set_io SPIFLASH_MISO 68
+
+set_io SPIFLASH_IO[0] 67
+set_io SPIFLASH_IO[1] 68
+
+set_io RESET 47
--- a/BOARDS/run_arty.sh
+++ b/BOARDS/run_arty.sh
@@ -0,0 +1,18 @@
+#!/usr/bin/env bash
+PROJECT_NAME=SOC
+DB_DIR=/usr/share/nextpnr/prjxray-db
+CHIPDB_DIR=/usr/share/nextpnr/xilinx-chipdb
+PART=xc7a35tcsg324-1
+VERILOGS=$1
+BOARD_FREQ=100
+CPU_FREQ=100
+
+set -ex
+yosys -DARTY -DBOARD_FREQ=$BOARD_FREQ -DCPU_FREQ=$CPU_FREQ -p "scratchpad -set xilinx_dsp.multonly 1" -p "synth_xilinx -nowidelut -flatten -abc9 -arch xc7 -top SOC; write_json ${PROJECT_NAME}.json" ${VERILOGS}
+nextpnr-xilinx --chipdb ${CHIPDB_DIR}/xc7a35t.bin --xdc BOARDS/arty.xdc --json ${PROJECT_NAME}.json --write ${PROJECT_NAME}_routed.json --fasm ${PROJECT_NAME}.fasm
+fasm2frames --part ${PART} --db-root ${DB_DIR}/artix7 ${PROJECT_NAME}.fasm > ${PROJECT_NAME}.frames
+xc7frames2bit --part_file ${DB_DIR}/artix7/${PART}/part.yaml --part_name ${PART} --frm_file ${PROJECT_NAME}.frames --output_file ${PROJECT_NAME}.bit
+#To send to SRAM:
+openFPGALoader --board arty ${PROJECT_NAME}.bit
+#To send to FLASH: 
+#openFPGALoader --board arty -f ${PROJECT_NAME}.bit
--- a/BOARDS/run_cmod_a7.sh
+++ b/BOARDS/run_cmod_a7.sh
@@ -0,0 +1,18 @@
+#!/usr/bin/env bash
+PROJECT_NAME=SOC
+DB_DIR=/usr/share/nextpnr/prjxray-db
+CHIPDB_DIR=/usr/share/nextpnr/xilinx-chipdb
+PART=xc7a35tcpg236-1
+VERILOGS=$1
+BOARD_FREQ=100
+CPU_FREQ=100
+
+set -ex
+yosys -DCMODA7 -DBOARD_FREQ=$BOARD_FREQ -DCPU_FREQ=$CPU_FREQ -p "scratchpad -set xilinx_dsp.multonly 1" -p "synth_xilinx -nowidelut -flatten -abc9 -arch xc7 -top SOC; write_json ${PROJECT_NAME}.json" ${VERILOGS}
+nextpnr-xilinx --chipdb ${CHIPDB_DIR}/xc7a35tcpg236-1.bin --xdc BOARDS/cmod_a7.xdc --json ${PROJECT_NAME}.json --write ${PROJECT_NAME}_routed.json --fasm ${PROJECT_NAME}.fasm
+fasm2frames --part ${PART} --db-root ${DB_DIR}/artix7 ${PROJECT_NAME}.fasm > ${PROJECT_NAME}.frames
+xc7frames2bit --part_file ${DB_DIR}/artix7/${PART}/part.yaml --part_name ${PART} --frm_file ${PROJECT_NAME}.frames --output_file ${PROJECT_NAME}.bit
+#To send to SRAM:
+openFPGALoader --freq 30e6 -c digilent --fpga-part xc7a35 femtosoc.bit
+#To send to FLASH: 
+# openFPGALoader --freq 30e6 -c digilent --fpga-part xc7a35tcpg236 -f femtosoc.bit
--- a/BOARDS/run_ecp5evn.sh
+++ b/BOARDS/run_ecp5evn.sh
@@ -0,0 +1,13 @@
+PROJECTNAME=SOC
+BOARD=ecp5_evn
+BOARD_FREQ=12
+CPU_FREQ=100
+FPGA_VARIANT=um5g-85k
+FPGA_PACKAGE=CABGA381
+VERILOGS=$1
+
+yosys -q -DECP5_EVN -DBOARD_FREQ=$BOARD_FREQ -DCPU_FREQ=$CPU_FREQ -p "synth_ecp5 -abc9 -top $PROJECTNAME -json $PROJECTNAME.json" $VERILOGS  || exit
+nextpnr-ecp5 --force --timing-allow-fail --json $PROJECTNAME.json --lpf BOARDS/$BOARD.lpf --textcfg $PROJECTNAME"_out".config --freq $BOARD_FREQ --$FPGA_VARIANT --package $FPGA_PACKAGE || exit
+ecppack --compress --svf-rowsize 100000 --svf $PROJECTNAME".svf" $PROJECTNAME"_out.config" $PROJECTNAME".bit" || exit
+ujprog -j FLASH $PROJECTNAME".bit"  || exit
+
--- a/BOARDS/run_gowin.sh
+++ b/BOARDS/run_gowin.sh
@@ -0,0 +1,30 @@
+#!/bin/bash
+
+# --- CONFIGURATION ---
+PROJECTNAME=SOC
+DEVICE='GW2A-LV18PG256C8/I7'
+BOARD='tangprimer20k'
+BOARD_FREQ=27
+CPU_FREQ=50
+VERILOGS=$1
+
+# --- Synthesis with Yosys ---
+yosys -q -DPRIMER20K -DBOARD_FREQ=$BOARD_FREQ -DCPU_FREQ=$CPU_FREQ -D INV_BTN=0 -p "
+    read_verilog $VERILOGS;
+    synth_gowin -top $PROJECTNAME -json $PROJECTNAME.json -family gw2a" || exit 1
+
+# --- Placement and Routing with nextpnr-himbaechel ---
+nextpnr-himbaechel \
+    --json $PROJECTNAME.json \
+    --write $PROJECTNAME"_pnr.json" \
+    --device $DEVICE \
+    --vopt cst=BOARDS/$BOARD.cst \
+    --vopt family=GW2A-18 \
+    --freq $BOARD_FREQ || exit 1
+
+# --- Bitstream Packing with gowin_pack ---
+gowin_pack -d $DEVICE -o $PROJECTNAME.fs $PROJECTNAME"_pnr.json" || exit 1
+
+# --- Programming with openFPGALoader ---
+openFPGALoader -b tangprimer20k $PROJECTNAME.fs || exit 1
+
--- a/BOARDS/run_icebreaker.sh
+++ b/BOARDS/run_icebreaker.sh
@@ -0,0 +1,14 @@
+PROJECTNAME=SOC
+BOARD=icebreaker
+BOARD_FREQ=12
+CPU_FREQ=20
+FPGA_VARIANT=up5k
+FPGA_PACKAGE=sg48
+VERILOGS=$1
+yosys -q -DICE_BREAKER -DNEGATIVE_RESET -DBOARD_FREQ=$BOARD_FREQ -DCPU_FREQ=$CPU_FREQ -p "synth_ice40 -abc9 -device u -dsp -top $PROJECTNAME -json $PROJECTNAME.json" $VERILOGS  || exit
+nextpnr-ice40 --force --json $PROJECTNAME.json --pcf BOARDS/$BOARD.pcf --asc $PROJECTNAME.asc --freq $BOARD_FREQ --$FPGA_VARIANT --package $FPGA_PACKAGE --pcf-allow-unconstrained || exit
+icetime -p BOARDS/$BOARD.pcf -P $FPGA_PACKAGE -r $PROJECTNAME.timings -d up5k -t $PROJECTNAME.asc
+icepack $PROJECTNAME.asc $PROJECTNAME.bin || exit
+iceprog $PROJECTNAME.bin || exit
+echo DONE.
+
--- a/BOARDS/run_icestick.sh
+++ b/BOARDS/run_icestick.sh
@@ -0,0 +1,14 @@
+PROJECTNAME=SOC
+BOARD=icestick
+BOARD_FREQ=12
+CPU_FREQ=45
+FPGA_VARIANT=hx1k
+FPGA_PACKAGE=tq144
+VERILOGS=$1
+yosys -q -DICE_STICK -DBOARD_FREQ=$BOARD_FREQ -DCPU_FREQ=$CPU_FREQ -p "synth_ice40 -relut -top $PROJECTNAME -json $PROJECTNAME.json" $VERILOGS  || exit
+nextpnr-ice40 --force --timing-allow-fail --json $PROJECTNAME.json --pcf BOARDS/$BOARD.pcf --asc $PROJECTNAME.asc --freq $CPU_FREQ --$FPGA_VARIANT --package $FPGA_PACKAGE --pcf-allow-unconstrained --opt-timing || exit
+icetime -p BOARDS/$BOARD.pcf -P $FPGA_PACKAGE -r $PROJECTNAME.timings -d hx1k -t $PROJECTNAME.asc
+icepack $PROJECTNAME.asc $PROJECTNAME.bin || exit
+iceprog $PROJECTNAME.bin || exit
+echo DONE.
+
--- a/BOARDS/run_icestick_show.sh
+++ b/BOARDS/run_icestick_show.sh
@@ -0,0 +1,9 @@
+PROJECTNAME=SOC
+BOARD=icestick
+BOARD_FREQ=12
+CPU_FREQ=45
+FPGA_VARIANT=hx1k
+FPGA_PACKAGE=tq144
+VERILOGS=$1
+yosys -q -DICE_STICK -DBOARD_FREQ=$BOARD_FREQ -DCPU_FREQ=$CPU_FREQ -p "synth_ice40 -relut -top $PROJECTNAME -json $PROJECTNAME.json" $VERILOGS  || exit
+nextpnr-ice40 --gui --force --timing-allow-fail --json $PROJECTNAME.json --pcf BOARDS/$BOARD.pcf --asc $PROJECTNAME.asc --freq $CPU_FREQ --$FPGA_VARIANT --package $FPGA_PACKAGE --pcf-allow-unconstrained --opt-timing || exit
--- a/BOARDS/run_ulx3s.sh
+++ b/BOARDS/run_ulx3s.sh
@@ -0,0 +1,13 @@
+PROJECTNAME=SOC
+BOARD=ulx3s
+BOARD_FREQ=25
+CPU_FREQ=100
+FPGA_VARIANT=85k
+FPGA_PACKAGE=CABGA381
+VERILOGS=$1
+
+yosys -q -DULX3S -DBOARD_FREQ=$BOARD_FREQ -DCPU_FREQ=$CPU_FREQ -p "synth_ecp5 -abc9 -top $PROJECTNAME -json $PROJECTNAME.json" $VERILOGS  || exit
+nextpnr-ecp5 --force --timing-allow-fail --json $PROJECTNAME.json --lpf BOARDS/$BOARD.lpf --textcfg $PROJECTNAME"_out".config --freq $BOARD_FREQ --$FPGA_VARIANT --package $FPGA_PACKAGE || exit
+ecppack --compress --svf-rowsize 100000 --svf $PROJECTNAME".svf" $PROJECTNAME"_out.config" $PROJECTNAME".bit" || exit
+ujprog -j FLASH $PROJECTNAME".bit"  || exit
+
--- a/BOARDS/tangprimer20k.cst
+++ b/BOARDS/tangprimer20k.cst
@@ -0,0 +1,143 @@
+IO_LOC  "clk" H11;
+IO_PORT "clk" IO_TYPE=LVCMOS33;
+IO_LOC  "key_i" T3;
+IO_LOC  "rst_i" T10;
+IO_PORT "rst_i" IO_TYPE=LVCMOS33;
+
+IO_LOC  "clk_i" IOT27A;
+
+IO_LOC  "led[0]" C13;
+IO_PORT "led[0]" IO_TYPE=LVCMOS33;
+IO_LOC  "led[1]" A13;
+IO_PORT "led[1]" IO_TYPE=LVCMOS33;
+IO_LOC  "led[2]" N16;
+IO_PORT "led[2]" IO_TYPE=LVCMOS33;
+IO_LOC  "led[3]" N14;
+IO_PORT "led[3]" IO_TYPE=LVCMOS33;
+IO_LOC  "led[4]" L14;
+IO_PORT "led[4]" IO_TYPE=LVCMOS33;
+IO_LOC  "led[5]" L16;
+IO_PORT "led[5]" IO_TYPE=LVCMOS33;
+
+IO_LOC  "TXD" A15;
+IO_PORT "TXD" IO_TYPE=LVCMOS33 PULL_MODE=UP;
+IO_LOC  "RXD" D14;
+IO_PORT "RXD" IO_TYPE=LVCMOS33 PULL_MODE=UP;
+
+// fake
+IO_LOC  "led[6]" A15;
+IO_PORT "led[6]" IO_TYPE=LVCMOS33 PULL_MODE=NONE;
+IO_LOC  "led[7]" D14;
+IO_PORT "led[7]" IO_TYPE=LVCMOS33 PULL_MODE=NONE;
+
+IO_LOC  "tlvds_p" P6;
+IO_PORT "tlvds_p" IO_TYPE=LVDS25 PULL_MODE=NONE;
+IO_LOC  "tlvds_n" T6;
+IO_PORT "tlvds_n" IO_TYPE=LVDS25 PULL_MODE=NONE;
+
+IO_LOC  "elvds_p" C12;
+IO_PORT "elvds_p" IO_TYPE=LVDS25 PULL_MODE=NONE;
+IO_LOC  "elvds_n" B12;
+IO_PORT "elvds_n" IO_TYPE=LVDS25 PULL_MODE=NONE;
+
+IO_LOC  "LED_R" C13;
+IO_PORT "LED_R" IO_TYPE=LVCMOS33;
+IO_LOC  "LED_G" A13;
+IO_PORT "LED_G" IO_TYPE=LVCMOS33;
+IO_LOC  "LED_B" N16;
+IO_PORT "LED_B" IO_TYPE=LVCMOS33;
+
+// oser
+IO_LOC  "oser_out" C13;
+IO_PORT "oser_out" IO_TYPE=LVCMOS33;
+IO_LOC  "fclk_o"   N16;
+IO_PORT "fclk_o"   IO_TYPE=LVCMOS33;
+IO_LOC  "pclk_o"   N14;
+IO_PORT "pclk_o"   IO_TYPE=LVCMOS33;
+
+// ides
+IO_LOC  "fclk_i" B13;
+IO_PORT "fclk_i" IO_TYPE=LVCMOS33;
+IO_LOC  "data_i" C12;
+IO_PORT "data_i" IO_TYPE=LVCMOS33;
+IO_LOC  "q_o[0]" P9;
+IO_PORT "q_o[0]" IO_TYPE=LVCMOS33;
+IO_LOC  "q_o[1]" E15;
+IO_PORT "q_o[1]" IO_TYPE=LVCMOS33;
+IO_LOC  "q_o[2]" T7;
+IO_PORT "q_o[2]" IO_TYPE=LVCMOS33;
+IO_LOC  "q_o[3]" R8;
+IO_PORT "q_o[3]" IO_TYPE=LVCMOS33;
+IO_LOC  "q_o[4]" T6;
+IO_PORT "q_o[4]" IO_TYPE=LVCMOS33;
+IO_LOC  "q_o[5]" P6;
+IO_PORT "q_o[5]" IO_TYPE=LVCMOS33;
+IO_LOC  "q_o[6]" T8;
+IO_PORT "q_o[6]" IO_TYPE=LVCMOS33;
+IO_LOC  "q_o[7]" P8;
+IO_PORT "q_o[7]" IO_TYPE=LVCMOS33;
+
+// RGB  LCD
+IO_LOC  "LCD_CLK"  R9;
+IO_PORT "LCD_CLK"  IO_TYPE=LVCMOS33;
+IO_LOC  "LCD_HYNC" A15;
+IO_PORT "LCD_HYNC" IO_TYPE=LVCMOS33;
+IO_LOC  "LCD_SYNC" D14;
+IO_PORT "LCD_SYNC" IO_TYPE=LVCMOS33;
+IO_LOC  "LCD_DEN"  E15;
+IO_PORT "LCD_DEN"  IO_TYPE=LVCMOS33;
+IO_LOC  "LCD_R[0]" L9;
+IO_PORT "LCD_R[0]" IO_TYPE=LVCMOS33;
+IO_LOC  "LCD_R[1]" N8;
+IO_PORT "LCD_R[1]" IO_TYPE=LVCMOS33;
+IO_LOC  "LCD_R[2]" N9;
+IO_PORT "LCD_R[2]" IO_TYPE=LVCMOS33;
+IO_LOC  "LCD_R[3]" N7;
+IO_PORT "LCD_R[3]" IO_TYPE=LVCMOS33;
+IO_LOC  "LCD_R[4]" N6;
+IO_PORT "LCD_R[4]" IO_TYPE=LVCMOS33;
+
+IO_LOC  "LCD_G[0]" D11;
+IO_PORT "LCD_G[0]" IO_TYPE=LVCMOS33;
+IO_LOC  "LCD_G[1]" A11;
+IO_PORT "LCD_G[1]" IO_TYPE=LVCMOS33;
+IO_LOC  "LCD_G[2]" B11;
+IO_PORT "LCD_G[2]" IO_TYPE=LVCMOS33;
+IO_LOC  "LCD_G[3]" P7;
+IO_PORT "LCD_G[3]" IO_TYPE=LVCMOS33;
+IO_LOC  "LCD_G[4]" R7;
+IO_PORT "LCD_G[4]" IO_TYPE=LVCMOS33;
+IO_LOC  "LCD_G[5]" D10;
+IO_PORT "LCD_G[5]" IO_TYPE=LVCMOS33;
+
+IO_LOC  "LCD_B[0]" B12;
+IO_PORT "LCD_B[0]" IO_TYPE=LVCMOS33;
+IO_LOC  "LCD_B[1]" C12;
+IO_PORT "LCD_B[1]" IO_TYPE=LVCMOS33;
+IO_LOC  "LCD_B[2]" B13;
+IO_PORT "LCD_B[2]" IO_TYPE=LVCMOS33;
+IO_LOC  "LCD_B[3]" A14;
+IO_PORT "LCD_B[3]" IO_TYPE=LVCMOS33;
+IO_LOC  "LCD_B[4]" B14;
+IO_PORT "LCD_B[4]" IO_TYPE=LVCMOS33;
+
+// DVI
+IO_LOC  "tmds_clk_p" G16;
+IO_PORT "tmds_clk_p" PULL_MODE=NONE DRIVE=3.5;
+IO_LOC  "tmds_clk_n" H15;
+IO_PORT "tmds_clk_n" PULL_MODE=NONE DRIVE=3.5;
+IO_LOC  "tmds_d_p[0]" H14;
+IO_PORT "tmds_d_p[0]" PULL_MODE=NONE DRIVE=3.5;
+IO_LOC  "tmds_d_n[0]" H16;
+IO_PORT "tmds_d_n[0]" PULL_MODE=NONE DRIVE=3.5;
+IO_LOC  "tmds_d_p[1]" J15;
+IO_PORT "tmds_d_p[1]" PULL_MODE=NONE DRIVE=3.5;
+IO_LOC  "tmds_d_n[1]" K16;
+IO_PORT "tmds_d_n[1]" PULL_MODE=NONE DRIVE=3.5;
+IO_LOC  "tmds_d_p[2]" K14;
+IO_PORT "tmds_d_p[2]" PULL_MODE=NONE DRIVE=3.5;
+IO_LOC  "tmds_d_n[2]" K15;
+IO_PORT "tmds_d_n[2]" PULL_MODE=NONE DRIVE=3.5;
+
+IO_LOC  "div_led" C13;
+IO_PORT "div_led" IO_TYPE=LVCMOS33;
--- a/BOARDS/ulx3s.lpf
+++ b/BOARDS/ulx3s.lpf
@@ -0,0 +1,35 @@
+# See https://github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf
+
+## Clock #########################################
+
+LOCATE COMP "CLK" SITE "G2";
+IOBUF PORT "CLK" PULLMODE=NONE IO_TYPE=LVCMOS33;
+FREQUENCY PORT "CLK" 25 MHZ;
+
+## RESET button ##################################
+
+LOCATE COMP "RESET" SITE "T1"; # fire 2 
+IOBUF PORT "RESET" IO_TYPE=LVCMOS33;
+
+## LEDs ##########################################
+
+LOCATE COMP "LEDS[0]" SITE "B2";
+LOCATE COMP "LEDS[1]" SITE "C2";
+LOCATE COMP "LEDS[2]" SITE "C1";
+LOCATE COMP "LEDS[3]" SITE "D2";
+LOCATE COMP "LEDS[4]" SITE "D1";
+
+IOBUF PORT "LEDS[0]"  IO_TYPE=LVCMOS33;
+IOBUF PORT "LEDS[1]"  IO_TYPE=LVCMOS33;
+IOBUF PORT "LEDS[2]"  IO_TYPE=LVCMOS33;
+IOBUF PORT "LEDS[3]"  IO_TYPE=LVCMOS33;
+IOBUF PORT "LEDS[4]"  IO_TYPE=LVCMOS33;
+
+## UART ######################################################
+
+LOCATE COMP "TXD"   SITE "L4"; # FPGA transmits to ftdi
+LOCATE COMP "RXD"   SITE "M1"; # FPGA receives from ftdi
+
+IOBUF PORT "TXD" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT "RXD" PULLMODE=UP IO_TYPE=LVCMOS33;
+