/* Register bank and state machine */
`default_nettype none
`include "clockworks.v"

module SOC (
  input clk,
  input rst_i,
  input [4:0] led,
  input RXD,
  output TXD
);

  wire clk_i;
  wire resetn;

  reg [31:0] MEM [0:31];
  reg [31:0] instr;
  reg [31:0] PC;

  inital begin
    PC = 0;
    
    //addi x0, x0, 0
    //    imm 12bit- rs1 5bit- funct3 3bit- rd 5bit - opC 7bit
    instr = 32'b0000_0000_0000_0000_0000_0000_0001_0011;

    // add x1, x0, x0
    MEM[1] = 32'b0000_0000_0000_0000_0000_0000_1011_0011;

    // addi x1, x1, 1
    MEM[2] = 32'b0000_0000_0001_0000_1000_0000_1001_0011;

    // addi x1, x1, 1
    MEM[3] = 32'b0000_0000_0001_0000_1000_0000_1001_0011;
  
    // addi x1, x1, 1
    MEM[4] = 32'b0000_0000_0001_0000_1000_0000_1001_0011;

    // ebreak
    MEM[5] = 32'b0000_0000_0001_0000_0000_0000_0111_0011;

  end

    wire isALUreg = (instr[6:0] == 7'b011_0011);
    wire isALUimm = (instr[6:0] == 7'b001_0011);
    wire isLUI = (instr[6:0] == 7'b011_0111);
    wire isAUIPC = (instr[6:0] == 7'b001_0111);
    wire isJAL = (instr[6:0] == 7'b110_1111);
    wire isJALR = (instr[6:0] == 7'b110_0111);
    wire isBRANCH = (instr[6:0] == 7'b110_0011);
    wire isLOAD = (instr[6:0] == 7'b000_0011);
    wire isSTORE = (instr[6:0] == 7'b010_0011);
    wire isSYSTEM = (instr[6:0] == 7'b111_0011);