31 lines
559 B
Verilog
31 lines
559 B
Verilog
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module bench();
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reg CLK; // Main clock
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reg RESET; // Active-low reset
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wire [4:0] LEDS; // LED outputs
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reg RXD = 1'b1; // UART receive (idle high)
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wire TXD; // UART transmit
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// Device Under Test
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SOC uut(
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.clk(CLK),
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.rst_i(RESET),
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.led(LEDS),
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.RXD(RXD),
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.TXD(TXD)
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);
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reg[4:0] prev_LEDS = 0;
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initial begin
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CLK = 0;
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forever begin
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#1 CLK = ~CLK;
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if(LEDS != prev_LEDS) begin
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$display("LEDS = %b",LEDS);
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end
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prev_LEDS <= LEDS;
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end
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end
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endmodule
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