41 lines
947 B
Verilog
41 lines
947 B
Verilog
/**
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* Step 2: Blinker (slower version)
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* DONE*
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*/
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`default_nettype none
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`include "clockworks.v"
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module SOC (
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input clk, // system clock
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input rst_i, // reset button
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output [4:0] led, // system LEDs
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input RXD, // UART receive
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output TXD // UART transmit
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);
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wire clkI; // internal clock
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wire resetn; // internal reset signal, goes low on reset
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// A blinker that counts on 5 bits, wired to the 5 LEDs
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reg [4:0] count = 0;
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always @(posedge clkI) begin
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count <= !resetn ? 0 : count + 1;
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end
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// Clock gearbox (to let you see what happens)
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// and reset circuitry (to workaround an
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// initialization problem with Ice40)
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Clockworks #(
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.SLOW(21) // Divide clock frequency by 2^21
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)CW(
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.CLK(clk),
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.RESET(rst_i),
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.clk(clkI),
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.resetn(resetn)
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);
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assign led = count;
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assign TXD = 1'b0; // not used for now
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endmodule
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