55 lines
1.3 KiB
Verilog
55 lines
1.3 KiB
Verilog
/* Register bank and state machine */
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`default_nettype none
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`include "clockworks.v"
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module SOC (
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input clk,
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input rst_i,
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input [4:0] led,
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input RXD,
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output TXD
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);
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wire clk_i;
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wire resetn;
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reg [31:0] MEM [0:31];
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reg [31:0] instr;
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reg [31:0] PC;
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inital begin
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PC = 0;
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//addi x0, x0, 0
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// imm 12bit- rs1 5bit- funct3 3bit- rd 5bit - opC 7bit
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instr = 32'b0000_0000_0000_0000_0000_0000_0001_0011;
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// add x1, x0, x0
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MEM[1] = 32'b0000_0000_0000_0000_0000_0000_1011_0011;
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// addi x1, x1, 1
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MEM[2] = 32'b0000_0000_0001_0000_1000_0000_1001_0011;
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// addi x1, x1, 1
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MEM[3] = 32'b0000_0000_0001_0000_1000_0000_1001_0011;
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// addi x1, x1, 1
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MEM[4] = 32'b0000_0000_0001_0000_1000_0000_1001_0011;
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// ebreak
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MEM[5] = 32'b0000_0000_0001_0000_0000_0000_0111_0011;
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end
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wire isALUreg = (instr[6:0] == 7'b011_0011);
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wire isALUimm = (instr[6:0] == 7'b001_0011);
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wire isLUI = (instr[6:0] == 7'b011_0111);
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wire isAUIPC = (instr[6:0] == 7'b001_0111);
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wire isJAL = (instr[6:0] == 7'b110_1111);
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wire isJALR = (instr[6:0] == 7'b110_0111);
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wire isBRANCH = (instr[6:0] == 7'b110_0011);
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wire isLOAD = (instr[6:0] == 7'b000_0011);
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wire isSTORE = (instr[6:0] == 7'b010_0011);
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wire isSYSTEM = (instr[6:0] == 7'b111_0011);
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