Files
learnFPGA/FIRMWARE/pipeline.ld
2025-08-02 06:09:31 +03:00

30 lines
566 B
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MEMORY {
PROGROM (RX) : ORIGIN = 0x00000, LENGTH = 0x10000 /* 64kB ROM */
DATARAM (RW) : ORIGIN = 0x10000, LENGTH = 0x10000 /* 64kB RAM */
}
SECTIONS {
.text : {
. = ALIGN(4);
start_pipeline.o (.text)
*(.text*)
} > PROGROM
.data : {
. = ALIGN(4);
*(.data*)
*(.sdata*)
*(.rodata*)
*(.srodata*)
*(.bss*)
*(.sbss*)
*(COMMON)
*(.eh_frame)
*(.eh_frame_hdr)
*(.init_array*)
*(.gcc_except_table*)
} > DATARAM
}