60 lines
1.1 KiB
Verilog
60 lines
1.1 KiB
Verilog
`include "clockworks.v"
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module SOC (
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input clk,
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input rst_i,
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output [4:0] led,
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output TXD,
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input RXD
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);
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wire clkI, resetn;
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reg [4:0] PC = 0;
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reg [4:0] MEM [0:20];
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initial begin
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MEM[0] = 5'b00000;
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MEM[1] = 5'b00001;
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MEM[2] = 5'b00010;
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MEM[3] = 5'b00100;
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MEM[4] = 5'b01000;
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MEM[5] = 5'b10000;
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MEM[6] = 5'b10001;
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MEM[7] = 5'b10010;
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MEM[8] = 5'b10100;
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MEM[9] = 5'b11000;
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MEM[10] = 5'b11001;
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MEM[11] = 5'b11010;
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MEM[12] = 5'b11100;
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MEM[13] = 5'b11101;
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MEM[14] = 5'b11110;
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MEM[15] = 5'b11111;
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MEM[16] = 5'b11110;
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MEM[17] = 5'b11100;
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MEM[18] = 5'b11000;
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MEM[19] = 5'b10000;
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MEM[20] = 5'b00000;
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end
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reg [4:0] leds = 0;
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assign led = leds;
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always @(posedge clkI) begin
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leds <= MEM[PC];
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PC <= (!resetn || PC == 20) ? 0 : (PC + 1);
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end
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Clockworks #(
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.SLOW(21)
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)clkw(
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.CLK(clk),
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.RESET(rst_i),
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.clk(clkI),
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.resetn(resetn)
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);
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assign TXD = 1'b0;
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endmodule
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