36 lines
1.0 KiB
Plaintext
36 lines
1.0 KiB
Plaintext
# See https://github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf
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## Clock #########################################
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LOCATE COMP "CLK" SITE "G2";
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IOBUF PORT "CLK" PULLMODE=NONE IO_TYPE=LVCMOS33;
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FREQUENCY PORT "CLK" 25 MHZ;
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## RESET button ##################################
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LOCATE COMP "RESET" SITE "T1"; # fire 2
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IOBUF PORT "RESET" IO_TYPE=LVCMOS33;
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## LEDs ##########################################
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LOCATE COMP "LEDS[0]" SITE "B2";
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LOCATE COMP "LEDS[1]" SITE "C2";
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LOCATE COMP "LEDS[2]" SITE "C1";
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LOCATE COMP "LEDS[3]" SITE "D2";
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LOCATE COMP "LEDS[4]" SITE "D1";
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IOBUF PORT "LEDS[0]" IO_TYPE=LVCMOS33;
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IOBUF PORT "LEDS[1]" IO_TYPE=LVCMOS33;
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IOBUF PORT "LEDS[2]" IO_TYPE=LVCMOS33;
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IOBUF PORT "LEDS[3]" IO_TYPE=LVCMOS33;
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IOBUF PORT "LEDS[4]" IO_TYPE=LVCMOS33;
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## UART ######################################################
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LOCATE COMP "TXD" SITE "L4"; # FPGA transmits to ftdi
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LOCATE COMP "RXD" SITE "M1"; # FPGA receives from ftdi
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IOBUF PORT "TXD" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
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IOBUF PORT "RXD" PULLMODE=UP IO_TYPE=LVCMOS33;
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