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learnFPGA/FIRMWARE/bram.ld
2025-08-02 06:09:31 +03:00

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MEMORY
{
BRAM (RWX) : ORIGIN = 0x0000, LENGTH = 0x1800 /* 6kB RAM */
}
SECTIONS
{
everything :
{
. = ALIGN(4);
start.o (.text)
*(.*)
} >BRAM
}