Timing Messages
Report Title | Timing Analysis Report |
Design File | \\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\impl\gwsynthesis\seq_light_test.vg |
Physical Constraints File | \\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seq_light_test.cst |
Timing Constraint File | --- |
Tool Version | V1.9.9.03 Education (64-bit) |
Part Number | GW2A-LV18PG256C8/I7 |
Device | GW2A-18 |
Device Version | C |
Created Time | Sun Jul 7 15:45:18 2024 |
Legal Announcement | Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved. |
Timing Summaries
STA Tool Run Summary:
Setup Delay Model | Slow 0.95V 85C C8/I7 |
Hold Delay Model | Fast 1.05V 0C C8/I7 |
Numbers of Paths Analyzed | 82 |
Numbers of Endpoints Analyzed | 81 |
Numbers of Falling Endpoints | 0 |
Numbers of Setup Violated Endpoints | 0 |
Numbers of Hold Violated Endpoints | 1 |
Clock Summary:
Clock Name | Type | Period | Frequency(MHz) | Rise | Fall | Source | Master | Objects |
---|---|---|---|---|---|---|---|---|
clock | Base | 10.000 | 100.000 | 0.000 | 5.000 | clock_ibuf/I | ||
newclk | Base | 10.000 | 100.000 | 0.000 | 5.000 | newclk_s1/Q |
Max Frequency Summary:
NO. | Clock Name | Constraint | Actual Fmax | Logic Level | Entity |
---|---|---|---|---|---|
1 | clock | 100.000(MHz) | 306.038(MHz) | 4 | TOP |
2 | newclk | 100.000(MHz) | 328.985(MHz) | 2 | TOP |
Total Negative Slack Summary:
Clock Name | Analysis Type | Endpoints TNS | Number of Endpoints |
---|---|---|---|
clock | Setup | 0.000 | 0 |
clock | Hold | 0.000 | 0 |
newclk | Setup | 0.000 | 0 |
newclk | Hold | 0.000 | 0 |
Timing Details
Path Slacks Table:
Setup Paths Table
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | 6.732 | clkcnt_26_s0/Q | clkcnt_24_s0/RESET | clock:[R] | clock:[R] | 10.000 | 0.000 | 3.233 |
2 | 6.732 | clkcnt_26_s0/Q | clkcnt_25_s0/RESET | clock:[R] | clock:[R] | 10.000 | 0.000 | 3.233 |
3 | 6.732 | clkcnt_26_s0/Q | clkcnt_26_s0/RESET | clock:[R] | clock:[R] | 10.000 | 0.000 | 3.233 |
4 | 6.732 | clkcnt_26_s0/Q | clkcnt_27_s0/RESET | clock:[R] | clock:[R] | 10.000 | 0.000 | 3.233 |
5 | 6.732 | clkcnt_26_s0/Q | clkcnt_28_s0/RESET | clock:[R] | clock:[R] | 10.000 | 0.000 | 3.233 |
6 | 6.732 | clkcnt_26_s0/Q | clkcnt_29_s0/RESET | clock:[R] | clock:[R] | 10.000 | 0.000 | 3.233 |
7 | 6.740 | clkcnt_26_s0/Q | clkcnt_31_s0/RESET | clock:[R] | clock:[R] | 10.000 | 0.000 | 3.225 |
8 | 6.740 | clkcnt_26_s0/Q | clkcnt_30_s0/RESET | clock:[R] | clock:[R] | 10.000 | 0.000 | 3.225 |
9 | 6.923 | clkcnt_26_s0/Q | clkcnt_12_s0/RESET | clock:[R] | clock:[R] | 10.000 | 0.000 | 3.042 |
10 | 6.923 | clkcnt_26_s0/Q | clkcnt_13_s0/RESET | clock:[R] | clock:[R] | 10.000 | 0.000 | 3.042 |
11 | 6.923 | clkcnt_26_s0/Q | clkcnt_14_s0/RESET | clock:[R] | clock:[R] | 10.000 | 0.000 | 3.042 |
12 | 6.923 | clkcnt_26_s0/Q | clkcnt_15_s0/RESET | clock:[R] | clock:[R] | 10.000 | 0.000 | 3.042 |
13 | 6.923 | clkcnt_26_s0/Q | clkcnt_16_s0/RESET | clock:[R] | clock:[R] | 10.000 | 0.000 | 3.042 |
14 | 6.923 | clkcnt_26_s0/Q | clkcnt_17_s0/RESET | clock:[R] | clock:[R] | 10.000 | 0.000 | 3.042 |
15 | 6.923 | clkcnt_26_s0/Q | clkcnt_18_s0/RESET | clock:[R] | clock:[R] | 10.000 | 0.000 | 3.042 |
16 | 6.923 | clkcnt_26_s0/Q | clkcnt_19_s0/RESET | clock:[R] | clock:[R] | 10.000 | 0.000 | 3.042 |
17 | 6.923 | clkcnt_26_s0/Q | clkcnt_20_s0/RESET | clock:[R] | clock:[R] | 10.000 | 0.000 | 3.042 |
18 | 6.923 | clkcnt_26_s0/Q | clkcnt_21_s0/RESET | clock:[R] | clock:[R] | 10.000 | 0.000 | 3.042 |
19 | 6.923 | clkcnt_26_s0/Q | clkcnt_22_s0/RESET | clock:[R] | clock:[R] | 10.000 | 0.000 | 3.042 |
20 | 6.923 | clkcnt_26_s0/Q | clkcnt_23_s0/RESET | clock:[R] | clock:[R] | 10.000 | 0.000 | 3.042 |
21 | 6.927 | clkcnt_26_s0/Q | clkcnt_1_s0/RESET | clock:[R] | clock:[R] | 10.000 | 0.000 | 3.038 |
22 | 6.927 | clkcnt_26_s0/Q | clkcnt_2_s0/RESET | clock:[R] | clock:[R] | 10.000 | 0.000 | 3.038 |
23 | 6.927 | clkcnt_26_s0/Q | clkcnt_3_s0/RESET | clock:[R] | clock:[R] | 10.000 | 0.000 | 3.038 |
24 | 6.927 | clkcnt_26_s0/Q | clkcnt_4_s0/RESET | clock:[R] | clock:[R] | 10.000 | 0.000 | 3.038 |
25 | 6.927 | clkcnt_26_s0/Q | clkcnt_5_s0/RESET | clock:[R] | clock:[R] | 10.000 | 0.000 | 3.038 |
Hold Paths Table
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path Number | Path Slack | From Node | To Node | From Clock | To Clock | Relation | Clock Skew | Data Delay |
---|---|---|---|---|---|---|---|---|
1 | -4.449 | n72_s2/I0 | newclk_s1/D | newclk:[R] | clock:[R] | 0.000 | -4.638 | 0.234 |
2 | 0.425 | clkcnt_2_s0/Q | clkcnt_2_s0/D | clock:[R] | clock:[R] | 0.000 | 0.000 | 0.436 |
3 | 0.425 | clkcnt_6_s0/Q | clkcnt_6_s0/D | clock:[R] | clock:[R] | 0.000 | 0.000 | 0.436 |
4 | 0.425 | clkcnt_8_s0/Q | clkcnt_8_s0/D | clock:[R] | clock:[R] | 0.000 | 0.000 | 0.436 |
5 | 0.425 | clkcnt_14_s0/Q | clkcnt_14_s0/D | clock:[R] | clock:[R] | 0.000 | 0.000 | 0.436 |
6 | 0.425 | clkcnt_20_s0/Q | clkcnt_20_s0/D | clock:[R] | clock:[R] | 0.000 | 0.000 | 0.436 |
7 | 0.425 | clkcnt_24_s0/Q | clkcnt_24_s0/D | clock:[R] | clock:[R] | 0.000 | 0.000 | 0.436 |
8 | 0.425 | clkcnt_26_s0/Q | clkcnt_26_s0/D | clock:[R] | clock:[R] | 0.000 | 0.000 | 0.436 |
9 | 0.425 | clkcnt_30_s0/Q | clkcnt_30_s0/D | clock:[R] | clock:[R] | 0.000 | 0.000 | 0.436 |
10 | 0.425 | fsm_2_s0/Q | fsm_2_s0/D | newclk:[R] | newclk:[R] | 0.000 | 0.000 | 0.436 |
11 | 0.427 | clkcnt_0_s0/Q | clkcnt_0_s0/D | clock:[R] | clock:[R] | 0.000 | 0.000 | 0.438 |
12 | 0.427 | clkcnt_12_s0/Q | clkcnt_12_s0/D | clock:[R] | clock:[R] | 0.000 | 0.000 | 0.438 |
13 | 0.427 | clkcnt_18_s0/Q | clkcnt_18_s0/D | clock:[R] | clock:[R] | 0.000 | 0.000 | 0.438 |
14 | 0.542 | clkcnt_31_s0/Q | clkcnt_31_s0/D | clock:[R] | clock:[R] | 0.000 | 0.000 | 0.553 |
15 | 0.542 | clkcnt_11_s0/Q | clkcnt_11_s0/D | clock:[R] | clock:[R] | 0.000 | 0.000 | 0.553 |
16 | 0.542 | clkcnt_23_s0/Q | clkcnt_23_s0/D | clock:[R] | clock:[R] | 0.000 | 0.000 | 0.553 |
17 | 0.546 | clkcnt_3_s0/Q | clkcnt_3_s0/D | clock:[R] | clock:[R] | 0.000 | 0.000 | 0.557 |
18 | 0.546 | clkcnt_4_s0/Q | clkcnt_4_s0/D | clock:[R] | clock:[R] | 0.000 | 0.000 | 0.557 |
19 | 0.546 | clkcnt_9_s0/Q | clkcnt_9_s0/D | clock:[R] | clock:[R] | 0.000 | 0.000 | 0.557 |
20 | 0.546 | clkcnt_16_s0/Q | clkcnt_16_s0/D | clock:[R] | clock:[R] | 0.000 | 0.000 | 0.557 |
21 | 0.546 | clkcnt_21_s0/Q | clkcnt_21_s0/D | clock:[R] | clock:[R] | 0.000 | 0.000 | 0.557 |
22 | 0.546 | clkcnt_22_s0/Q | clkcnt_22_s0/D | clock:[R] | clock:[R] | 0.000 | 0.000 | 0.557 |
23 | 0.546 | clkcnt_27_s0/Q | clkcnt_27_s0/D | clock:[R] | clock:[R] | 0.000 | 0.000 | 0.557 |
24 | 0.546 | clkcnt_28_s0/Q | clkcnt_28_s0/D | clock:[R] | clock:[R] | 0.000 | 0.000 | 0.557 |
25 | 0.546 | clkcnt_29_s0/Q | clkcnt_29_s0/D | clock:[R] | clock:[R] | 0.000 | 0.000 | 0.557 |
Recovery Paths Table
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
Nothing to report!
Removal Paths Table
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
Nothing to report!
Minimum Pulse Width Table:
Number | Slack | Actual Width | Required Width | Type | Clock | Objects |
---|---|---|---|---|---|---|
1 | 1.152 | 2.152 | 1.000 | High Pulse Width | clock | clkcnt_30_s0 |
2 | 1.152 | 2.152 | 1.000 | High Pulse Width | clock | clkcnt_29_s0 |
3 | 1.152 | 2.152 | 1.000 | High Pulse Width | clock | clkcnt_27_s0 |
4 | 1.152 | 2.152 | 1.000 | High Pulse Width | clock | clkcnt_23_s0 |
5 | 1.152 | 2.152 | 1.000 | High Pulse Width | clock | clkcnt_15_s0 |
6 | 1.152 | 2.152 | 1.000 | High Pulse Width | clock | clkcnt_31_s0 |
7 | 1.152 | 2.152 | 1.000 | High Pulse Width | clock | clkcnt_0_s0 |
8 | 1.152 | 2.152 | 1.000 | High Pulse Width | clock | clkcnt_16_s0 |
9 | 1.152 | 2.152 | 1.000 | High Pulse Width | clock | clkcnt_1_s0 |
10 | 1.152 | 2.152 | 1.000 | High Pulse Width | clock | clkcnt_2_s0 |
Timing Report By Analysis Type:
Setup Analysis Report
Report Command:report_timing -setup -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | 6.732 |
Data Arrival Time | 9.734 |
Data Required Time | 16.466 |
From | clkcnt_26_s0 |
To | clkcnt_24_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | 1 | R26C31[1][A] | clkcnt_26_s0/CLK |
6.733 | 0.232 | tC2Q | RF | 2 | R26C31[1][A] | clkcnt_26_s0/Q |
6.890 | 0.156 | tNET | FF | 1 | R26C31[3][B] | n38_s108/I1 |
7.460 | 0.570 | tINS | FR | 1 | R26C31[3][B] | n38_s108/F |
7.632 | 0.172 | tNET | RR | 1 | R26C30[3][B] | n38_s100/I3 |
8.187 | 0.555 | tINS | RF | 1 | R26C30[3][B] | n38_s100/F |
8.600 | 0.413 | tNET | FF | 1 | R27C28[0][B] | n38_s96/I3 |
9.170 | 0.570 | tINS | FR | 33 | R27C28[0][B] | n38_s96/F |
9.734 | 0.563 | tNET | RR | 1 | R26C31[0][A] | clkcnt_24_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clock | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
14.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
16.501 | 2.271 | tNET | RR | 1 | R26C31[0][A] | clkcnt_24_s0/CLK |
16.466 | -0.035 | tSu | 1 | R26C31[0][A] | clkcnt_24_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Arrival Data Path Delay | cell: 1.695, 52.435%; route: 1.306, 40.388%; tC2Q: 0.232, 7.177% |
Required Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Path2
Path Summary:
Slack | 6.732 |
Data Arrival Time | 9.734 |
Data Required Time | 16.466 |
From | clkcnt_26_s0 |
To | clkcnt_25_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | 1 | R26C31[1][A] | clkcnt_26_s0/CLK |
6.733 | 0.232 | tC2Q | RF | 2 | R26C31[1][A] | clkcnt_26_s0/Q |
6.890 | 0.156 | tNET | FF | 1 | R26C31[3][B] | n38_s108/I1 |
7.460 | 0.570 | tINS | FR | 1 | R26C31[3][B] | n38_s108/F |
7.632 | 0.172 | tNET | RR | 1 | R26C30[3][B] | n38_s100/I3 |
8.187 | 0.555 | tINS | RF | 1 | R26C30[3][B] | n38_s100/F |
8.600 | 0.413 | tNET | FF | 1 | R27C28[0][B] | n38_s96/I3 |
9.170 | 0.570 | tINS | FR | 33 | R27C28[0][B] | n38_s96/F |
9.734 | 0.563 | tNET | RR | 1 | R26C31[0][B] | clkcnt_25_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clock | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
14.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
16.501 | 2.271 | tNET | RR | 1 | R26C31[0][B] | clkcnt_25_s0/CLK |
16.466 | -0.035 | tSu | 1 | R26C31[0][B] | clkcnt_25_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Arrival Data Path Delay | cell: 1.695, 52.435%; route: 1.306, 40.388%; tC2Q: 0.232, 7.177% |
Required Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Path3
Path Summary:
Slack | 6.732 |
Data Arrival Time | 9.734 |
Data Required Time | 16.466 |
From | clkcnt_26_s0 |
To | clkcnt_26_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | 1 | R26C31[1][A] | clkcnt_26_s0/CLK |
6.733 | 0.232 | tC2Q | RF | 2 | R26C31[1][A] | clkcnt_26_s0/Q |
6.890 | 0.156 | tNET | FF | 1 | R26C31[3][B] | n38_s108/I1 |
7.460 | 0.570 | tINS | FR | 1 | R26C31[3][B] | n38_s108/F |
7.632 | 0.172 | tNET | RR | 1 | R26C30[3][B] | n38_s100/I3 |
8.187 | 0.555 | tINS | RF | 1 | R26C30[3][B] | n38_s100/F |
8.600 | 0.413 | tNET | FF | 1 | R27C28[0][B] | n38_s96/I3 |
9.170 | 0.570 | tINS | FR | 33 | R27C28[0][B] | n38_s96/F |
9.734 | 0.563 | tNET | RR | 1 | R26C31[1][A] | clkcnt_26_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clock | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
14.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
16.501 | 2.271 | tNET | RR | 1 | R26C31[1][A] | clkcnt_26_s0/CLK |
16.466 | -0.035 | tSu | 1 | R26C31[1][A] | clkcnt_26_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Arrival Data Path Delay | cell: 1.695, 52.435%; route: 1.306, 40.388%; tC2Q: 0.232, 7.177% |
Required Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Path4
Path Summary:
Slack | 6.732 |
Data Arrival Time | 9.734 |
Data Required Time | 16.466 |
From | clkcnt_26_s0 |
To | clkcnt_27_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | 1 | R26C31[1][A] | clkcnt_26_s0/CLK |
6.733 | 0.232 | tC2Q | RF | 2 | R26C31[1][A] | clkcnt_26_s0/Q |
6.890 | 0.156 | tNET | FF | 1 | R26C31[3][B] | n38_s108/I1 |
7.460 | 0.570 | tINS | FR | 1 | R26C31[3][B] | n38_s108/F |
7.632 | 0.172 | tNET | RR | 1 | R26C30[3][B] | n38_s100/I3 |
8.187 | 0.555 | tINS | RF | 1 | R26C30[3][B] | n38_s100/F |
8.600 | 0.413 | tNET | FF | 1 | R27C28[0][B] | n38_s96/I3 |
9.170 | 0.570 | tINS | FR | 33 | R27C28[0][B] | n38_s96/F |
9.734 | 0.563 | tNET | RR | 1 | R26C31[1][B] | clkcnt_27_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clock | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
14.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
16.501 | 2.271 | tNET | RR | 1 | R26C31[1][B] | clkcnt_27_s0/CLK |
16.466 | -0.035 | tSu | 1 | R26C31[1][B] | clkcnt_27_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Arrival Data Path Delay | cell: 1.695, 52.435%; route: 1.306, 40.388%; tC2Q: 0.232, 7.177% |
Required Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Path5
Path Summary:
Slack | 6.732 |
Data Arrival Time | 9.734 |
Data Required Time | 16.466 |
From | clkcnt_26_s0 |
To | clkcnt_28_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | 1 | R26C31[1][A] | clkcnt_26_s0/CLK |
6.733 | 0.232 | tC2Q | RF | 2 | R26C31[1][A] | clkcnt_26_s0/Q |
6.890 | 0.156 | tNET | FF | 1 | R26C31[3][B] | n38_s108/I1 |
7.460 | 0.570 | tINS | FR | 1 | R26C31[3][B] | n38_s108/F |
7.632 | 0.172 | tNET | RR | 1 | R26C30[3][B] | n38_s100/I3 |
8.187 | 0.555 | tINS | RF | 1 | R26C30[3][B] | n38_s100/F |
8.600 | 0.413 | tNET | FF | 1 | R27C28[0][B] | n38_s96/I3 |
9.170 | 0.570 | tINS | FR | 33 | R27C28[0][B] | n38_s96/F |
9.734 | 0.563 | tNET | RR | 1 | R26C31[2][A] | clkcnt_28_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clock | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
14.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
16.501 | 2.271 | tNET | RR | 1 | R26C31[2][A] | clkcnt_28_s0/CLK |
16.466 | -0.035 | tSu | 1 | R26C31[2][A] | clkcnt_28_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Arrival Data Path Delay | cell: 1.695, 52.435%; route: 1.306, 40.388%; tC2Q: 0.232, 7.177% |
Required Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Path6
Path Summary:
Slack | 6.732 |
Data Arrival Time | 9.734 |
Data Required Time | 16.466 |
From | clkcnt_26_s0 |
To | clkcnt_29_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | 1 | R26C31[1][A] | clkcnt_26_s0/CLK |
6.733 | 0.232 | tC2Q | RF | 2 | R26C31[1][A] | clkcnt_26_s0/Q |
6.890 | 0.156 | tNET | FF | 1 | R26C31[3][B] | n38_s108/I1 |
7.460 | 0.570 | tINS | FR | 1 | R26C31[3][B] | n38_s108/F |
7.632 | 0.172 | tNET | RR | 1 | R26C30[3][B] | n38_s100/I3 |
8.187 | 0.555 | tINS | RF | 1 | R26C30[3][B] | n38_s100/F |
8.600 | 0.413 | tNET | FF | 1 | R27C28[0][B] | n38_s96/I3 |
9.170 | 0.570 | tINS | FR | 33 | R27C28[0][B] | n38_s96/F |
9.734 | 0.563 | tNET | RR | 1 | R26C31[2][B] | clkcnt_29_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clock | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
14.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
16.501 | 2.271 | tNET | RR | 1 | R26C31[2][B] | clkcnt_29_s0/CLK |
16.466 | -0.035 | tSu | 1 | R26C31[2][B] | clkcnt_29_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Arrival Data Path Delay | cell: 1.695, 52.435%; route: 1.306, 40.388%; tC2Q: 0.232, 7.177% |
Required Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Path7
Path Summary:
Slack | 6.740 |
Data Arrival Time | 9.726 |
Data Required Time | 16.466 |
From | clkcnt_26_s0 |
To | clkcnt_31_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | 1 | R26C31[1][A] | clkcnt_26_s0/CLK |
6.733 | 0.232 | tC2Q | RF | 2 | R26C31[1][A] | clkcnt_26_s0/Q |
6.890 | 0.156 | tNET | FF | 1 | R26C31[3][B] | n38_s108/I1 |
7.460 | 0.570 | tINS | FR | 1 | R26C31[3][B] | n38_s108/F |
7.632 | 0.172 | tNET | RR | 1 | R26C30[3][B] | n38_s100/I3 |
8.187 | 0.555 | tINS | RF | 1 | R26C30[3][B] | n38_s100/F |
8.600 | 0.413 | tNET | FF | 1 | R27C28[0][B] | n38_s96/I3 |
9.170 | 0.570 | tINS | FR | 33 | R27C28[0][B] | n38_s96/F |
9.726 | 0.556 | tNET | RR | 1 | R26C32[0][B] | clkcnt_31_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clock | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
14.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
16.501 | 2.271 | tNET | RR | 1 | R26C32[0][B] | clkcnt_31_s0/CLK |
16.466 | -0.035 | tSu | 1 | R26C32[0][B] | clkcnt_31_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Arrival Data Path Delay | cell: 1.695, 52.554%; route: 1.298, 40.252%; tC2Q: 0.232, 7.193% |
Required Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Path8
Path Summary:
Slack | 6.740 |
Data Arrival Time | 9.726 |
Data Required Time | 16.466 |
From | clkcnt_26_s0 |
To | clkcnt_30_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | 1 | R26C31[1][A] | clkcnt_26_s0/CLK |
6.733 | 0.232 | tC2Q | RF | 2 | R26C31[1][A] | clkcnt_26_s0/Q |
6.890 | 0.156 | tNET | FF | 1 | R26C31[3][B] | n38_s108/I1 |
7.460 | 0.570 | tINS | FR | 1 | R26C31[3][B] | n38_s108/F |
7.632 | 0.172 | tNET | RR | 1 | R26C30[3][B] | n38_s100/I3 |
8.187 | 0.555 | tINS | RF | 1 | R26C30[3][B] | n38_s100/F |
8.600 | 0.413 | tNET | FF | 1 | R27C28[0][B] | n38_s96/I3 |
9.170 | 0.570 | tINS | FR | 33 | R27C28[0][B] | n38_s96/F |
9.726 | 0.556 | tNET | RR | 1 | R26C32[0][A] | clkcnt_30_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clock | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
14.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
16.501 | 2.271 | tNET | RR | 1 | R26C32[0][A] | clkcnt_30_s0/CLK |
16.466 | -0.035 | tSu | 1 | R26C32[0][A] | clkcnt_30_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Arrival Data Path Delay | cell: 1.695, 52.554%; route: 1.298, 40.252%; tC2Q: 0.232, 7.193% |
Required Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Path9
Path Summary:
Slack | 6.923 |
Data Arrival Time | 9.543 |
Data Required Time | 16.466 |
From | clkcnt_26_s0 |
To | clkcnt_12_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | 1 | R26C31[1][A] | clkcnt_26_s0/CLK |
6.733 | 0.232 | tC2Q | RF | 2 | R26C31[1][A] | clkcnt_26_s0/Q |
6.890 | 0.156 | tNET | FF | 1 | R26C31[3][B] | n38_s108/I1 |
7.460 | 0.570 | tINS | FR | 1 | R26C31[3][B] | n38_s108/F |
7.632 | 0.172 | tNET | RR | 1 | R26C30[3][B] | n38_s100/I3 |
8.187 | 0.555 | tINS | RF | 1 | R26C30[3][B] | n38_s100/F |
8.600 | 0.413 | tNET | FF | 1 | R27C28[0][B] | n38_s96/I3 |
9.170 | 0.570 | tINS | FR | 33 | R27C28[0][B] | n38_s96/F |
9.543 | 0.373 | tNET | RR | 1 | R26C29[0][A] | clkcnt_12_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clock | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
14.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
16.501 | 2.271 | tNET | RR | 1 | R26C29[0][A] | clkcnt_12_s0/CLK |
16.466 | -0.035 | tSu | 1 | R26C29[0][A] | clkcnt_12_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Arrival Data Path Delay | cell: 1.695, 55.728%; route: 1.115, 36.645%; tC2Q: 0.232, 7.628% |
Required Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Path10
Path Summary:
Slack | 6.923 |
Data Arrival Time | 9.543 |
Data Required Time | 16.466 |
From | clkcnt_26_s0 |
To | clkcnt_13_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | 1 | R26C31[1][A] | clkcnt_26_s0/CLK |
6.733 | 0.232 | tC2Q | RF | 2 | R26C31[1][A] | clkcnt_26_s0/Q |
6.890 | 0.156 | tNET | FF | 1 | R26C31[3][B] | n38_s108/I1 |
7.460 | 0.570 | tINS | FR | 1 | R26C31[3][B] | n38_s108/F |
7.632 | 0.172 | tNET | RR | 1 | R26C30[3][B] | n38_s100/I3 |
8.187 | 0.555 | tINS | RF | 1 | R26C30[3][B] | n38_s100/F |
8.600 | 0.413 | tNET | FF | 1 | R27C28[0][B] | n38_s96/I3 |
9.170 | 0.570 | tINS | FR | 33 | R27C28[0][B] | n38_s96/F |
9.543 | 0.373 | tNET | RR | 1 | R26C29[0][B] | clkcnt_13_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clock | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
14.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
16.501 | 2.271 | tNET | RR | 1 | R26C29[0][B] | clkcnt_13_s0/CLK |
16.466 | -0.035 | tSu | 1 | R26C29[0][B] | clkcnt_13_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Arrival Data Path Delay | cell: 1.695, 55.728%; route: 1.115, 36.645%; tC2Q: 0.232, 7.628% |
Required Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Path11
Path Summary:
Slack | 6.923 |
Data Arrival Time | 9.543 |
Data Required Time | 16.466 |
From | clkcnt_26_s0 |
To | clkcnt_14_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | 1 | R26C31[1][A] | clkcnt_26_s0/CLK |
6.733 | 0.232 | tC2Q | RF | 2 | R26C31[1][A] | clkcnt_26_s0/Q |
6.890 | 0.156 | tNET | FF | 1 | R26C31[3][B] | n38_s108/I1 |
7.460 | 0.570 | tINS | FR | 1 | R26C31[3][B] | n38_s108/F |
7.632 | 0.172 | tNET | RR | 1 | R26C30[3][B] | n38_s100/I3 |
8.187 | 0.555 | tINS | RF | 1 | R26C30[3][B] | n38_s100/F |
8.600 | 0.413 | tNET | FF | 1 | R27C28[0][B] | n38_s96/I3 |
9.170 | 0.570 | tINS | FR | 33 | R27C28[0][B] | n38_s96/F |
9.543 | 0.373 | tNET | RR | 1 | R26C29[1][A] | clkcnt_14_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clock | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
14.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
16.501 | 2.271 | tNET | RR | 1 | R26C29[1][A] | clkcnt_14_s0/CLK |
16.466 | -0.035 | tSu | 1 | R26C29[1][A] | clkcnt_14_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Arrival Data Path Delay | cell: 1.695, 55.728%; route: 1.115, 36.645%; tC2Q: 0.232, 7.628% |
Required Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Path12
Path Summary:
Slack | 6.923 |
Data Arrival Time | 9.543 |
Data Required Time | 16.466 |
From | clkcnt_26_s0 |
To | clkcnt_15_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | 1 | R26C31[1][A] | clkcnt_26_s0/CLK |
6.733 | 0.232 | tC2Q | RF | 2 | R26C31[1][A] | clkcnt_26_s0/Q |
6.890 | 0.156 | tNET | FF | 1 | R26C31[3][B] | n38_s108/I1 |
7.460 | 0.570 | tINS | FR | 1 | R26C31[3][B] | n38_s108/F |
7.632 | 0.172 | tNET | RR | 1 | R26C30[3][B] | n38_s100/I3 |
8.187 | 0.555 | tINS | RF | 1 | R26C30[3][B] | n38_s100/F |
8.600 | 0.413 | tNET | FF | 1 | R27C28[0][B] | n38_s96/I3 |
9.170 | 0.570 | tINS | FR | 33 | R27C28[0][B] | n38_s96/F |
9.543 | 0.373 | tNET | RR | 1 | R26C29[1][B] | clkcnt_15_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clock | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
14.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
16.501 | 2.271 | tNET | RR | 1 | R26C29[1][B] | clkcnt_15_s0/CLK |
16.466 | -0.035 | tSu | 1 | R26C29[1][B] | clkcnt_15_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Arrival Data Path Delay | cell: 1.695, 55.728%; route: 1.115, 36.645%; tC2Q: 0.232, 7.628% |
Required Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Path13
Path Summary:
Slack | 6.923 |
Data Arrival Time | 9.543 |
Data Required Time | 16.466 |
From | clkcnt_26_s0 |
To | clkcnt_16_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | 1 | R26C31[1][A] | clkcnt_26_s0/CLK |
6.733 | 0.232 | tC2Q | RF | 2 | R26C31[1][A] | clkcnt_26_s0/Q |
6.890 | 0.156 | tNET | FF | 1 | R26C31[3][B] | n38_s108/I1 |
7.460 | 0.570 | tINS | FR | 1 | R26C31[3][B] | n38_s108/F |
7.632 | 0.172 | tNET | RR | 1 | R26C30[3][B] | n38_s100/I3 |
8.187 | 0.555 | tINS | RF | 1 | R26C30[3][B] | n38_s100/F |
8.600 | 0.413 | tNET | FF | 1 | R27C28[0][B] | n38_s96/I3 |
9.170 | 0.570 | tINS | FR | 33 | R27C28[0][B] | n38_s96/F |
9.543 | 0.373 | tNET | RR | 1 | R26C29[2][A] | clkcnt_16_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clock | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
14.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
16.501 | 2.271 | tNET | RR | 1 | R26C29[2][A] | clkcnt_16_s0/CLK |
16.466 | -0.035 | tSu | 1 | R26C29[2][A] | clkcnt_16_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Arrival Data Path Delay | cell: 1.695, 55.728%; route: 1.115, 36.645%; tC2Q: 0.232, 7.628% |
Required Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Path14
Path Summary:
Slack | 6.923 |
Data Arrival Time | 9.543 |
Data Required Time | 16.466 |
From | clkcnt_26_s0 |
To | clkcnt_17_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | 1 | R26C31[1][A] | clkcnt_26_s0/CLK |
6.733 | 0.232 | tC2Q | RF | 2 | R26C31[1][A] | clkcnt_26_s0/Q |
6.890 | 0.156 | tNET | FF | 1 | R26C31[3][B] | n38_s108/I1 |
7.460 | 0.570 | tINS | FR | 1 | R26C31[3][B] | n38_s108/F |
7.632 | 0.172 | tNET | RR | 1 | R26C30[3][B] | n38_s100/I3 |
8.187 | 0.555 | tINS | RF | 1 | R26C30[3][B] | n38_s100/F |
8.600 | 0.413 | tNET | FF | 1 | R27C28[0][B] | n38_s96/I3 |
9.170 | 0.570 | tINS | FR | 33 | R27C28[0][B] | n38_s96/F |
9.543 | 0.373 | tNET | RR | 1 | R26C29[2][B] | clkcnt_17_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clock | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
14.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
16.501 | 2.271 | tNET | RR | 1 | R26C29[2][B] | clkcnt_17_s0/CLK |
16.466 | -0.035 | tSu | 1 | R26C29[2][B] | clkcnt_17_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Arrival Data Path Delay | cell: 1.695, 55.728%; route: 1.115, 36.645%; tC2Q: 0.232, 7.628% |
Required Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Path15
Path Summary:
Slack | 6.923 |
Data Arrival Time | 9.543 |
Data Required Time | 16.466 |
From | clkcnt_26_s0 |
To | clkcnt_18_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | 1 | R26C31[1][A] | clkcnt_26_s0/CLK |
6.733 | 0.232 | tC2Q | RF | 2 | R26C31[1][A] | clkcnt_26_s0/Q |
6.890 | 0.156 | tNET | FF | 1 | R26C31[3][B] | n38_s108/I1 |
7.460 | 0.570 | tINS | FR | 1 | R26C31[3][B] | n38_s108/F |
7.632 | 0.172 | tNET | RR | 1 | R26C30[3][B] | n38_s100/I3 |
8.187 | 0.555 | tINS | RF | 1 | R26C30[3][B] | n38_s100/F |
8.600 | 0.413 | tNET | FF | 1 | R27C28[0][B] | n38_s96/I3 |
9.170 | 0.570 | tINS | FR | 33 | R27C28[0][B] | n38_s96/F |
9.543 | 0.373 | tNET | RR | 1 | R26C30[0][A] | clkcnt_18_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clock | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
14.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
16.501 | 2.271 | tNET | RR | 1 | R26C30[0][A] | clkcnt_18_s0/CLK |
16.466 | -0.035 | tSu | 1 | R26C30[0][A] | clkcnt_18_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Arrival Data Path Delay | cell: 1.695, 55.728%; route: 1.115, 36.645%; tC2Q: 0.232, 7.628% |
Required Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Path16
Path Summary:
Slack | 6.923 |
Data Arrival Time | 9.543 |
Data Required Time | 16.466 |
From | clkcnt_26_s0 |
To | clkcnt_19_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | 1 | R26C31[1][A] | clkcnt_26_s0/CLK |
6.733 | 0.232 | tC2Q | RF | 2 | R26C31[1][A] | clkcnt_26_s0/Q |
6.890 | 0.156 | tNET | FF | 1 | R26C31[3][B] | n38_s108/I1 |
7.460 | 0.570 | tINS | FR | 1 | R26C31[3][B] | n38_s108/F |
7.632 | 0.172 | tNET | RR | 1 | R26C30[3][B] | n38_s100/I3 |
8.187 | 0.555 | tINS | RF | 1 | R26C30[3][B] | n38_s100/F |
8.600 | 0.413 | tNET | FF | 1 | R27C28[0][B] | n38_s96/I3 |
9.170 | 0.570 | tINS | FR | 33 | R27C28[0][B] | n38_s96/F |
9.543 | 0.373 | tNET | RR | 1 | R26C30[0][B] | clkcnt_19_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clock | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
14.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
16.501 | 2.271 | tNET | RR | 1 | R26C30[0][B] | clkcnt_19_s0/CLK |
16.466 | -0.035 | tSu | 1 | R26C30[0][B] | clkcnt_19_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Arrival Data Path Delay | cell: 1.695, 55.728%; route: 1.115, 36.645%; tC2Q: 0.232, 7.628% |
Required Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Path17
Path Summary:
Slack | 6.923 |
Data Arrival Time | 9.543 |
Data Required Time | 16.466 |
From | clkcnt_26_s0 |
To | clkcnt_20_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | 1 | R26C31[1][A] | clkcnt_26_s0/CLK |
6.733 | 0.232 | tC2Q | RF | 2 | R26C31[1][A] | clkcnt_26_s0/Q |
6.890 | 0.156 | tNET | FF | 1 | R26C31[3][B] | n38_s108/I1 |
7.460 | 0.570 | tINS | FR | 1 | R26C31[3][B] | n38_s108/F |
7.632 | 0.172 | tNET | RR | 1 | R26C30[3][B] | n38_s100/I3 |
8.187 | 0.555 | tINS | RF | 1 | R26C30[3][B] | n38_s100/F |
8.600 | 0.413 | tNET | FF | 1 | R27C28[0][B] | n38_s96/I3 |
9.170 | 0.570 | tINS | FR | 33 | R27C28[0][B] | n38_s96/F |
9.543 | 0.373 | tNET | RR | 1 | R26C30[1][A] | clkcnt_20_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clock | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
14.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
16.501 | 2.271 | tNET | RR | 1 | R26C30[1][A] | clkcnt_20_s0/CLK |
16.466 | -0.035 | tSu | 1 | R26C30[1][A] | clkcnt_20_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Arrival Data Path Delay | cell: 1.695, 55.728%; route: 1.115, 36.645%; tC2Q: 0.232, 7.628% |
Required Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Path18
Path Summary:
Slack | 6.923 |
Data Arrival Time | 9.543 |
Data Required Time | 16.466 |
From | clkcnt_26_s0 |
To | clkcnt_21_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | 1 | R26C31[1][A] | clkcnt_26_s0/CLK |
6.733 | 0.232 | tC2Q | RF | 2 | R26C31[1][A] | clkcnt_26_s0/Q |
6.890 | 0.156 | tNET | FF | 1 | R26C31[3][B] | n38_s108/I1 |
7.460 | 0.570 | tINS | FR | 1 | R26C31[3][B] | n38_s108/F |
7.632 | 0.172 | tNET | RR | 1 | R26C30[3][B] | n38_s100/I3 |
8.187 | 0.555 | tINS | RF | 1 | R26C30[3][B] | n38_s100/F |
8.600 | 0.413 | tNET | FF | 1 | R27C28[0][B] | n38_s96/I3 |
9.170 | 0.570 | tINS | FR | 33 | R27C28[0][B] | n38_s96/F |
9.543 | 0.373 | tNET | RR | 1 | R26C30[1][B] | clkcnt_21_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clock | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
14.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
16.501 | 2.271 | tNET | RR | 1 | R26C30[1][B] | clkcnt_21_s0/CLK |
16.466 | -0.035 | tSu | 1 | R26C30[1][B] | clkcnt_21_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Arrival Data Path Delay | cell: 1.695, 55.728%; route: 1.115, 36.645%; tC2Q: 0.232, 7.628% |
Required Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Path19
Path Summary:
Slack | 6.923 |
Data Arrival Time | 9.543 |
Data Required Time | 16.466 |
From | clkcnt_26_s0 |
To | clkcnt_22_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | 1 | R26C31[1][A] | clkcnt_26_s0/CLK |
6.733 | 0.232 | tC2Q | RF | 2 | R26C31[1][A] | clkcnt_26_s0/Q |
6.890 | 0.156 | tNET | FF | 1 | R26C31[3][B] | n38_s108/I1 |
7.460 | 0.570 | tINS | FR | 1 | R26C31[3][B] | n38_s108/F |
7.632 | 0.172 | tNET | RR | 1 | R26C30[3][B] | n38_s100/I3 |
8.187 | 0.555 | tINS | RF | 1 | R26C30[3][B] | n38_s100/F |
8.600 | 0.413 | tNET | FF | 1 | R27C28[0][B] | n38_s96/I3 |
9.170 | 0.570 | tINS | FR | 33 | R27C28[0][B] | n38_s96/F |
9.543 | 0.373 | tNET | RR | 1 | R26C30[2][A] | clkcnt_22_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clock | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
14.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
16.501 | 2.271 | tNET | RR | 1 | R26C30[2][A] | clkcnt_22_s0/CLK |
16.466 | -0.035 | tSu | 1 | R26C30[2][A] | clkcnt_22_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Arrival Data Path Delay | cell: 1.695, 55.728%; route: 1.115, 36.645%; tC2Q: 0.232, 7.628% |
Required Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Path20
Path Summary:
Slack | 6.923 |
Data Arrival Time | 9.543 |
Data Required Time | 16.466 |
From | clkcnt_26_s0 |
To | clkcnt_23_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | 1 | R26C31[1][A] | clkcnt_26_s0/CLK |
6.733 | 0.232 | tC2Q | RF | 2 | R26C31[1][A] | clkcnt_26_s0/Q |
6.890 | 0.156 | tNET | FF | 1 | R26C31[3][B] | n38_s108/I1 |
7.460 | 0.570 | tINS | FR | 1 | R26C31[3][B] | n38_s108/F |
7.632 | 0.172 | tNET | RR | 1 | R26C30[3][B] | n38_s100/I3 |
8.187 | 0.555 | tINS | RF | 1 | R26C30[3][B] | n38_s100/F |
8.600 | 0.413 | tNET | FF | 1 | R27C28[0][B] | n38_s96/I3 |
9.170 | 0.570 | tINS | FR | 33 | R27C28[0][B] | n38_s96/F |
9.543 | 0.373 | tNET | RR | 1 | R26C30[2][B] | clkcnt_23_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clock | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
14.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
16.501 | 2.271 | tNET | RR | 1 | R26C30[2][B] | clkcnt_23_s0/CLK |
16.466 | -0.035 | tSu | 1 | R26C30[2][B] | clkcnt_23_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Arrival Data Path Delay | cell: 1.695, 55.728%; route: 1.115, 36.645%; tC2Q: 0.232, 7.628% |
Required Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Path21
Path Summary:
Slack | 6.927 |
Data Arrival Time | 9.539 |
Data Required Time | 16.466 |
From | clkcnt_26_s0 |
To | clkcnt_1_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | 1 | R26C31[1][A] | clkcnt_26_s0/CLK |
6.733 | 0.232 | tC2Q | RF | 2 | R26C31[1][A] | clkcnt_26_s0/Q |
6.890 | 0.156 | tNET | FF | 1 | R26C31[3][B] | n38_s108/I1 |
7.460 | 0.570 | tINS | FR | 1 | R26C31[3][B] | n38_s108/F |
7.632 | 0.172 | tNET | RR | 1 | R26C30[3][B] | n38_s100/I3 |
8.187 | 0.555 | tINS | RF | 1 | R26C30[3][B] | n38_s100/F |
8.600 | 0.413 | tNET | FF | 1 | R27C28[0][B] | n38_s96/I3 |
9.170 | 0.570 | tINS | FR | 33 | R27C28[0][B] | n38_s96/F |
9.539 | 0.369 | tNET | RR | 1 | R26C27[0][B] | clkcnt_1_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clock | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
14.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
16.501 | 2.271 | tNET | RR | 1 | R26C27[0][B] | clkcnt_1_s0/CLK |
16.466 | -0.035 | tSu | 1 | R26C27[0][B] | clkcnt_1_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Arrival Data Path Delay | cell: 1.695, 55.795%; route: 1.111, 36.568%; tC2Q: 0.232, 7.637% |
Required Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Path22
Path Summary:
Slack | 6.927 |
Data Arrival Time | 9.539 |
Data Required Time | 16.466 |
From | clkcnt_26_s0 |
To | clkcnt_2_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | 1 | R26C31[1][A] | clkcnt_26_s0/CLK |
6.733 | 0.232 | tC2Q | RF | 2 | R26C31[1][A] | clkcnt_26_s0/Q |
6.890 | 0.156 | tNET | FF | 1 | R26C31[3][B] | n38_s108/I1 |
7.460 | 0.570 | tINS | FR | 1 | R26C31[3][B] | n38_s108/F |
7.632 | 0.172 | tNET | RR | 1 | R26C30[3][B] | n38_s100/I3 |
8.187 | 0.555 | tINS | RF | 1 | R26C30[3][B] | n38_s100/F |
8.600 | 0.413 | tNET | FF | 1 | R27C28[0][B] | n38_s96/I3 |
9.170 | 0.570 | tINS | FR | 33 | R27C28[0][B] | n38_s96/F |
9.539 | 0.369 | tNET | RR | 1 | R26C27[1][A] | clkcnt_2_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clock | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
14.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
16.501 | 2.271 | tNET | RR | 1 | R26C27[1][A] | clkcnt_2_s0/CLK |
16.466 | -0.035 | tSu | 1 | R26C27[1][A] | clkcnt_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Arrival Data Path Delay | cell: 1.695, 55.795%; route: 1.111, 36.568%; tC2Q: 0.232, 7.637% |
Required Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Path23
Path Summary:
Slack | 6.927 |
Data Arrival Time | 9.539 |
Data Required Time | 16.466 |
From | clkcnt_26_s0 |
To | clkcnt_3_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | 1 | R26C31[1][A] | clkcnt_26_s0/CLK |
6.733 | 0.232 | tC2Q | RF | 2 | R26C31[1][A] | clkcnt_26_s0/Q |
6.890 | 0.156 | tNET | FF | 1 | R26C31[3][B] | n38_s108/I1 |
7.460 | 0.570 | tINS | FR | 1 | R26C31[3][B] | n38_s108/F |
7.632 | 0.172 | tNET | RR | 1 | R26C30[3][B] | n38_s100/I3 |
8.187 | 0.555 | tINS | RF | 1 | R26C30[3][B] | n38_s100/F |
8.600 | 0.413 | tNET | FF | 1 | R27C28[0][B] | n38_s96/I3 |
9.170 | 0.570 | tINS | FR | 33 | R27C28[0][B] | n38_s96/F |
9.539 | 0.369 | tNET | RR | 1 | R26C27[1][B] | clkcnt_3_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clock | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
14.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
16.501 | 2.271 | tNET | RR | 1 | R26C27[1][B] | clkcnt_3_s0/CLK |
16.466 | -0.035 | tSu | 1 | R26C27[1][B] | clkcnt_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Arrival Data Path Delay | cell: 1.695, 55.795%; route: 1.111, 36.568%; tC2Q: 0.232, 7.637% |
Required Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Path24
Path Summary:
Slack | 6.927 |
Data Arrival Time | 9.539 |
Data Required Time | 16.466 |
From | clkcnt_26_s0 |
To | clkcnt_4_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | 1 | R26C31[1][A] | clkcnt_26_s0/CLK |
6.733 | 0.232 | tC2Q | RF | 2 | R26C31[1][A] | clkcnt_26_s0/Q |
6.890 | 0.156 | tNET | FF | 1 | R26C31[3][B] | n38_s108/I1 |
7.460 | 0.570 | tINS | FR | 1 | R26C31[3][B] | n38_s108/F |
7.632 | 0.172 | tNET | RR | 1 | R26C30[3][B] | n38_s100/I3 |
8.187 | 0.555 | tINS | RF | 1 | R26C30[3][B] | n38_s100/F |
8.600 | 0.413 | tNET | FF | 1 | R27C28[0][B] | n38_s96/I3 |
9.170 | 0.570 | tINS | FR | 33 | R27C28[0][B] | n38_s96/F |
9.539 | 0.369 | tNET | RR | 1 | R26C27[2][A] | clkcnt_4_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clock | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
14.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
16.501 | 2.271 | tNET | RR | 1 | R26C27[2][A] | clkcnt_4_s0/CLK |
16.466 | -0.035 | tSu | 1 | R26C27[2][A] | clkcnt_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Arrival Data Path Delay | cell: 1.695, 55.795%; route: 1.111, 36.568%; tC2Q: 0.232, 7.637% |
Required Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Path25
Path Summary:
Slack | 6.927 |
Data Arrival Time | 9.539 |
Data Required Time | 16.466 |
From | clkcnt_26_s0 |
To | clkcnt_5_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | 1 | R26C31[1][A] | clkcnt_26_s0/CLK |
6.733 | 0.232 | tC2Q | RF | 2 | R26C31[1][A] | clkcnt_26_s0/Q |
6.890 | 0.156 | tNET | FF | 1 | R26C31[3][B] | n38_s108/I1 |
7.460 | 0.570 | tINS | FR | 1 | R26C31[3][B] | n38_s108/F |
7.632 | 0.172 | tNET | RR | 1 | R26C30[3][B] | n38_s100/I3 |
8.187 | 0.555 | tINS | RF | 1 | R26C30[3][B] | n38_s100/F |
8.600 | 0.413 | tNET | FF | 1 | R27C28[0][B] | n38_s96/I3 |
9.170 | 0.570 | tINS | FR | 33 | R27C28[0][B] | n38_s96/F |
9.539 | 0.369 | tNET | RR | 1 | R26C27[2][B] | clkcnt_5_s0/RESET |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
10.000 | 10.000 | active clock edge time | ||||
10.000 | 0.000 | clock | ||||
10.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
14.230 | 4.230 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
16.501 | 2.271 | tNET | RR | 1 | R26C27[2][B] | clkcnt_5_s0/CLK |
16.466 | -0.035 | tSu | 1 | R26C27[2][B] | clkcnt_5_s0 |
Path Statistics:
Clock Skew | 0.000 |
Setup Relationship | 10.000 |
Logic Level | 4 |
Arrival Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Arrival Data Path Delay | cell: 1.695, 55.795%; route: 1.111, 36.568%; tC2Q: 0.232, 7.637% |
Required Clock Path Delay | cell: 4.230, 65.063%; route: 2.271, 34.937% |
Hold Analysis Report
Report Command:report_timing -hold -max_paths 25 -max_common_paths 1
Path1
Path Summary:
Slack | -4.449 |
Data Arrival Time | 0.234 |
Data Required Time | 4.684 |
From | n72_s2 |
To | newclk_s1 |
Launch Clk | newclk:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | newclk | ||||
0.000 | 0.000 | tCL | RR | 8 | R29C28[0][A] | newclk_s1/Q |
0.002 | 0.002 | tNET | RR | 1 | R29C28[0][A] | n72_s2/I0 |
0.234 | 0.232 | tINS | RF | 1 | R29C28[0][A] | n72_s2/F |
0.234 | 0.000 | tNET | FF | 1 | R29C28[0][A] | newclk_s1/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R29C28[0][A] | newclk_s1/CLK |
4.673 | 0.035 | tUnc | newclk_s1 | |||
4.684 | 0.011 | tHld | 1 | R29C28[0][A] | newclk_s1 |
Path Statistics:
Clock Skew | 4.638 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 0.000, 0.000% |
Arrival Data Path Delay | cell: 0.232, 98.957%; route: 0.000, 0.000%; tC2Q: 0.002, 1.043% |
Required Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Path2
Path Summary:
Slack | 0.425 |
Data Arrival Time | 5.074 |
Data Required Time | 4.649 |
From | clkcnt_2_s0 |
To | clkcnt_2_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C27[1][A] | clkcnt_2_s0/CLK |
4.840 | 0.202 | tC2Q | RR | 2 | R26C27[1][A] | clkcnt_2_s0/Q |
4.842 | 0.002 | tNET | RR | 2 | R26C27[1][A] | n35_s/I1 |
5.074 | 0.232 | tINS | RF | 1 | R26C27[1][A] | n35_s/SUM |
5.074 | 0.000 | tNET | FF | 1 | R26C27[1][A] | clkcnt_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C27[1][A] | clkcnt_2_s0/CLK |
4.649 | 0.011 | tHld | 1 | R26C27[1][A] | clkcnt_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Path3
Path Summary:
Slack | 0.425 |
Data Arrival Time | 5.074 |
Data Required Time | 4.649 |
From | clkcnt_6_s0 |
To | clkcnt_6_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C28[0][A] | clkcnt_6_s0/CLK |
4.840 | 0.202 | tC2Q | RR | 2 | R26C28[0][A] | clkcnt_6_s0/Q |
4.842 | 0.002 | tNET | RR | 2 | R26C28[0][A] | n31_s/I1 |
5.074 | 0.232 | tINS | RF | 1 | R26C28[0][A] | n31_s/SUM |
5.074 | 0.000 | tNET | FF | 1 | R26C28[0][A] | clkcnt_6_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C28[0][A] | clkcnt_6_s0/CLK |
4.649 | 0.011 | tHld | 1 | R26C28[0][A] | clkcnt_6_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Path4
Path Summary:
Slack | 0.425 |
Data Arrival Time | 5.074 |
Data Required Time | 4.649 |
From | clkcnt_8_s0 |
To | clkcnt_8_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C28[1][A] | clkcnt_8_s0/CLK |
4.840 | 0.202 | tC2Q | RR | 2 | R26C28[1][A] | clkcnt_8_s0/Q |
4.842 | 0.002 | tNET | RR | 2 | R26C28[1][A] | n29_s/I1 |
5.074 | 0.232 | tINS | RF | 1 | R26C28[1][A] | n29_s/SUM |
5.074 | 0.000 | tNET | FF | 1 | R26C28[1][A] | clkcnt_8_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C28[1][A] | clkcnt_8_s0/CLK |
4.649 | 0.011 | tHld | 1 | R26C28[1][A] | clkcnt_8_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Path5
Path Summary:
Slack | 0.425 |
Data Arrival Time | 5.074 |
Data Required Time | 4.649 |
From | clkcnt_14_s0 |
To | clkcnt_14_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C29[1][A] | clkcnt_14_s0/CLK |
4.840 | 0.202 | tC2Q | RR | 2 | R26C29[1][A] | clkcnt_14_s0/Q |
4.842 | 0.002 | tNET | RR | 2 | R26C29[1][A] | n23_s/I1 |
5.074 | 0.232 | tINS | RF | 1 | R26C29[1][A] | n23_s/SUM |
5.074 | 0.000 | tNET | FF | 1 | R26C29[1][A] | clkcnt_14_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C29[1][A] | clkcnt_14_s0/CLK |
4.649 | 0.011 | tHld | 1 | R26C29[1][A] | clkcnt_14_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Path6
Path Summary:
Slack | 0.425 |
Data Arrival Time | 5.074 |
Data Required Time | 4.649 |
From | clkcnt_20_s0 |
To | clkcnt_20_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C30[1][A] | clkcnt_20_s0/CLK |
4.840 | 0.202 | tC2Q | RR | 2 | R26C30[1][A] | clkcnt_20_s0/Q |
4.842 | 0.002 | tNET | RR | 2 | R26C30[1][A] | n17_s/I1 |
5.074 | 0.232 | tINS | RF | 1 | R26C30[1][A] | n17_s/SUM |
5.074 | 0.000 | tNET | FF | 1 | R26C30[1][A] | clkcnt_20_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C30[1][A] | clkcnt_20_s0/CLK |
4.649 | 0.011 | tHld | 1 | R26C30[1][A] | clkcnt_20_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Path7
Path Summary:
Slack | 0.425 |
Data Arrival Time | 5.074 |
Data Required Time | 4.649 |
From | clkcnt_24_s0 |
To | clkcnt_24_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C31[0][A] | clkcnt_24_s0/CLK |
4.840 | 0.202 | tC2Q | RR | 2 | R26C31[0][A] | clkcnt_24_s0/Q |
4.842 | 0.002 | tNET | RR | 2 | R26C31[0][A] | n13_s/I1 |
5.074 | 0.232 | tINS | RF | 1 | R26C31[0][A] | n13_s/SUM |
5.074 | 0.000 | tNET | FF | 1 | R26C31[0][A] | clkcnt_24_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C31[0][A] | clkcnt_24_s0/CLK |
4.649 | 0.011 | tHld | 1 | R26C31[0][A] | clkcnt_24_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Path8
Path Summary:
Slack | 0.425 |
Data Arrival Time | 5.074 |
Data Required Time | 4.649 |
From | clkcnt_26_s0 |
To | clkcnt_26_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C31[1][A] | clkcnt_26_s0/CLK |
4.840 | 0.202 | tC2Q | RR | 2 | R26C31[1][A] | clkcnt_26_s0/Q |
4.842 | 0.002 | tNET | RR | 2 | R26C31[1][A] | n11_s/I1 |
5.074 | 0.232 | tINS | RF | 1 | R26C31[1][A] | n11_s/SUM |
5.074 | 0.000 | tNET | FF | 1 | R26C31[1][A] | clkcnt_26_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C31[1][A] | clkcnt_26_s0/CLK |
4.649 | 0.011 | tHld | 1 | R26C31[1][A] | clkcnt_26_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Path9
Path Summary:
Slack | 0.425 |
Data Arrival Time | 5.074 |
Data Required Time | 4.649 |
From | clkcnt_30_s0 |
To | clkcnt_30_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C32[0][A] | clkcnt_30_s0/CLK |
4.840 | 0.202 | tC2Q | RR | 2 | R26C32[0][A] | clkcnt_30_s0/Q |
4.842 | 0.002 | tNET | RR | 2 | R26C32[0][A] | n7_s/I1 |
5.074 | 0.232 | tINS | RF | 1 | R26C32[0][A] | n7_s/SUM |
5.074 | 0.000 | tNET | FF | 1 | R26C32[0][A] | clkcnt_30_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C32[0][A] | clkcnt_30_s0/CLK |
4.649 | 0.011 | tHld | 1 | R26C32[0][A] | clkcnt_30_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Path10
Path Summary:
Slack | 0.425 |
Data Arrival Time | 2.197 |
Data Required Time | 1.771 |
From | fsm_2_s0 |
To | fsm_2_s0 |
Launch Clk | newclk:[R] |
Latch Clk | newclk:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | newclk | ||||
0.000 | 0.000 | tCL | RR | 8 | R29C28[0][A] | newclk_s1/Q |
1.760 | 1.760 | tNET | RR | 1 | R27C31[0][A] | fsm_2_s0/CLK |
1.962 | 0.202 | tC2Q | RR | 5 | R27C31[0][A] | fsm_2_s0/Q |
1.965 | 0.002 | tNET | RR | 1 | R27C31[0][A] | n111_s0/I2 |
2.197 | 0.232 | tINS | RF | 1 | R27C31[0][A] | n111_s0/F |
2.197 | 0.000 | tNET | FF | 1 | R27C31[0][A] | fsm_2_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | newclk | ||||
0.000 | 0.000 | tCL | RR | 8 | R29C28[0][A] | newclk_s1/Q |
1.760 | 1.760 | tNET | RR | 1 | R27C31[0][A] | fsm_2_s0/CLK |
1.771 | 0.011 | tHld | 1 | R27C31[0][A] | fsm_2_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 0.000, 0.000%; route: 1.760, 100.000% |
Arrival Data Path Delay | cell: 0.232, 53.157%; route: 0.002, 0.560%; tC2Q: 0.202, 46.283% |
Required Clock Path Delay | cell: 0.000, 0.000%; route: 1.760, 100.000% |
Path11
Path Summary:
Slack | 0.427 |
Data Arrival Time | 5.075 |
Data Required Time | 4.649 |
From | clkcnt_0_s0 |
To | clkcnt_0_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R29C28[1][A] | clkcnt_0_s0/CLK |
4.840 | 0.202 | tC2Q | RR | 3 | R29C28[1][A] | clkcnt_0_s0/Q |
4.843 | 0.004 | tNET | RR | 1 | R29C28[1][A] | n37_s2/I0 |
5.075 | 0.232 | tINS | RF | 1 | R29C28[1][A] | n37_s2/F |
5.075 | 0.000 | tNET | FF | 1 | R29C28[1][A] | clkcnt_0_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R29C28[1][A] | clkcnt_0_s0/CLK |
4.649 | 0.011 | tHld | 1 | R29C28[1][A] | clkcnt_0_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154% |
Required Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Path12
Path Summary:
Slack | 0.427 |
Data Arrival Time | 5.075 |
Data Required Time | 4.649 |
From | clkcnt_12_s0 |
To | clkcnt_12_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C29[0][A] | clkcnt_12_s0/CLK |
4.840 | 0.202 | tC2Q | RR | 3 | R26C29[0][A] | clkcnt_12_s0/Q |
4.843 | 0.004 | tNET | RR | 2 | R26C29[0][A] | n25_s/I1 |
5.075 | 0.232 | tINS | RF | 1 | R26C29[0][A] | n25_s/SUM |
5.075 | 0.000 | tNET | FF | 1 | R26C29[0][A] | clkcnt_12_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C29[0][A] | clkcnt_12_s0/CLK |
4.649 | 0.011 | tHld | 1 | R26C29[0][A] | clkcnt_12_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154% |
Required Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Path13
Path Summary:
Slack | 0.427 |
Data Arrival Time | 5.075 |
Data Required Time | 4.649 |
From | clkcnt_18_s0 |
To | clkcnt_18_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C30[0][A] | clkcnt_18_s0/CLK |
4.840 | 0.202 | tC2Q | RR | 3 | R26C30[0][A] | clkcnt_18_s0/Q |
4.843 | 0.004 | tNET | RR | 2 | R26C30[0][A] | n19_s/I1 |
5.075 | 0.232 | tINS | RF | 1 | R26C30[0][A] | n19_s/SUM |
5.075 | 0.000 | tNET | FF | 1 | R26C30[0][A] | clkcnt_18_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C30[0][A] | clkcnt_18_s0/CLK |
4.649 | 0.011 | tHld | 1 | R26C30[0][A] | clkcnt_18_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Arrival Data Path Delay | cell: 0.232, 53.008%; route: 0.004, 0.838%; tC2Q: 0.202, 46.154% |
Required Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Path14
Path Summary:
Slack | 0.542 |
Data Arrival Time | 5.191 |
Data Required Time | 4.649 |
From | clkcnt_31_s0 |
To | clkcnt_31_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C32[0][B] | clkcnt_31_s0/CLK |
4.839 | 0.201 | tC2Q | RF | 2 | R26C32[0][B] | clkcnt_31_s0/Q |
4.959 | 0.120 | tNET | FF | 2 | R26C32[0][B] | n6_s/I1 |
5.191 | 0.232 | tINS | FF | 1 | R26C32[0][B] | n6_s/SUM |
5.191 | 0.000 | tNET | FF | 1 | R26C32[0][B] | clkcnt_31_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C32[0][B] | clkcnt_31_s0/CLK |
4.649 | 0.011 | tHld | 1 | R26C32[0][B] | clkcnt_31_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Arrival Data Path Delay | cell: 0.232, 41.934%; route: 0.120, 21.736%; tC2Q: 0.201, 36.331% |
Required Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Path15
Path Summary:
Slack | 0.542 |
Data Arrival Time | 5.191 |
Data Required Time | 4.649 |
From | clkcnt_11_s0 |
To | clkcnt_11_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C28[2][B] | clkcnt_11_s0/CLK |
4.839 | 0.201 | tC2Q | RF | 2 | R26C28[2][B] | clkcnt_11_s0/Q |
4.959 | 0.120 | tNET | FF | 2 | R26C28[2][B] | n26_s/I1 |
5.191 | 0.232 | tINS | FF | 1 | R26C28[2][B] | n26_s/SUM |
5.191 | 0.000 | tNET | FF | 1 | R26C28[2][B] | clkcnt_11_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C28[2][B] | clkcnt_11_s0/CLK |
4.649 | 0.011 | tHld | 1 | R26C28[2][B] | clkcnt_11_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Arrival Data Path Delay | cell: 0.232, 41.934%; route: 0.120, 21.736%; tC2Q: 0.201, 36.331% |
Required Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Path16
Path Summary:
Slack | 0.542 |
Data Arrival Time | 5.191 |
Data Required Time | 4.649 |
From | clkcnt_23_s0 |
To | clkcnt_23_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C30[2][B] | clkcnt_23_s0/CLK |
4.839 | 0.201 | tC2Q | RF | 3 | R26C30[2][B] | clkcnt_23_s0/Q |
4.959 | 0.120 | tNET | FF | 2 | R26C30[2][B] | n14_s/I1 |
5.191 | 0.232 | tINS | FF | 1 | R26C30[2][B] | n14_s/SUM |
5.191 | 0.000 | tNET | FF | 1 | R26C30[2][B] | clkcnt_23_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C30[2][B] | clkcnt_23_s0/CLK |
4.649 | 0.011 | tHld | 1 | R26C30[2][B] | clkcnt_23_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Arrival Data Path Delay | cell: 0.232, 41.934%; route: 0.120, 21.736%; tC2Q: 0.201, 36.331% |
Required Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Path17
Path Summary:
Slack | 0.546 |
Data Arrival Time | 5.194 |
Data Required Time | 4.649 |
From | clkcnt_3_s0 |
To | clkcnt_3_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C27[1][B] | clkcnt_3_s0/CLK |
4.839 | 0.201 | tC2Q | RF | 2 | R26C27[1][B] | clkcnt_3_s0/Q |
4.962 | 0.124 | tNET | FF | 2 | R26C27[1][B] | n34_s/I1 |
5.194 | 0.232 | tINS | FF | 1 | R26C27[1][B] | n34_s/SUM |
5.194 | 0.000 | tNET | FF | 1 | R26C27[1][B] | clkcnt_3_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C27[1][B] | clkcnt_3_s0/CLK |
4.649 | 0.011 | tHld | 1 | R26C27[1][B] | clkcnt_3_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Arrival Data Path Delay | cell: 0.232, 41.676%; route: 0.124, 22.216%; tC2Q: 0.201, 36.107% |
Required Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Path18
Path Summary:
Slack | 0.546 |
Data Arrival Time | 5.194 |
Data Required Time | 4.649 |
From | clkcnt_4_s0 |
To | clkcnt_4_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C27[2][A] | clkcnt_4_s0/CLK |
4.839 | 0.201 | tC2Q | RF | 2 | R26C27[2][A] | clkcnt_4_s0/Q |
4.962 | 0.124 | tNET | FF | 2 | R26C27[2][A] | n33_s/I1 |
5.194 | 0.232 | tINS | FF | 1 | R26C27[2][A] | n33_s/SUM |
5.194 | 0.000 | tNET | FF | 1 | R26C27[2][A] | clkcnt_4_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C27[2][A] | clkcnt_4_s0/CLK |
4.649 | 0.011 | tHld | 1 | R26C27[2][A] | clkcnt_4_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Arrival Data Path Delay | cell: 0.232, 41.676%; route: 0.124, 22.216%; tC2Q: 0.201, 36.107% |
Required Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Path19
Path Summary:
Slack | 0.546 |
Data Arrival Time | 5.194 |
Data Required Time | 4.649 |
From | clkcnt_9_s0 |
To | clkcnt_9_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C28[1][B] | clkcnt_9_s0/CLK |
4.839 | 0.201 | tC2Q | RF | 2 | R26C28[1][B] | clkcnt_9_s0/Q |
4.962 | 0.124 | tNET | FF | 2 | R26C28[1][B] | n28_s/I1 |
5.194 | 0.232 | tINS | FF | 1 | R26C28[1][B] | n28_s/SUM |
5.194 | 0.000 | tNET | FF | 1 | R26C28[1][B] | clkcnt_9_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C28[1][B] | clkcnt_9_s0/CLK |
4.649 | 0.011 | tHld | 1 | R26C28[1][B] | clkcnt_9_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Arrival Data Path Delay | cell: 0.232, 41.676%; route: 0.124, 22.216%; tC2Q: 0.201, 36.107% |
Required Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Path20
Path Summary:
Slack | 0.546 |
Data Arrival Time | 5.194 |
Data Required Time | 4.649 |
From | clkcnt_16_s0 |
To | clkcnt_16_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C29[2][A] | clkcnt_16_s0/CLK |
4.839 | 0.201 | tC2Q | RF | 2 | R26C29[2][A] | clkcnt_16_s0/Q |
4.962 | 0.124 | tNET | FF | 2 | R26C29[2][A] | n21_s/I1 |
5.194 | 0.232 | tINS | FF | 1 | R26C29[2][A] | n21_s/SUM |
5.194 | 0.000 | tNET | FF | 1 | R26C29[2][A] | clkcnt_16_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C29[2][A] | clkcnt_16_s0/CLK |
4.649 | 0.011 | tHld | 1 | R26C29[2][A] | clkcnt_16_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Arrival Data Path Delay | cell: 0.232, 41.676%; route: 0.124, 22.216%; tC2Q: 0.201, 36.107% |
Required Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Path21
Path Summary:
Slack | 0.546 |
Data Arrival Time | 5.194 |
Data Required Time | 4.649 |
From | clkcnt_21_s0 |
To | clkcnt_21_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C30[1][B] | clkcnt_21_s0/CLK |
4.839 | 0.201 | tC2Q | RF | 2 | R26C30[1][B] | clkcnt_21_s0/Q |
4.962 | 0.124 | tNET | FF | 2 | R26C30[1][B] | n16_s/I1 |
5.194 | 0.232 | tINS | FF | 1 | R26C30[1][B] | n16_s/SUM |
5.194 | 0.000 | tNET | FF | 1 | R26C30[1][B] | clkcnt_21_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C30[1][B] | clkcnt_21_s0/CLK |
4.649 | 0.011 | tHld | 1 | R26C30[1][B] | clkcnt_21_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Arrival Data Path Delay | cell: 0.232, 41.676%; route: 0.124, 22.216%; tC2Q: 0.201, 36.107% |
Required Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Path22
Path Summary:
Slack | 0.546 |
Data Arrival Time | 5.194 |
Data Required Time | 4.649 |
From | clkcnt_22_s0 |
To | clkcnt_22_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C30[2][A] | clkcnt_22_s0/CLK |
4.839 | 0.201 | tC2Q | RF | 2 | R26C30[2][A] | clkcnt_22_s0/Q |
4.962 | 0.124 | tNET | FF | 2 | R26C30[2][A] | n15_s/I1 |
5.194 | 0.232 | tINS | FF | 1 | R26C30[2][A] | n15_s/SUM |
5.194 | 0.000 | tNET | FF | 1 | R26C30[2][A] | clkcnt_22_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C30[2][A] | clkcnt_22_s0/CLK |
4.649 | 0.011 | tHld | 1 | R26C30[2][A] | clkcnt_22_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Arrival Data Path Delay | cell: 0.232, 41.676%; route: 0.124, 22.216%; tC2Q: 0.201, 36.107% |
Required Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Path23
Path Summary:
Slack | 0.546 |
Data Arrival Time | 5.194 |
Data Required Time | 4.649 |
From | clkcnt_27_s0 |
To | clkcnt_27_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C31[1][B] | clkcnt_27_s0/CLK |
4.839 | 0.201 | tC2Q | RF | 2 | R26C31[1][B] | clkcnt_27_s0/Q |
4.962 | 0.124 | tNET | FF | 2 | R26C31[1][B] | n10_s/I1 |
5.194 | 0.232 | tINS | FF | 1 | R26C31[1][B] | n10_s/SUM |
5.194 | 0.000 | tNET | FF | 1 | R26C31[1][B] | clkcnt_27_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C31[1][B] | clkcnt_27_s0/CLK |
4.649 | 0.011 | tHld | 1 | R26C31[1][B] | clkcnt_27_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Arrival Data Path Delay | cell: 0.232, 41.676%; route: 0.124, 22.216%; tC2Q: 0.201, 36.107% |
Required Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Path24
Path Summary:
Slack | 0.546 |
Data Arrival Time | 5.194 |
Data Required Time | 4.649 |
From | clkcnt_28_s0 |
To | clkcnt_28_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C31[2][A] | clkcnt_28_s0/CLK |
4.839 | 0.201 | tC2Q | RF | 2 | R26C31[2][A] | clkcnt_28_s0/Q |
4.962 | 0.124 | tNET | FF | 2 | R26C31[2][A] | n9_s/I1 |
5.194 | 0.232 | tINS | FF | 1 | R26C31[2][A] | n9_s/SUM |
5.194 | 0.000 | tNET | FF | 1 | R26C31[2][A] | clkcnt_28_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C31[2][A] | clkcnt_28_s0/CLK |
4.649 | 0.011 | tHld | 1 | R26C31[2][A] | clkcnt_28_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Arrival Data Path Delay | cell: 0.232, 41.676%; route: 0.124, 22.216%; tC2Q: 0.201, 36.107% |
Required Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Path25
Path Summary:
Slack | 0.546 |
Data Arrival Time | 5.194 |
Data Required Time | 4.649 |
From | clkcnt_29_s0 |
To | clkcnt_29_s0 |
Launch Clk | clock:[R] |
Latch Clk | clock:[R] |
Data Arrival Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C31[2][B] | clkcnt_29_s0/CLK |
4.839 | 0.201 | tC2Q | RF | 2 | R26C31[2][B] | clkcnt_29_s0/Q |
4.962 | 0.124 | tNET | FF | 2 | R26C31[2][B] | n8_s/I1 |
5.194 | 0.232 | tINS | FF | 1 | R26C31[2][B] | n8_s/SUM |
5.194 | 0.000 | tNET | FF | 1 | R26C31[2][B] | clkcnt_29_s0/D |
Data Required Path:
AT | DELAY | TYPE | RF | FANOUT | LOC | NODE |
---|---|---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||||
0.000 | 0.000 | clock | ||||
0.000 | 0.000 | tCL | RR | 1 | IOT27[A] | clock_ibuf/I |
3.126 | 3.126 | tINS | RR | 33 | IOT27[A] | clock_ibuf/O |
4.638 | 1.511 | tNET | RR | 1 | R26C31[2][B] | clkcnt_29_s0/CLK |
4.649 | 0.011 | tHld | 1 | R26C31[2][B] | clkcnt_29_s0 |
Path Statistics:
Clock Skew | 0.000 |
Hold Relationship | 0.000 |
Logic Level | 2 |
Arrival Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Arrival Data Path Delay | cell: 0.232, 41.676%; route: 0.124, 22.216%; tC2Q: 0.201, 36.107% |
Required Clock Path Delay | cell: 3.126, 67.413%; route: 1.511, 32.587% |
Recovery Analysis Report
Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1
No recovery paths to report!
Removal Analysis Report
Report Command:report_timing -removal -max_paths 25 -max_common_paths 1
No removal paths to report!
Minimum Pulse Width Report:
Report Command:report_min_pulse_width -nworst 10 -detail
MPW1
MPW Summary:
Slack: | 1.152 |
Actual Width: | 2.152 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clock |
Objects: | clkcnt_30_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clock | ||
0.000 | 0.000 | tCL | RR | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | clkcnt_30_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clock | ||
5.000 | 0.000 | tCL | FF | clock_ibuf/I |
7.140 | 2.140 | tINS | FF | clock_ibuf/O |
8.653 | 1.514 | tNET | FF | clkcnt_30_s0/CLK |
MPW2
MPW Summary:
Slack: | 1.152 |
Actual Width: | 2.152 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clock |
Objects: | clkcnt_29_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clock | ||
0.000 | 0.000 | tCL | RR | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | clkcnt_29_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clock | ||
5.000 | 0.000 | tCL | FF | clock_ibuf/I |
7.140 | 2.140 | tINS | FF | clock_ibuf/O |
8.653 | 1.514 | tNET | FF | clkcnt_29_s0/CLK |
MPW3
MPW Summary:
Slack: | 1.152 |
Actual Width: | 2.152 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clock |
Objects: | clkcnt_27_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clock | ||
0.000 | 0.000 | tCL | RR | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | clkcnt_27_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clock | ||
5.000 | 0.000 | tCL | FF | clock_ibuf/I |
7.140 | 2.140 | tINS | FF | clock_ibuf/O |
8.653 | 1.514 | tNET | FF | clkcnt_27_s0/CLK |
MPW4
MPW Summary:
Slack: | 1.152 |
Actual Width: | 2.152 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clock |
Objects: | clkcnt_23_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clock | ||
0.000 | 0.000 | tCL | RR | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | clkcnt_23_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clock | ||
5.000 | 0.000 | tCL | FF | clock_ibuf/I |
7.140 | 2.140 | tINS | FF | clock_ibuf/O |
8.653 | 1.514 | tNET | FF | clkcnt_23_s0/CLK |
MPW5
MPW Summary:
Slack: | 1.152 |
Actual Width: | 2.152 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clock |
Objects: | clkcnt_15_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clock | ||
0.000 | 0.000 | tCL | RR | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | clkcnt_15_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clock | ||
5.000 | 0.000 | tCL | FF | clock_ibuf/I |
7.140 | 2.140 | tINS | FF | clock_ibuf/O |
8.653 | 1.514 | tNET | FF | clkcnt_15_s0/CLK |
MPW6
MPW Summary:
Slack: | 1.152 |
Actual Width: | 2.152 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clock |
Objects: | clkcnt_31_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clock | ||
0.000 | 0.000 | tCL | RR | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | clkcnt_31_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clock | ||
5.000 | 0.000 | tCL | FF | clock_ibuf/I |
7.140 | 2.140 | tINS | FF | clock_ibuf/O |
8.653 | 1.514 | tNET | FF | clkcnt_31_s0/CLK |
MPW7
MPW Summary:
Slack: | 1.152 |
Actual Width: | 2.152 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clock |
Objects: | clkcnt_0_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clock | ||
0.000 | 0.000 | tCL | RR | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | clkcnt_0_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clock | ||
5.000 | 0.000 | tCL | FF | clock_ibuf/I |
7.140 | 2.140 | tINS | FF | clock_ibuf/O |
8.653 | 1.514 | tNET | FF | clkcnt_0_s0/CLK |
MPW8
MPW Summary:
Slack: | 1.152 |
Actual Width: | 2.152 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clock |
Objects: | clkcnt_16_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clock | ||
0.000 | 0.000 | tCL | RR | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | clkcnt_16_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clock | ||
5.000 | 0.000 | tCL | FF | clock_ibuf/I |
7.140 | 2.140 | tINS | FF | clock_ibuf/O |
8.653 | 1.514 | tNET | FF | clkcnt_16_s0/CLK |
MPW9
MPW Summary:
Slack: | 1.152 |
Actual Width: | 2.152 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clock |
Objects: | clkcnt_1_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clock | ||
0.000 | 0.000 | tCL | RR | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | clkcnt_1_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clock | ||
5.000 | 0.000 | tCL | FF | clock_ibuf/I |
7.140 | 2.140 | tINS | FF | clock_ibuf/O |
8.653 | 1.514 | tNET | FF | clkcnt_1_s0/CLK |
MPW10
MPW Summary:
Slack: | 1.152 |
Actual Width: | 2.152 |
Required Width: | 1.000 |
Type: | High Pulse Width |
Clock: | clock |
Objects: | clkcnt_2_s0 |
Late clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
0.000 | 0.000 | active clock edge time | ||
0.000 | 0.000 | clock | ||
0.000 | 0.000 | tCL | RR | clock_ibuf/I |
4.230 | 4.230 | tINS | RR | clock_ibuf/O |
6.501 | 2.271 | tNET | RR | clkcnt_2_s0/CLK |
Early clock Path:
AT | DELAY | TYPE | RF | NODE |
---|---|---|---|---|
5.000 | 0.000 | active clock edge time | ||
5.000 | 0.000 | clock | ||
5.000 | 0.000 | tCL | FF | clock_ibuf/I |
7.140 | 2.140 | tINS | FF | clock_ibuf/O |
8.653 | 1.514 | tNET | FF | clkcnt_2_s0/CLK |
High Fanout Nets Report:
Report Command:report_high_fanout_nets -max_nets 10
FANOUT | NET NAME | WORST SLACK | MAX DELAY |
---|---|---|---|
33 | clock_d | 6.732 | 2.274 |
33 | n38_132 | 6.732 | 0.702 |
8 | newclk | 6.960 | 2.669 |
7 | fsm[0] | 6.960 | 0.197 |
7 | fsm[1] | 7.132 | 0.989 |
5 | fsm[2] | 6.998 | 0.180 |
3 | clkcnt[23] | 7.185 | 0.424 |
3 | n109_5 | 8.854 | 0.162 |
3 | clkcnt[12] | 7.060 | 0.419 |
3 | clkcnt[15] | 7.183 | 0.169 |
Route Congestions Report:
Report Command:report_route_congestion -max_grids 10
GRID LOC | ROUTE CONGESTIONS |
---|---|
R26C29 | 80.56% |
R26C28 | 79.17% |
R26C30 | 79.17% |
R26C31 | 77.78% |
R26C27 | 59.72% |
R27C31 | 48.61% |
R26C32 | 40.28% |
R29C28 | 31.94% |
R27C28 | 8.33% |
R28C31 | 5.56% |
Timing Exceptions Report:
Setup Analysis Report
Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Hold Analysis Report
Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Recovery Analysis Report
Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Removal Analysis Report
Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1
No timing exceptions to report!
Timing Constraints Report:
SDC Command Type | State | Detail Command |
---|