Synthesis Messages

Report Title GowinSynthesis Report
Design File \\wsl.localhost\Debian\home\koray\code\verilog\gowin\seq_light_test\src\seqBlink.v
GowinSynthesis Constraints File ---
Tool Version V1.9.9.03 Education (64-bit)
Part Number GW2A-LV18PG256C8/I7
Device GW2A-18
Device Version C
Created Time Sun Jul 7 15:45:04 2024
Legal Announcement Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.

Synthesis Details

Top Level Module seqBlink
Synthesis Process Running parser:
    CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.294s, Peak memory usage = 439.246MB
Running netlist conversion:
    CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB
Running device independent optimization:
    Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 439.246MB
    Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.008s, Peak memory usage = 439.246MB
    Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.009s, Peak memory usage = 439.246MB
Running inference:
    Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.007s, Peak memory usage = 439.246MB
    Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 439.246MB
    Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 439.246MB
    Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 439.246MB
Running technical mapping:
    Tech-Mapping Phase 0: CPU time = 0h 0m 0.062s, Elapsed time = 0h 0m 0.017s, Peak memory usage = 439.246MB
    Tech-Mapping Phase 1: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.006s, Peak memory usage = 439.246MB
    Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 439.246MB
    Tech-Mapping Phase 3: CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.351s, Peak memory usage = 439.246MB
    Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 439.246MB
Generate output files:
    CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.035s, Peak memory usage = 439.246MB
Total Time and Memory Usage CPU time = 0h 0m 0.372s, Elapsed time = 0h 0m 0.749s, Peak memory usage = 439.246MB

Resource

Resource Usage Summary

Resource Usage
I/O Port 5
I/O Buf 5
    IBUF 1
    OBUF 4
Register 40
    DFF 3
    DFFE 1
    DFFS 1
    DFFR 35
LUT 19
    LUT2 1
    LUT3 7
    LUT4 11
ALU 31
    ALU 31
INV 4
    INV 4

Resource Utilization Summary

Resource Usage Utilization
Logic 54(23 LUT, 31 ALU) / 20736 <1%
Register 40 / 16173 <1%
  --Register as Latch 0 / 16173 0%
  --Register as FF 40 / 16173 <1%
BSRAM 0 / 46 0%

Timing

Clock Summary:

Clock Name Type Period Frequency(MHz) Rise Fall Source Master Object
clock Base 10.000 100.0 0.000 5.000 clock_ibuf/I
newclk Base 10.000 100.0 0.000 5.000 newclk_s1/Q

Max Frequency Summary:

No. Clock Name Constraint Actual Fmax Logic Level Entity
1 clock 100.000(MHz) 268.168(MHz) 4 TOP
2 newclk 100.000(MHz) 564.972(MHz) 2 TOP

Detail Timing Paths Information

Path 1

Path Summary:
Slack 3.825
Data Arrival Time 6.465
Data Required Time 10.290
From n72_s2
To newclk_s1
Launch Clk newclk[R]
Latch Clk clock[F]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
5.000 0.000 newclk
5.000 0.000 tCL FF 8 newclk_s1/Q
5.474 0.474 tNET FF 1 n72_s2/I0
5.991 0.517 tINS FF 1 n72_s2/F
6.465 0.474 tNET FF 1 newclk_s1/D
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clock
10.000 0.000 tCL RR 1 clock_ibuf/I
10.000 0.000 tINS RR 33 clock_ibuf/O
10.360 0.360 tNET RR 1 newclk_s1/CLK
10.325 -0.035 tUnc newclk_s1
10.290 -0.035 tSu 1 newclk_s1
Path Statistics:
Clock Skew: 0.360
Setup Relationship: 5.000
Logic Level: 2
Arrival Clock Path Delay: cell: 0.000, 100.000%; route: 0.000, 0.000%
Arrival Data Path Delay: cell: 0.517, 35.290%; route: 0.474, 32.355%; tC2Q: 0.474, 32.355%
Required Clock Path Delay: cell: 0.000, 100.000%; route: 0.000, 0.000%

Path 2

Path Summary:
Slack 6.271
Data Arrival Time 4.054
Data Required Time 10.325
From clkcnt_9_s0
To newclk_s1
Launch Clk clock[R]
Latch Clk clock[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clock
0.000 0.000 tCL RR 1 clock_ibuf/I
0.000 0.000 tINS RR 33 clock_ibuf/O
0.360 0.360 tNET RR 1 clkcnt_9_s0/CLK
0.592 0.232 tC2Q RF 2 clkcnt_9_s0/Q
1.066 0.474 tNET FF 1 n38_s103/I1
1.621 0.555 tINS FF 1 n38_s103/F
2.095 0.474 tNET FF 1 n38_s98/I1
2.650 0.555 tINS FF 1 n38_s98/F
3.124 0.474 tNET FF 1 n38_s96/I1
3.694 0.570 tINS FR 33 n38_s96/F
4.054 0.360 tNET RR 1 newclk_s1/CE
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clock
10.000 0.000 tCL RR 1 clock_ibuf/I
10.000 0.000 tINS RR 33 clock_ibuf/O
10.360 0.360 tNET RR 1 newclk_s1/CLK
10.325 -0.035 tSu 1 newclk_s1
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 1.680, 45.479%; route: 1.782, 48.241%; tC2Q: 0.232, 6.280%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 3

Path Summary:
Slack 6.271
Data Arrival Time 4.054
Data Required Time 10.325
From clkcnt_9_s0
To clkcnt_31_s0
Launch Clk clock[R]
Latch Clk clock[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clock
0.000 0.000 tCL RR 1 clock_ibuf/I
0.000 0.000 tINS RR 33 clock_ibuf/O
0.360 0.360 tNET RR 1 clkcnt_9_s0/CLK
0.592 0.232 tC2Q RF 2 clkcnt_9_s0/Q
1.066 0.474 tNET FF 1 n38_s103/I1
1.621 0.555 tINS FF 1 n38_s103/F
2.095 0.474 tNET FF 1 n38_s98/I1
2.650 0.555 tINS FF 1 n38_s98/F
3.124 0.474 tNET FF 1 n38_s96/I1
3.694 0.570 tINS FR 33 n38_s96/F
4.054 0.360 tNET RR 1 clkcnt_31_s0/RESET
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clock
10.000 0.000 tCL RR 1 clock_ibuf/I
10.000 0.000 tINS RR 33 clock_ibuf/O
10.360 0.360 tNET RR 1 clkcnt_31_s0/CLK
10.325 -0.035 tSu 1 clkcnt_31_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 1.680, 45.479%; route: 1.782, 48.241%; tC2Q: 0.232, 6.280%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 4

Path Summary:
Slack 6.271
Data Arrival Time 4.054
Data Required Time 10.325
From clkcnt_9_s0
To clkcnt_0_s0
Launch Clk clock[R]
Latch Clk clock[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clock
0.000 0.000 tCL RR 1 clock_ibuf/I
0.000 0.000 tINS RR 33 clock_ibuf/O
0.360 0.360 tNET RR 1 clkcnt_9_s0/CLK
0.592 0.232 tC2Q RF 2 clkcnt_9_s0/Q
1.066 0.474 tNET FF 1 n38_s103/I1
1.621 0.555 tINS FF 1 n38_s103/F
2.095 0.474 tNET FF 1 n38_s98/I1
2.650 0.555 tINS FF 1 n38_s98/F
3.124 0.474 tNET FF 1 n38_s96/I1
3.694 0.570 tINS FR 33 n38_s96/F
4.054 0.360 tNET RR 1 clkcnt_0_s0/RESET
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clock
10.000 0.000 tCL RR 1 clock_ibuf/I
10.000 0.000 tINS RR 33 clock_ibuf/O
10.360 0.360 tNET RR 1 clkcnt_0_s0/CLK
10.325 -0.035 tSu 1 clkcnt_0_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 1.680, 45.479%; route: 1.782, 48.241%; tC2Q: 0.232, 6.280%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%

Path 5

Path Summary:
Slack 6.271
Data Arrival Time 4.054
Data Required Time 10.325
From clkcnt_9_s0
To clkcnt_1_s0
Launch Clk clock[R]
Latch Clk clock[R]
Data Arrival Path:
AT DELAY TYPE RF FANOUT NODE
0.000 0.000 clock
0.000 0.000 tCL RR 1 clock_ibuf/I
0.000 0.000 tINS RR 33 clock_ibuf/O
0.360 0.360 tNET RR 1 clkcnt_9_s0/CLK
0.592 0.232 tC2Q RF 2 clkcnt_9_s0/Q
1.066 0.474 tNET FF 1 n38_s103/I1
1.621 0.555 tINS FF 1 n38_s103/F
2.095 0.474 tNET FF 1 n38_s98/I1
2.650 0.555 tINS FF 1 n38_s98/F
3.124 0.474 tNET FF 1 n38_s96/I1
3.694 0.570 tINS FR 33 n38_s96/F
4.054 0.360 tNET RR 1 clkcnt_1_s0/RESET
Data Required Path:
AT DELAY TYPE RF FANOUT NODE
10.000 0.000 clock
10.000 0.000 tCL RR 1 clock_ibuf/I
10.000 0.000 tINS RR 33 clock_ibuf/O
10.360 0.360 tNET RR 1 clkcnt_1_s0/CLK
10.325 -0.035 tSu 1 clkcnt_1_s0
Path Statistics:
Clock Skew: 0.000
Setup Relationship: 10.000
Logic Level: 4
Arrival Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%
Arrival Data Path Delay: cell: 1.680, 45.479%; route: 1.782, 48.241%; tC2Q: 0.232, 6.280%
Required Clock Path Delay: cell: 0.000, 0.000%; route: 0.360, 100.000%