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rearrangement

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This commit is contained in:
k0rrluna
2024-12-01 02:01:08 +03:00
parent 7466f916d3
commit 0237c7bcb2
277 changed files with 56884 additions and 56884 deletions
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58
gowin/fpga_project/impl/pnr/fpga_project.log
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@ -1,29 +1,29 @@
Reading netlist file: "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project.vg"
Parsing netlist file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project.vg" completed
Processing netlist completed
Reading constraint file: "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fpga_project.cst"
Physical Constraint parsed completed
Running placement......
[10%] Placement Phase 0 completed
[20%] Placement Phase 1 completed
[30%] Placement Phase 2 completed
[50%] Placement Phase 3 completed
Running routing......
[60%] Routing Phase 0 completed
[70%] Routing Phase 1 completed
[80%] Routing Phase 2 completed
[90%] Routing Phase 3 completed
Running timing analysis......
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\pnr\fpga_project.power.html" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\pnr\fpga_project.pin.html" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\pnr\fpga_project.rpt.html" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\pnr\fpga_project.rpt.txt" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\pnr\fpga_project.tr.html" completed
Fri Jul 5 01:48:07 2024
Reading netlist file: "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project.vg"
Parsing netlist file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\gwsynthesis\fpga_project.vg" completed
Processing netlist completed
Reading constraint file: "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\src\fpga_project.cst"
Physical Constraint parsed completed
Running placement......
[10%] Placement Phase 0 completed
[20%] Placement Phase 1 completed
[30%] Placement Phase 2 completed
[50%] Placement Phase 3 completed
Running routing......
[60%] Routing Phase 0 completed
[70%] Routing Phase 1 completed
[80%] Routing Phase 2 completed
[90%] Routing Phase 3 completed
Running timing analysis......
[95%] Timing analysis completed
Placement and routing completed
Bitstream generation in progress......
Bitstream generation completed
Running power analysis......
[100%] Power analysis completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\pnr\fpga_project.power.html" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\pnr\fpga_project.pin.html" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\pnr\fpga_project.rpt.html" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\pnr\fpga_project.rpt.txt" completed
Generate file "\\wsl.localhost\Debian\home\koray\code\verilog\gowin\fpga_project\impl\pnr\fpga_project.tr.html" completed
Fri Jul 5 01:48:07 2024