rearrangement
This commit is contained in:
24
iverilog/tobb/labs/lab2/impl/gwsynthesis/lab2.log
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24
iverilog/tobb/labs/lab2/impl/gwsynthesis/lab2.log
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@ -0,0 +1,24 @@
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||||
GowinSynthesis start
|
||||
Running parser ...
|
||||
Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab2\src\BitM.v'
|
||||
Compiling module 'BitM'("C:\cygwin64\home\koray\verilog\lab2\src\BitM.v":1)
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NOTE (EX0101) : Current top module is "BitM"
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||||
[5%] Running netlist conversion ...
|
||||
Running device independent optimization ...
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||||
[10%] Optimizing Phase 0 completed
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||||
[15%] Optimizing Phase 1 completed
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||||
[25%] Optimizing Phase 2 completed
|
||||
Running inference ...
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||||
[30%] Inferring Phase 0 completed
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[40%] Inferring Phase 1 completed
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[50%] Inferring Phase 2 completed
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||||
[55%] Inferring Phase 3 completed
|
||||
Running technical mapping ...
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||||
[60%] Tech-Mapping Phase 0 completed
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[65%] Tech-Mapping Phase 1 completed
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[75%] Tech-Mapping Phase 2 completed
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[80%] Tech-Mapping Phase 3 completed
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||||
[90%] Tech-Mapping Phase 4 completed
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||||
[95%] Generate netlist file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2.vg" completed
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||||
[100%] Generate report file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2_syn.rpt.html" completed
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||||
GowinSynthesis finish
|
19
iverilog/tobb/labs/lab2/impl/gwsynthesis/lab2.prj
Normal file
19
iverilog/tobb/labs/lab2/impl/gwsynthesis/lab2.prj
Normal file
@ -0,0 +1,19 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE gowin-synthesis-project>
|
||||
<Project>
|
||||
<Version>beta</Version>
|
||||
<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
|
||||
<FileList>
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||||
<File path="C:\cygwin64\home\koray\verilog\lab2\src\BitM.v" type="verilog"/>
|
||||
</FileList>
|
||||
<OptionList>
|
||||
<Option type="disable_insert_pad" value="0"/>
|
||||
<Option type="global_freq" value="100.000"/>
|
||||
<Option type="looplimit" value="2000"/>
|
||||
<Option type="output_file" value="C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2.vg"/>
|
||||
<Option type="print_all_synthesis_warning" value="0"/>
|
||||
<Option type="ram_rw_check" value="0"/>
|
||||
<Option type="verilog_language" value="verilog-2001"/>
|
||||
<Option type="vhdl_language" value="vhdl-1993"/>
|
||||
</OptionList>
|
||||
</Project>
|
76
iverilog/tobb/labs/lab2/impl/gwsynthesis/lab2.vg
Normal file
76
iverilog/tobb/labs/lab2/impl/gwsynthesis/lab2.vg
Normal file
@ -0,0 +1,76 @@
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||||
//
|
||||
//Written by GowinSynthesis
|
||||
//Tool Version "V1.9.9.02"
|
||||
//Thu Apr 11 07:46:56 2024
|
||||
|
||||
//Source file index table:
|
||||
//file0 "\C:/cygwin64/home/koray/verilog/lab2/src/BitM.v"
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`timescale 100 ps/100 ps
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module BitM (
|
||||
A,
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||||
B,
|
||||
AlB,
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||||
AeB,
|
||||
AgB
|
||||
)
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;
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||||
input A;
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||||
input B;
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||||
output AlB;
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||||
output AeB;
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output AgB;
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wire A_d;
|
||||
wire B_d;
|
||||
wire AlB_d;
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wire AgB_d;
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wire AeB_d;
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wire VCC;
|
||||
wire GND;
|
||||
IBUF A_ibuf (
|
||||
.O(A_d),
|
||||
.I(A)
|
||||
);
|
||||
IBUF B_ibuf (
|
||||
.O(B_d),
|
||||
.I(B)
|
||||
);
|
||||
OBUF AlB_obuf (
|
||||
.O(AlB),
|
||||
.I(AlB_d)
|
||||
);
|
||||
OBUF AeB_obuf (
|
||||
.O(AeB),
|
||||
.I(AeB_d)
|
||||
);
|
||||
OBUF AgB_obuf (
|
||||
.O(AgB),
|
||||
.I(AgB_d)
|
||||
);
|
||||
LUT2 AlB_d_s (
|
||||
.F(AlB_d),
|
||||
.I0(A_d),
|
||||
.I1(B_d)
|
||||
);
|
||||
defparam AlB_d_s.INIT=4'h4;
|
||||
LUT2 AgB_d_s (
|
||||
.F(AgB_d),
|
||||
.I0(B_d),
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||||
.I1(A_d)
|
||||
);
|
||||
defparam AgB_d_s.INIT=4'h4;
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||||
LUT2 AeB_d_s (
|
||||
.F(AeB_d),
|
||||
.I0(A_d),
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||||
.I1(B_d)
|
||||
);
|
||||
defparam AeB_d_s.INIT=4'h9;
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||||
VCC VCC_cZ (
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||||
.V(VCC)
|
||||
);
|
||||
GND GND_cZ (
|
||||
.G(GND)
|
||||
);
|
||||
GSR GSR (
|
||||
.GSRI(VCC)
|
||||
);
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endmodule /* BitM */
|
167
iverilog/tobb/labs/lab2/impl/gwsynthesis/lab2_syn.rpt.html
Normal file
167
iverilog/tobb/labs/lab2/impl/gwsynthesis/lab2_syn.rpt.html
Normal file
@ -0,0 +1,167 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>synthesis Report</title>
|
||||
<style type="text/css">
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
|
||||
div#main_wrapper{ width: 100%; }
|
||||
div#content { margin-left: 350px; margin-right: 30px; }
|
||||
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
|
||||
div#catalog ul { list-style-type: none; }
|
||||
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
|
||||
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
|
||||
div#catalog a:visited { color: #0084ff; }
|
||||
div#catalog a:hover { color: #fff; background: #0084ff; }
|
||||
hr { margin-top: 30px; margin-bottom: 30px; }
|
||||
h1, h3 { text-align: center; }
|
||||
h1 {margin-top: 50px; }
|
||||
table, th, td { border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { padding: 5px 5px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
|
||||
table.detail_table td.label { min-width: 100px; width: 8%;}
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="main_wrapper">
|
||||
<div id="catalog_wrapper">
|
||||
<div id="catalog">
|
||||
<ul>
|
||||
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
|
||||
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
|
||||
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
|
||||
<ul>
|
||||
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
|
||||
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
|
||||
</ul>
|
||||
</li>
|
||||
</ul>
|
||||
</div><!-- catalog -->
|
||||
</div><!-- catalog_wrapper -->
|
||||
<div id="content">
|
||||
<h1><a name="about">Synthesis Messages</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Report Title</td>
|
||||
<td>GowinSynthesis Report</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Design File</td>
|
||||
<td>C:\cygwin64\home\koray\verilog\lab2\src\BitM.v<br>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">GowinSynthesis Constraints File</td>
|
||||
<td>---</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Tool Version</td>
|
||||
<td>V1.9.9.02</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Part Number</td>
|
||||
<td>GW2A-LV18PG256C8/I7</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device</td>
|
||||
<td>GW2A-18</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device Version</td>
|
||||
<td>C</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Created Time</td>
|
||||
<td>Thu Apr 11 07:46:56 2024
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Legal Announcement</td>
|
||||
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="summary">Synthesis Details</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Top Level Module</td>
|
||||
<td>BitM</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Synthesis Process</td>
|
||||
<td>Running parser:<br/> CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.088s, Peak memory usage = 181.887MB<br/>Running netlist conversion:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/> Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/>Running inference:<br/> Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/>Running technical mapping:<br/> Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Tech-Mapping Phase 3: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.132s, Peak memory usage = 181.887MB<br/> Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/>Generate output files:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 181.887MB<br/></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Total Time and Memory Usage</td>
|
||||
<td>CPU time = 0h 0m 0.108s, Elapsed time = 0h 0m 0.221s, Peak memory usage = 181.887MB</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="resource">Resource</a></h1>
|
||||
<h2><a name="usage">Resource Usage Summary</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label"><b>Resource</b></td>
|
||||
<td><b>Usage</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>I/O Port </b></td>
|
||||
<td>5</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>I/O Buf </b></td>
|
||||
<td>5</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    IBUF</td>
|
||||
<td>2</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    OBUF</td>
|
||||
<td>3</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>LUT </b></td>
|
||||
<td>3</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    LUT2</td>
|
||||
<td>3</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="utilization">Resource Utilization Summary</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label"><b>Resource</b></td>
|
||||
<td><b>Usage</b></td>
|
||||
<td><b>Utilization</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Logic</td>
|
||||
<td>3(3 LUT, 0 ALU) / 20736</td>
|
||||
<td><1%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Register</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">  --Register as Latch</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">  --Register as FF</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">BSRAM</td>
|
||||
<td>0 / 46</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
@ -0,0 +1,46 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>Hierarchy Module Resource</title>
|
||||
<style type="text/css">
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
|
||||
div#main_wrapper{ width: 100%; }
|
||||
h1 {text-align: center; }
|
||||
h1 {margin-top: 36px; }
|
||||
table, th, td { border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { align = "center"; padding: 5px 2px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="main_wrapper">
|
||||
<div id="content">
|
||||
<h1>Hierarchy Module Resource</h1>
|
||||
<table>
|
||||
<tr>
|
||||
<th class="label">MODULE NAME</th>
|
||||
<th class="label">REG NUMBER</th>
|
||||
<th class="label">ALU NUMBER</th>
|
||||
<th class="label">LUT NUMBER</th>
|
||||
<th class="label">DSP NUMBER</th>
|
||||
<th class="label">BSRAM NUMBER</th>
|
||||
<th class="label">SSRAM NUMBER</th>
|
||||
<th class="label">ROM16 NUMBER</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">BitM (C:/cygwin64/home/koray/verilog/lab2/src/BitM.v)</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">3</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
@ -0,0 +1,2 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Module name="BitM" Lut="3" T_Lut="3(3)"/>
|
88
iverilog/tobb/labs/lab2/impl/lab2_process_config.json
Normal file
88
iverilog/tobb/labs/lab2/impl/lab2_process_config.json
Normal file
@ -0,0 +1,88 @@
|
||||
{
|
||||
"BACKGROUND_PROGRAMMING" : "off",
|
||||
"COMPRESS" : false,
|
||||
"CPU" : false,
|
||||
"CRC_CHECK" : true,
|
||||
"Clock_Route_Order" : 0,
|
||||
"Correct_Hold_Violation" : true,
|
||||
"DONE" : false,
|
||||
"DOWNLOAD_SPEED" : "default",
|
||||
"Disable_Insert_Pad" : false,
|
||||
"ENABLE_CTP" : false,
|
||||
"ENABLE_MERGE_MODE" : false,
|
||||
"ENCRYPTION_KEY" : false,
|
||||
"ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
|
||||
"ERROR_DECTION_AND_CORRECTION" : false,
|
||||
"ERROR_DECTION_ONLY" : false,
|
||||
"ERROR_INJECTION" : false,
|
||||
"EXTERNAL_MASTER_CONFIG_CLOCK" : false,
|
||||
"Enable_DSRM" : false,
|
||||
"FORMAT" : "binary",
|
||||
"FREQUENCY_DIVIDER" : "",
|
||||
"Generate_Constraint_File_of_Ports" : false,
|
||||
"Generate_IBIS_File" : false,
|
||||
"Generate_Plain_Text_Timing_Report" : false,
|
||||
"Generate_Post_PNR_Simulation_Model_File" : false,
|
||||
"Generate_Post_Place_File" : false,
|
||||
"Generate_SDF_File" : false,
|
||||
"Generate_VHDL_Post_PNR_Simulation_Model_File" : false,
|
||||
"Global_Freq" : "default",
|
||||
"GwSyn_Loop_Limit" : 2000,
|
||||
"HOTBOOT" : false,
|
||||
"I2C" : false,
|
||||
"I2C_SLAVE_ADDR" : "00",
|
||||
"IncludePath" : [
|
||||
|
||||
],
|
||||
"Incremental_Compile" : "",
|
||||
"Initialize_Primitives" : false,
|
||||
"JTAG" : false,
|
||||
"MODE_IO" : false,
|
||||
"MSPI" : false,
|
||||
"MSPI_JUMP" : false,
|
||||
"MULTIBOOT_ADDRESS_WIDTH" : "24",
|
||||
"MULTIBOOT_MODE" : "Normal",
|
||||
"MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000",
|
||||
"MULTIJUMP_ADDRESS_WIDTH" : "24",
|
||||
"MULTIJUMP_MODE" : "Normal",
|
||||
"MULTIJUMP_SPI_FLASH_ADDRESS" : "000000",
|
||||
"Multi_Boot" : true,
|
||||
"OUTPUT_BASE_NAME" : "lab2",
|
||||
"POWER_ON_RESET_MONITOR" : true,
|
||||
"PRINT_BSRAM_VALUE" : true,
|
||||
"PROGRAM_DONE_BYPASS" : false,
|
||||
"PlaceInRegToIob" : true,
|
||||
"PlaceIoRegToIob" : true,
|
||||
"PlaceOutRegToIob" : true,
|
||||
"Place_Option" : "0",
|
||||
"Process_Configuration_Verion" : "1.0",
|
||||
"Promote_Physical_Constraint_Warning_to_Error" : true,
|
||||
"READY" : false,
|
||||
"RECONFIG_N" : false,
|
||||
"Ram_RW_Check" : false,
|
||||
"Replicate_Resources" : false,
|
||||
"Report_Auto-Placed_Io_Information" : false,
|
||||
"Route_Maxfan" : 23,
|
||||
"Route_Option" : "0",
|
||||
"Run_Timing_Driven" : true,
|
||||
"SECURE_MODE" : false,
|
||||
"SECURITY_BIT" : true,
|
||||
"SEU_HANDLER" : false,
|
||||
"SEU_HANDLER_CHECKSUM" : false,
|
||||
"SEU_HANDLER_MODE" : "auto",
|
||||
"SSPI" : false,
|
||||
"STOP_SEU_HANDLER" : false,
|
||||
"Show_All_Warnings" : false,
|
||||
"Synthesize_tool" : "GowinSyn",
|
||||
"TclPre" : "",
|
||||
"TopModule" : "",
|
||||
"USERCODE" : "default",
|
||||
"Unused_Pin" : "As_input_tri_stated_with_pull_up",
|
||||
"VCCAUX" : 3.3,
|
||||
"VCCX" : "3.3",
|
||||
"VHDL_Standard" : "VHDL_Std_1993",
|
||||
"Verilog_Standard" : "Vlg_Std_2001",
|
||||
"WAKE_UP" : "0",
|
||||
"show_all_warnings" : false,
|
||||
"turn_off_bg" : false
|
||||
}
|
36
iverilog/tobb/labs/lab2/impl/temp/rtl_parser.result
Normal file
36
iverilog/tobb/labs/lab2/impl/temp/rtl_parser.result
Normal file
@ -0,0 +1,36 @@
|
||||
[
|
||||
{
|
||||
"InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/BitM.v",
|
||||
"InstLine" : 1,
|
||||
"InstName" : "BitM",
|
||||
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/BitM.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "BitM"
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/fullAdder.v",
|
||||
"InstLine" : 1,
|
||||
"InstName" : "fullAdder",
|
||||
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/fullAdder.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "fullAdder"
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
|
||||
"InstLine" : 1,
|
||||
"InstName" : "tb",
|
||||
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "tb",
|
||||
"SubInsts" : [
|
||||
{
|
||||
"InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
|
||||
"InstLine" : 6,
|
||||
"InstName" : "uut",
|
||||
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/halfAdder.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "halfAdder"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
29
iverilog/tobb/labs/lab2/impl/temp/rtl_parser_arg.json
Normal file
29
iverilog/tobb/labs/lab2/impl/temp/rtl_parser_arg.json
Normal file
@ -0,0 +1,29 @@
|
||||
{
|
||||
"Device" : "GW2A-18C",
|
||||
"Files" : [
|
||||
{
|
||||
"Path" : "C:/cygwin64/home/koray/verilog/lab2/src/BitM.v",
|
||||
"Type" : "verilog"
|
||||
},
|
||||
{
|
||||
"Path" : "C:/cygwin64/home/koray/verilog/lab2/src/fullAdder.v",
|
||||
"Type" : "verilog"
|
||||
},
|
||||
{
|
||||
"Path" : "C:/cygwin64/home/koray/verilog/lab2/src/halfAdder.v",
|
||||
"Type" : "verilog"
|
||||
},
|
||||
{
|
||||
"Path" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
|
||||
"Type" : "verilog"
|
||||
}
|
||||
],
|
||||
"IncludePath" : [
|
||||
|
||||
],
|
||||
"LoopLimit" : 2000,
|
||||
"ResultFile" : "C:/cygwin64/home/koray/verilog/lab2/impl/temp/rtl_parser.result",
|
||||
"Top" : "",
|
||||
"VerilogStd" : "verilog_2001",
|
||||
"VhdlStd" : "vhdl_93"
|
||||
}
|
13
iverilog/tobb/labs/lab2/lab2.gprj
Normal file
13
iverilog/tobb/labs/lab2/lab2.gprj
Normal file
@ -0,0 +1,13 @@
|
||||
<?xml version="1" encoding="UTF-8"?>
|
||||
<!DOCTYPE gowin-fpga-project>
|
||||
<Project>
|
||||
<Template>FPGA</Template>
|
||||
<Version>5</Version>
|
||||
<Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device>
|
||||
<FileList>
|
||||
<File path="src/BitM.v" type="file.verilog" enable="1"/>
|
||||
<File path="src/fullAdder.v" type="file.verilog" enable="1"/>
|
||||
<File path="src/halfAdder.v" type="file.verilog" enable="1"/>
|
||||
<File path="src/tb.v" type="file.verilog" enable="1"/>
|
||||
</FileList>
|
||||
</Project>
|
17
iverilog/tobb/labs/lab2/lab2.gprj.user
Normal file
17
iverilog/tobb/labs/lab2/lab2.gprj.user
Normal file
@ -0,0 +1,17 @@
|
||||
<?xml version="1" encoding="UTF-8"?>
|
||||
<!DOCTYPE ProjectUserData>
|
||||
<UserConfig>
|
||||
<Version>1.0</Version>
|
||||
<FlowState>
|
||||
<Process ID="Synthesis" State="4"/>
|
||||
<Process ID="Pnr" State="0"/>
|
||||
<Process ID="Gao" State="0"/>
|
||||
<Process ID="Rtl_Gao" State="2"/>
|
||||
</FlowState>
|
||||
<ResultFileList>
|
||||
<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/lab2.vg"/>
|
||||
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/lab2_syn.rpt.html"/>
|
||||
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/lab2_syn_rsc.xml"/>
|
||||
</ResultFileList>
|
||||
<Ui>000000ff00000001fd00000002000000000000010000000130fc0200000001fc00000063000001300000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000000000030000050000000121fc0100000001fc00000000000005000000009b00fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000005100fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff0000009b00ffffff000003f80000013000000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e0045006400690074010000009bffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000157ffffffff0000000000000000</Ui>
|
||||
</UserConfig>
|
19
iverilog/tobb/labs/lab2/src/BitM.v
Normal file
19
iverilog/tobb/labs/lab2/src/BitM.v
Normal file
@ -0,0 +1,19 @@
|
||||
module BitM(
|
||||
input A,
|
||||
input B,
|
||||
output AlB,
|
||||
output AeB,
|
||||
output AgB
|
||||
);
|
||||
|
||||
wire An, Bn;
|
||||
|
||||
not n1 (An, A);
|
||||
not n2 (Bn, B);
|
||||
|
||||
and a1 (AlB, An, B);
|
||||
and a2 (AgB, Bn, A);
|
||||
|
||||
nor nor1 (AeB, AlB, AgB);
|
||||
|
||||
endmodule
|
26
iverilog/tobb/labs/lab2/src/BitM_tb.v
Normal file
26
iverilog/tobb/labs/lab2/src/BitM_tb.v
Normal file
@ -0,0 +1,26 @@
|
||||
module BitM_tb();
|
||||
|
||||
reg r1, r2;
|
||||
wire w1, w2, w3;
|
||||
|
||||
BitM uut(
|
||||
.A(r1),
|
||||
.B(r2),
|
||||
.AlB(w1),
|
||||
.AeB(w2),
|
||||
.AgB(w3)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("bdmp.vcd");
|
||||
$dumpvars;
|
||||
r1 = 0; r2 = 0; #10
|
||||
r1 = 0; r2 = 1; #10
|
||||
r1 = 1; r2 = 0; #10
|
||||
r1 = 1; r2 = 1; #10
|
||||
$display(w1);
|
||||
$display(w2);
|
||||
$display(w3);
|
||||
end
|
||||
|
||||
endmodule
|
58
iverilog/tobb/labs/lab2/src/bdmp.vcd
Normal file
58
iverilog/tobb/labs/lab2/src/bdmp.vcd
Normal file
@ -0,0 +1,58 @@
|
||||
$date
|
||||
Thu Apr 11 07:50:26 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module BitM_tb $end
|
||||
$var wire 1 ! w3 $end
|
||||
$var wire 1 " w2 $end
|
||||
$var wire 1 # w1 $end
|
||||
$var reg 1 $ r1 $end
|
||||
$var reg 1 % r2 $end
|
||||
$scope module uut $end
|
||||
$var wire 1 $ A $end
|
||||
$var wire 1 " AeB $end
|
||||
$var wire 1 ! AgB $end
|
||||
$var wire 1 # AlB $end
|
||||
$var wire 1 & An $end
|
||||
$var wire 1 % B $end
|
||||
$var wire 1 ' Bn $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$comment Show the parameter values. $end
|
||||
$dumpall
|
||||
$end
|
||||
#0
|
||||
$dumpvars
|
||||
1'
|
||||
1&
|
||||
0%
|
||||
0$
|
||||
0#
|
||||
1"
|
||||
0!
|
||||
$end
|
||||
#10
|
||||
0"
|
||||
0'
|
||||
1#
|
||||
1%
|
||||
#20
|
||||
1!
|
||||
0"
|
||||
1'
|
||||
0#
|
||||
0&
|
||||
0%
|
||||
1$
|
||||
#30
|
||||
1"
|
||||
0!
|
||||
0'
|
||||
1%
|
||||
#40
|
70
iverilog/tobb/labs/lab2/src/blab2
Normal file
70
iverilog/tobb/labs/lab2/src/blab2
Normal file
@ -0,0 +1,70 @@
|
||||
#! /c/Source/iverilog-install/bin/vvp
|
||||
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
|
||||
S_000002114102cad0 .scope module, "BitM_tb" "BitM_tb" 2 1;
|
||||
.timescale 0 0;
|
||||
v0000021140f146e0_0 .var "r1", 0 0;
|
||||
v0000021140f14780_0 .var "r2", 0 0;
|
||||
v0000021140f14820_0 .net "w1", 0 0, L_0000021140ee32f0; 1 drivers
|
||||
v0000021140f148c0_0 .net "w2", 0 0, L_0000021140f14f60; 1 drivers
|
||||
v0000021140f14960_0 .net "w3", 0 0, L_0000021140f14de0; 1 drivers
|
||||
S_000002114102cc60 .scope module, "uut" "BitM" 2 6, 3 1 0, S_000002114102cad0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "AlB";
|
||||
.port_info 3 /OUTPUT 1 "AeB";
|
||||
.port_info 4 /OUTPUT 1 "AgB";
|
||||
L_000002114102af60 .functor NOT 1, v0000021140f146e0_0, C4<0>, C4<0>, C4<0>;
|
||||
L_0000021140ee3190 .functor NOT 1, v0000021140f14780_0, C4<0>, C4<0>, C4<0>;
|
||||
L_0000021140ee32f0 .functor AND 1, L_000002114102af60, v0000021140f14780_0, C4<1>, C4<1>;
|
||||
L_0000021140f14de0 .functor AND 1, L_0000021140ee3190, v0000021140f146e0_0, C4<1>, C4<1>;
|
||||
L_0000021140f14f60 .functor NOR 1, L_0000021140ee32f0, L_0000021140f14de0, C4<0>, C4<0>;
|
||||
v0000021141028fc0_0 .net "A", 0 0, v0000021140f146e0_0; 1 drivers
|
||||
v0000021140ee2ee0_0 .net "AeB", 0 0, L_0000021140f14f60; alias, 1 drivers
|
||||
v000002114102aec0_0 .net "AgB", 0 0, L_0000021140f14de0; alias, 1 drivers
|
||||
v000002114102cdf0_0 .net "AlB", 0 0, L_0000021140ee32f0; alias, 1 drivers
|
||||
v000002114102ce90_0 .net "An", 0 0, L_000002114102af60; 1 drivers
|
||||
v0000021140f145a0_0 .net "B", 0 0, v0000021140f14780_0; 1 drivers
|
||||
v0000021140f14640_0 .net "Bn", 0 0, L_0000021140ee3190; 1 drivers
|
||||
.scope S_000002114102cad0;
|
||||
T_0 ;
|
||||
%vpi_call 2 15 "$dumpfile", "bdmp.vcd" {0 0 0};
|
||||
%vpi_call 2 16 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0000021140f146e0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0000021140f14780_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0000021140f146e0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0000021140f14780_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0000021140f146e0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0000021140f14780_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0000021140f146e0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0000021140f14780_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%vpi_call 2 21 "$display", v0000021140f14820_0 {0 0 0};
|
||||
%vpi_call 2 22 "$display", v0000021140f148c0_0 {0 0 0};
|
||||
%vpi_call 2 23 "$display", v0000021140f14960_0 {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"BitM_tb.v";
|
||||
"BitM.v";
|
43
iverilog/tobb/labs/lab2/src/dmp.vcd
Normal file
43
iverilog/tobb/labs/lab2/src/dmp.vcd
Normal file
@ -0,0 +1,43 @@
|
||||
$date
|
||||
Thu Apr 11 06:36:34 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module tb $end
|
||||
$var wire 1 ! w2 $end
|
||||
$var wire 1 " w1 $end
|
||||
$var reg 1 # r1 $end
|
||||
$var reg 1 $ r2 $end
|
||||
$scope module uut $end
|
||||
$var wire 1 # A $end
|
||||
$var wire 1 $ B $end
|
||||
$var wire 1 ! C $end
|
||||
$var wire 1 " S $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$comment Show the parameter values. $end
|
||||
$dumpall
|
||||
$end
|
||||
#0
|
||||
$dumpvars
|
||||
0$
|
||||
0#
|
||||
0"
|
||||
0!
|
||||
$end
|
||||
#20
|
||||
1"
|
||||
1#
|
||||
#40
|
||||
1$
|
||||
0#
|
||||
#60
|
||||
0"
|
||||
1!
|
||||
1#
|
||||
#80
|
75
iverilog/tobb/labs/lab2/src/fdmp.vcd
Normal file
75
iverilog/tobb/labs/lab2/src/fdmp.vcd
Normal file
@ -0,0 +1,75 @@
|
||||
$date
|
||||
Thu Apr 11 07:39:27 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module ftb $end
|
||||
$var wire 1 ! w2 $end
|
||||
$var wire 1 " w1 $end
|
||||
$var reg 1 # r1 $end
|
||||
$var reg 1 $ r2 $end
|
||||
$var reg 1 % r3 $end
|
||||
$scope module uut $end
|
||||
$var wire 1 # A $end
|
||||
$var wire 1 & AB $end
|
||||
$var wire 1 ' ABCin $end
|
||||
$var wire 1 ( AaB $end
|
||||
$var wire 1 $ B $end
|
||||
$var wire 1 % Cin $end
|
||||
$var wire 1 ! Cout $end
|
||||
$var wire 1 " S $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$comment Show the parameter values. $end
|
||||
$dumpall
|
||||
$end
|
||||
#0
|
||||
$dumpvars
|
||||
0(
|
||||
0'
|
||||
0&
|
||||
0%
|
||||
0$
|
||||
0#
|
||||
0"
|
||||
0!
|
||||
$end
|
||||
#10
|
||||
1"
|
||||
1%
|
||||
#20
|
||||
1&
|
||||
0%
|
||||
1$
|
||||
#30
|
||||
1!
|
||||
0"
|
||||
1'
|
||||
1%
|
||||
#40
|
||||
0!
|
||||
1"
|
||||
0'
|
||||
0%
|
||||
0$
|
||||
1#
|
||||
#50
|
||||
1!
|
||||
0"
|
||||
1'
|
||||
1%
|
||||
#60
|
||||
0'
|
||||
0&
|
||||
1(
|
||||
0%
|
||||
1$
|
||||
#70
|
||||
1"
|
||||
1%
|
||||
#80
|
106
iverilog/tobb/labs/lab2/src/flab2
Normal file
106
iverilog/tobb/labs/lab2/src/flab2
Normal file
@ -0,0 +1,106 @@
|
||||
#! /c/Source/iverilog-install/bin/vvp
|
||||
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
|
||||
S_000001da0354ad70 .scope module, "ftb" "ftb" 2 1;
|
||||
.timescale 0 0;
|
||||
v000001da035dc840_0 .var "r1", 0 0;
|
||||
v000001da035dc8e0_0 .var "r2", 0 0;
|
||||
v000001da035dc980_0 .var "r3", 0 0;
|
||||
v000001da035dca20_0 .net "w1", 0 0, L_000001da03594080; 1 drivers
|
||||
v000001da035935f0_0 .net "w2", 0 0, L_000001da03594470; 1 drivers
|
||||
S_000001da0354e9e0 .scope module, "uut" "fullAdder" 2 6, 3 1 0, S_000001da0354ad70;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "Cin";
|
||||
.port_info 3 /OUTPUT 1 "S";
|
||||
.port_info 4 /OUTPUT 1 "Cout";
|
||||
L_000001da03594010 .functor XOR 1, v000001da035dc840_0, v000001da035dc8e0_0, C4<0>, C4<0>;
|
||||
L_000001da03594080 .functor XOR 1, L_000001da03594010, v000001da035dc980_0, C4<0>, C4<0>;
|
||||
L_000001da03593e50 .functor AND 1, L_000001da03594010, v000001da035dc980_0, C4<1>, C4<1>;
|
||||
L_000001da035940f0 .functor AND 1, v000001da035dc840_0, v000001da035dc8e0_0, C4<1>, C4<1>;
|
||||
L_000001da03594470 .functor OR 1, L_000001da03593e50, L_000001da035940f0, C4<0>, C4<0>;
|
||||
v000001da03563310_0 .net "A", 0 0, v000001da035dc840_0; 1 drivers
|
||||
v000001da03562ee0_0 .net "AB", 0 0, L_000001da03594010; 1 drivers
|
||||
v000001da0354af00_0 .net "ABCin", 0 0, L_000001da03593e50; 1 drivers
|
||||
v000001da03549850_0 .net "AaB", 0 0, L_000001da035940f0; 1 drivers
|
||||
v000001da0354eb70_0 .net "B", 0 0, v000001da035dc8e0_0; 1 drivers
|
||||
v000001da0354ec10_0 .net "Cin", 0 0, v000001da035dc980_0; 1 drivers
|
||||
v000001da0354ecb0_0 .net "Cout", 0 0, L_000001da03594470; alias, 1 drivers
|
||||
v000001da0354ed50_0 .net "S", 0 0, L_000001da03594080; alias, 1 drivers
|
||||
.scope S_000001da0354ad70;
|
||||
T_0 ;
|
||||
%vpi_call 2 15 "$dumpfile", "fdmp.vcd" {0 0 0};
|
||||
%vpi_call 2 16 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc840_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc8e0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc980_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc840_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc8e0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc980_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc840_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc8e0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc980_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc840_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc8e0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc980_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc840_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc8e0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc980_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc840_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc8e0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc980_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc840_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc8e0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc980_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc840_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc8e0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc980_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%vpi_call 2 25 "$display", v000001da035dca20_0 {0 0 0};
|
||||
%vpi_call 2 26 "$display", v000001da035935f0_0 {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"ftb.v";
|
||||
"fullAdder.v";
|
29
iverilog/tobb/labs/lab2/src/ftb.v
Normal file
29
iverilog/tobb/labs/lab2/src/ftb.v
Normal file
@ -0,0 +1,29 @@
|
||||
module ftb ();
|
||||
|
||||
reg r1, r2, r3;
|
||||
wire w1, w2;
|
||||
|
||||
fullAdder uut(
|
||||
.A(r1),
|
||||
.B(r2),
|
||||
.Cin(r3),
|
||||
.S(w1),
|
||||
.Cout(w2)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("fdmp.vcd");
|
||||
$dumpvars;
|
||||
r1 = 0; r2 = 0; r3 = 0; #10
|
||||
r1 = 0; r2 = 0; r3 = 1; #10
|
||||
r1 = 0; r2 = 1; r3 = 0; #10
|
||||
r1 = 0; r2 = 1; r3 = 1; #10
|
||||
r1 = 1; r2 = 0; r3 = 0; #10
|
||||
r1 = 1; r2 = 0; r3 = 1; #10
|
||||
r1 = 1; r2 = 1; r3 = 0; #10
|
||||
r1 = 1; r2 = 1; r3 = 1; #10
|
||||
$display(w1);
|
||||
$display(w2);
|
||||
end
|
||||
|
||||
endmodule
|
20
iverilog/tobb/labs/lab2/src/fullAdder.v
Normal file
20
iverilog/tobb/labs/lab2/src/fullAdder.v
Normal file
@ -0,0 +1,20 @@
|
||||
module fullAdder(
|
||||
input A,
|
||||
input B,
|
||||
input Cin,
|
||||
output S,
|
||||
output Cout
|
||||
);
|
||||
|
||||
wire AB;
|
||||
wire ABCin, AaB;
|
||||
|
||||
xor (AB, A, B);
|
||||
xor (S, AB, Cin);
|
||||
|
||||
and (ABCin, AB, Cin);
|
||||
and (AaB, A, B);
|
||||
|
||||
or (Cout, ABCin, AaB);
|
||||
|
||||
endmodule
|
11
iverilog/tobb/labs/lab2/src/halfAdder.v
Normal file
11
iverilog/tobb/labs/lab2/src/halfAdder.v
Normal file
@ -0,0 +1,11 @@
|
||||
module halfAdder(
|
||||
input A,
|
||||
input B,
|
||||
output S,
|
||||
output C
|
||||
);
|
||||
|
||||
xor (S, A, B);
|
||||
and (C, A, B);
|
||||
|
||||
endmodule
|
61
iverilog/tobb/labs/lab2/src/lab2
Normal file
61
iverilog/tobb/labs/lab2/src/lab2
Normal file
@ -0,0 +1,61 @@
|
||||
#! /c/Source/iverilog-install/bin/vvp
|
||||
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
|
||||
S_000001b4458eec80 .scope module, "tb" "tb" 2 1;
|
||||
.timescale 0 0;
|
||||
v000001b4458ec1d0_0 .var "r1", 0 0;
|
||||
v000001b4458ec270_0 .var "r2", 0 0;
|
||||
v000001b4458ec310_0 .net "w1", 0 0, L_000001b445783190; 1 drivers
|
||||
v000001b4458ec3b0_0 .net "w2", 0 0, L_000001b4457832f0; 1 drivers
|
||||
S_000001b4458eee10 .scope module, "uut" "halfAdder" 2 6, 3 1 0, S_000001b4458eec80;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "S";
|
||||
.port_info 3 /OUTPUT 1 "C";
|
||||
L_000001b445783190 .functor XOR 1, v000001b4458ec1d0_0, v000001b4458ec270_0, C4<0>, C4<0>;
|
||||
L_000001b4457832f0 .functor AND 1, v000001b4458ec1d0_0, v000001b4458ec270_0, C4<1>, C4<1>;
|
||||
v000001b4458ebff0_0 .net "A", 0 0, v000001b4458ec1d0_0; 1 drivers
|
||||
v000001b445782ee0_0 .net "B", 0 0, v000001b4458ec270_0; 1 drivers
|
||||
v000001b4458ec090_0 .net "C", 0 0, L_000001b4457832f0; alias, 1 drivers
|
||||
v000001b4458ec130_0 .net "S", 0 0, L_000001b445783190; alias, 1 drivers
|
||||
.scope S_000001b4458eec80;
|
||||
T_0 ;
|
||||
%vpi_call 2 14 "$dumpfile", "dmp.vcd" {0 0 0};
|
||||
%vpi_call 2 15 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001b4458ec1d0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001b4458ec270_0, 0, 1;
|
||||
%delay 20, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001b4458ec1d0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001b4458ec270_0, 0, 1;
|
||||
%delay 20, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001b4458ec1d0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001b4458ec270_0, 0, 1;
|
||||
%delay 20, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001b4458ec1d0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001b4458ec270_0, 0, 1;
|
||||
%delay 20, 0;
|
||||
%vpi_call 2 20 "$display", v000001b4458ec310_0 {0 0 0};
|
||||
%vpi_call 2 21 "$display", v000001b4458ec3b0_0 {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"tb.v";
|
||||
"halfAdder.v";
|
24
iverilog/tobb/labs/lab2/src/tb.v
Normal file
24
iverilog/tobb/labs/lab2/src/tb.v
Normal file
@ -0,0 +1,24 @@
|
||||
module tb();
|
||||
|
||||
reg r1, r2;
|
||||
wire w1, w2;
|
||||
|
||||
halfAdder uut(
|
||||
.A(r1),
|
||||
.B(r2),
|
||||
.S(w1),
|
||||
.C(w2)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("dmp.vcd");
|
||||
$dumpvars;
|
||||
r1 = 0; r2 = 0; #20
|
||||
r1 = 1; r2 = 0; #20
|
||||
r1 = 0; r2 = 1; #20
|
||||
r1 = 1; r2 = 1; #20
|
||||
$display(w1);
|
||||
$display(w2);
|
||||
end
|
||||
|
||||
endmodule
|
40
iverilog/tobb/labs/lab2_prep/impl/gwsynthesis/lab2.log
Normal file
40
iverilog/tobb/labs/lab2_prep/impl/gwsynthesis/lab2.log
Normal file
@ -0,0 +1,40 @@
|
||||
GowinSynthesis start
|
||||
Running parser ...
|
||||
Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab2\src\lab2.v'
|
||||
Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab2\src\tb.v'
|
||||
Compiling module 'tb'("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":1)
|
||||
WARN (EX3858) : System task 'dumpfile' is ignored for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":17)
|
||||
WARN (EX3858) : System task 'dumpvars' is ignored for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":18)
|
||||
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":19)
|
||||
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":20)
|
||||
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":21)
|
||||
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":22)
|
||||
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":23)
|
||||
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":24)
|
||||
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":25)
|
||||
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":26)
|
||||
WARN (EX3858) : System task 'display' is ignored for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":27)
|
||||
WARN (EX3780) : Using initial value of 'r1' since it is never assigned("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":28)
|
||||
Compiling module 'lab2'("C:\cygwin64\home\koray\verilog\lab2\src\lab2.v":1)
|
||||
NOTE (EX0101) : Current top module is "tb"
|
||||
WARN (EX0203) : Top module "tb" has no ports("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":1)
|
||||
[5%] Running netlist conversion ...
|
||||
Running device independent optimization ...
|
||||
[10%] Optimizing Phase 0 completed
|
||||
[15%] Optimizing Phase 1 completed
|
||||
[25%] Optimizing Phase 2 completed
|
||||
Running inference ...
|
||||
[30%] Inferring Phase 0 completed
|
||||
[40%] Inferring Phase 1 completed
|
||||
[50%] Inferring Phase 2 completed
|
||||
[55%] Inferring Phase 3 completed
|
||||
Running technical mapping ...
|
||||
[60%] Tech-Mapping Phase 0 completed
|
||||
[65%] Tech-Mapping Phase 1 completed
|
||||
[75%] Tech-Mapping Phase 2 completed
|
||||
[80%] Tech-Mapping Phase 3 completed
|
||||
[90%] Tech-Mapping Phase 4 completed
|
||||
WARN (NL0002) : The module "lab2" instantiated to "uut" is swept in optimizing("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":12)
|
||||
[95%] Generate netlist file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2.vg" completed
|
||||
[100%] Generate report file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2_syn.rpt.html" completed
|
||||
GowinSynthesis finish
|
20
iverilog/tobb/labs/lab2_prep/impl/gwsynthesis/lab2.prj
Normal file
20
iverilog/tobb/labs/lab2_prep/impl/gwsynthesis/lab2.prj
Normal file
@ -0,0 +1,20 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE gowin-synthesis-project>
|
||||
<Project>
|
||||
<Version>beta</Version>
|
||||
<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
|
||||
<FileList>
|
||||
<File path="C:\cygwin64\home\koray\verilog\lab2\src\lab2.v" type="verilog"/>
|
||||
<File path="C:\cygwin64\home\koray\verilog\lab2\src\tb.v" type="verilog"/>
|
||||
</FileList>
|
||||
<OptionList>
|
||||
<Option type="disable_insert_pad" value="0"/>
|
||||
<Option type="global_freq" value="100.000"/>
|
||||
<Option type="looplimit" value="2000"/>
|
||||
<Option type="output_file" value="C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2.vg"/>
|
||||
<Option type="print_all_synthesis_warning" value="0"/>
|
||||
<Option type="ram_rw_check" value="0"/>
|
||||
<Option type="verilog_language" value="verilog-2001"/>
|
||||
<Option type="vhdl_language" value="vhdl-1993"/>
|
||||
</OptionList>
|
||||
</Project>
|
25
iverilog/tobb/labs/lab2_prep/impl/gwsynthesis/lab2.vg
Normal file
25
iverilog/tobb/labs/lab2_prep/impl/gwsynthesis/lab2.vg
Normal file
@ -0,0 +1,25 @@
|
||||
//
|
||||
//Written by GowinSynthesis
|
||||
//Tool Version "V1.9.9.02"
|
||||
//Thu Apr 11 06:15:18 2024
|
||||
|
||||
//Source file index table:
|
||||
//file0 "\C:/cygwin64/home/koray/verilog/lab2/src/lab2.v"
|
||||
//file1 "\C:/cygwin64/home/koray/verilog/lab2/src/tb.v"
|
||||
`timescale 100 ps/100 ps
|
||||
module tb (
|
||||
|
||||
)
|
||||
;
|
||||
wire VCC;
|
||||
wire GND;
|
||||
VCC VCC_cZ (
|
||||
.V(VCC)
|
||||
);
|
||||
GND GND_cZ (
|
||||
.G(GND)
|
||||
);
|
||||
GSR GSR (
|
||||
.GSRI(VCC)
|
||||
);
|
||||
endmodule /* tb */
|
144
iverilog/tobb/labs/lab2_prep/impl/gwsynthesis/lab2_syn.rpt.html
Normal file
144
iverilog/tobb/labs/lab2_prep/impl/gwsynthesis/lab2_syn.rpt.html
Normal file
@ -0,0 +1,144 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>synthesis Report</title>
|
||||
<style type="text/css">
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
|
||||
div#main_wrapper{ width: 100%; }
|
||||
div#content { margin-left: 350px; margin-right: 30px; }
|
||||
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
|
||||
div#catalog ul { list-style-type: none; }
|
||||
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
|
||||
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
|
||||
div#catalog a:visited { color: #0084ff; }
|
||||
div#catalog a:hover { color: #fff; background: #0084ff; }
|
||||
hr { margin-top: 30px; margin-bottom: 30px; }
|
||||
h1, h3 { text-align: center; }
|
||||
h1 {margin-top: 50px; }
|
||||
table, th, td { border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { padding: 5px 5px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
|
||||
table.detail_table td.label { min-width: 100px; width: 8%;}
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="main_wrapper">
|
||||
<div id="catalog_wrapper">
|
||||
<div id="catalog">
|
||||
<ul>
|
||||
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
|
||||
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
|
||||
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
|
||||
<ul>
|
||||
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
|
||||
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
|
||||
</ul>
|
||||
</li>
|
||||
</ul>
|
||||
</div><!-- catalog -->
|
||||
</div><!-- catalog_wrapper -->
|
||||
<div id="content">
|
||||
<h1><a name="about">Synthesis Messages</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Report Title</td>
|
||||
<td>GowinSynthesis Report</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Design File</td>
|
||||
<td>C:\cygwin64\home\koray\verilog\lab2\src\lab2.v<br>
|
||||
C:\cygwin64\home\koray\verilog\lab2\src\tb.v<br>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">GowinSynthesis Constraints File</td>
|
||||
<td>---</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Tool Version</td>
|
||||
<td>V1.9.9.02</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Part Number</td>
|
||||
<td>GW2A-LV18PG256C8/I7</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device</td>
|
||||
<td>GW2A-18</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device Version</td>
|
||||
<td>C</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Created Time</td>
|
||||
<td>Thu Apr 11 06:15:18 2024
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Legal Announcement</td>
|
||||
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="summary">Synthesis Details</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Top Level Module</td>
|
||||
<td>tb</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Synthesis Process</td>
|
||||
<td>Running parser:<br/> CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.148s, Peak memory usage = 184.680MB<br/>Running netlist conversion:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/> Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>Running inference:<br/> Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>Running technical mapping:<br/> Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Tech-Mapping Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 184.680MB<br/> Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>Generate output files:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 184.680MB<br/></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Total Time and Memory Usage</td>
|
||||
<td>CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.208s, Peak memory usage = 184.680MB</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="resource">Resource</a></h1>
|
||||
<h2><a name="usage">Resource Usage Summary</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label"><b>Resource</b></td>
|
||||
<td><b>Usage</b></td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="utilization">Resource Utilization Summary</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label"><b>Resource</b></td>
|
||||
<td><b>Usage</b></td>
|
||||
<td><b>Utilization</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Logic</td>
|
||||
<td>0(0 LUT, 0 ALU) / 20736</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Register</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">  --Register as Latch</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">  --Register as FF</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">BSRAM</td>
|
||||
<td>0 / 46</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
@ -0,0 +1,46 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>Hierarchy Module Resource</title>
|
||||
<style type="text/css">
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
|
||||
div#main_wrapper{ width: 100%; }
|
||||
h1 {text-align: center; }
|
||||
h1 {margin-top: 36px; }
|
||||
table, th, td { border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { align = "center"; padding: 5px 2px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="main_wrapper">
|
||||
<div id="content">
|
||||
<h1>Hierarchy Module Resource</h1>
|
||||
<table>
|
||||
<tr>
|
||||
<th class="label">MODULE NAME</th>
|
||||
<th class="label">REG NUMBER</th>
|
||||
<th class="label">ALU NUMBER</th>
|
||||
<th class="label">LUT NUMBER</th>
|
||||
<th class="label">DSP NUMBER</th>
|
||||
<th class="label">BSRAM NUMBER</th>
|
||||
<th class="label">SSRAM NUMBER</th>
|
||||
<th class="label">ROM16 NUMBER</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">tb (C:/cygwin64/home/koray/verilog/lab2/src/tb.v)</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
@ -0,0 +1,2 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Module name="tb"/>
|
88
iverilog/tobb/labs/lab2_prep/impl/lab2_process_config.json
Normal file
88
iverilog/tobb/labs/lab2_prep/impl/lab2_process_config.json
Normal file
@ -0,0 +1,88 @@
|
||||
{
|
||||
"BACKGROUND_PROGRAMMING" : "off",
|
||||
"COMPRESS" : false,
|
||||
"CPU" : false,
|
||||
"CRC_CHECK" : true,
|
||||
"Clock_Route_Order" : 0,
|
||||
"Correct_Hold_Violation" : true,
|
||||
"DONE" : false,
|
||||
"DOWNLOAD_SPEED" : "default",
|
||||
"Disable_Insert_Pad" : false,
|
||||
"ENABLE_CTP" : false,
|
||||
"ENABLE_MERGE_MODE" : false,
|
||||
"ENCRYPTION_KEY" : false,
|
||||
"ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
|
||||
"ERROR_DECTION_AND_CORRECTION" : false,
|
||||
"ERROR_DECTION_ONLY" : false,
|
||||
"ERROR_INJECTION" : false,
|
||||
"EXTERNAL_MASTER_CONFIG_CLOCK" : false,
|
||||
"Enable_DSRM" : false,
|
||||
"FORMAT" : "binary",
|
||||
"FREQUENCY_DIVIDER" : "",
|
||||
"Generate_Constraint_File_of_Ports" : false,
|
||||
"Generate_IBIS_File" : false,
|
||||
"Generate_Plain_Text_Timing_Report" : false,
|
||||
"Generate_Post_PNR_Simulation_Model_File" : false,
|
||||
"Generate_Post_Place_File" : false,
|
||||
"Generate_SDF_File" : false,
|
||||
"Generate_VHDL_Post_PNR_Simulation_Model_File" : false,
|
||||
"Global_Freq" : "default",
|
||||
"GwSyn_Loop_Limit" : 2000,
|
||||
"HOTBOOT" : false,
|
||||
"I2C" : false,
|
||||
"I2C_SLAVE_ADDR" : "00",
|
||||
"IncludePath" : [
|
||||
|
||||
],
|
||||
"Incremental_Compile" : "",
|
||||
"Initialize_Primitives" : false,
|
||||
"JTAG" : false,
|
||||
"MODE_IO" : false,
|
||||
"MSPI" : false,
|
||||
"MSPI_JUMP" : false,
|
||||
"MULTIBOOT_ADDRESS_WIDTH" : "24",
|
||||
"MULTIBOOT_MODE" : "Normal",
|
||||
"MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000",
|
||||
"MULTIJUMP_ADDRESS_WIDTH" : "24",
|
||||
"MULTIJUMP_MODE" : "Normal",
|
||||
"MULTIJUMP_SPI_FLASH_ADDRESS" : "000000",
|
||||
"Multi_Boot" : true,
|
||||
"OUTPUT_BASE_NAME" : "lab2",
|
||||
"POWER_ON_RESET_MONITOR" : true,
|
||||
"PRINT_BSRAM_VALUE" : true,
|
||||
"PROGRAM_DONE_BYPASS" : false,
|
||||
"PlaceInRegToIob" : true,
|
||||
"PlaceIoRegToIob" : true,
|
||||
"PlaceOutRegToIob" : true,
|
||||
"Place_Option" : "0",
|
||||
"Process_Configuration_Verion" : "1.0",
|
||||
"Promote_Physical_Constraint_Warning_to_Error" : true,
|
||||
"READY" : false,
|
||||
"RECONFIG_N" : false,
|
||||
"Ram_RW_Check" : false,
|
||||
"Replicate_Resources" : false,
|
||||
"Report_Auto-Placed_Io_Information" : false,
|
||||
"Route_Maxfan" : 23,
|
||||
"Route_Option" : "0",
|
||||
"Run_Timing_Driven" : true,
|
||||
"SECURE_MODE" : false,
|
||||
"SECURITY_BIT" : true,
|
||||
"SEU_HANDLER" : false,
|
||||
"SEU_HANDLER_CHECKSUM" : false,
|
||||
"SEU_HANDLER_MODE" : "auto",
|
||||
"SSPI" : false,
|
||||
"STOP_SEU_HANDLER" : false,
|
||||
"Show_All_Warnings" : false,
|
||||
"Synthesize_tool" : "GowinSyn",
|
||||
"TclPre" : "",
|
||||
"TopModule" : "",
|
||||
"USERCODE" : "default",
|
||||
"Unused_Pin" : "As_input_tri_stated_with_pull_up",
|
||||
"VCCAUX" : 3.3,
|
||||
"VCCX" : "3.3",
|
||||
"VHDL_Standard" : "VHDL_Std_1993",
|
||||
"Verilog_Standard" : "Vlg_Std_2001",
|
||||
"WAKE_UP" : "0",
|
||||
"show_all_warnings" : false,
|
||||
"turn_off_bg" : false
|
||||
}
|
20
iverilog/tobb/labs/lab2_prep/impl/temp/rtl_parser.result
Normal file
20
iverilog/tobb/labs/lab2_prep/impl/temp/rtl_parser.result
Normal file
@ -0,0 +1,20 @@
|
||||
[
|
||||
{
|
||||
"InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
|
||||
"InstLine" : 1,
|
||||
"InstName" : "tb",
|
||||
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "tb",
|
||||
"SubInsts" : [
|
||||
{
|
||||
"InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
|
||||
"InstLine" : 6,
|
||||
"InstName" : "uut",
|
||||
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/lab2.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "lab2"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
21
iverilog/tobb/labs/lab2_prep/impl/temp/rtl_parser_arg.json
Normal file
21
iverilog/tobb/labs/lab2_prep/impl/temp/rtl_parser_arg.json
Normal file
@ -0,0 +1,21 @@
|
||||
{
|
||||
"Device" : "GW2A-18C",
|
||||
"Files" : [
|
||||
{
|
||||
"Path" : "C:/cygwin64/home/koray/verilog/lab2/src/lab2.v",
|
||||
"Type" : "verilog"
|
||||
},
|
||||
{
|
||||
"Path" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
|
||||
"Type" : "verilog"
|
||||
}
|
||||
],
|
||||
"IncludePath" : [
|
||||
|
||||
],
|
||||
"LoopLimit" : 2000,
|
||||
"ResultFile" : "C:/cygwin64/home/koray/verilog/lab2/impl/temp/rtl_parser.result",
|
||||
"Top" : "",
|
||||
"VerilogStd" : "verilog_2001",
|
||||
"VhdlStd" : "vhdl_93"
|
||||
}
|
12
iverilog/tobb/labs/lab2_prep/lab2.gprj
Normal file
12
iverilog/tobb/labs/lab2_prep/lab2.gprj
Normal file
@ -0,0 +1,12 @@
|
||||
<?xml version="1" encoding="UTF-8"?>
|
||||
<!DOCTYPE gowin-fpga-project>
|
||||
<Project>
|
||||
<Template>FPGA</Template>
|
||||
<Version>5</Version>
|
||||
<Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device>
|
||||
<FileList>
|
||||
<File path="src/lab2.v" type="file.verilog" enable="1"/>
|
||||
<File path="src/tb.v" type="file.verilog" enable="1"/>
|
||||
<File path="src/labwave" type="file.other" enable="1"/>
|
||||
</FileList>
|
||||
</Project>
|
17
iverilog/tobb/labs/lab2_prep/lab2.gprj.user
Normal file
17
iverilog/tobb/labs/lab2_prep/lab2.gprj.user
Normal file
@ -0,0 +1,17 @@
|
||||
<?xml version="1" encoding="UTF-8"?>
|
||||
<!DOCTYPE ProjectUserData>
|
||||
<UserConfig>
|
||||
<Version>1.0</Version>
|
||||
<FlowState>
|
||||
<Process ID="Synthesis" State="2"/>
|
||||
<Process ID="Pnr" State="0"/>
|
||||
<Process ID="Gao" State="0"/>
|
||||
<Process ID="Rtl_Gao" State="2"/>
|
||||
</FlowState>
|
||||
<ResultFileList>
|
||||
<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/lab2.vg"/>
|
||||
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/lab2_syn.rpt.html"/>
|
||||
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/lab2_syn_rsc.xml"/>
|
||||
</ResultFileList>
|
||||
<Ui>000000ff00000001fd0000000200000000000001700000013dfc0200000001fc000000630000013d0000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000000000030000050000000114fc0100000001fc0000000000000500000000a100fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000007800fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000a100ffffff000003880000013d00000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e0045006400690074010000009bffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000157ffffffff0000000000000000</Ui>
|
||||
</UserConfig>
|
77
iverilog/tobb/labs/lab2_prep/src/dmp.vcd
Normal file
77
iverilog/tobb/labs/lab2_prep/src/dmp.vcd
Normal file
@ -0,0 +1,77 @@
|
||||
$date
|
||||
Thu Apr 11 06:20:47 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module tb $end
|
||||
$var wire 1 ! w1 $end
|
||||
$var reg 1 " r1 $end
|
||||
$var reg 1 # r2 $end
|
||||
$var reg 1 $ r3 $end
|
||||
$var reg 1 % r4 $end
|
||||
$scope module uut $end
|
||||
$var wire 1 " A $end
|
||||
$var wire 1 & AD $end
|
||||
$var wire 1 ' An $end
|
||||
$var wire 1 ( AnBC $end
|
||||
$var wire 1 # B $end
|
||||
$var wire 1 ) Bn $end
|
||||
$var wire 1 $ C $end
|
||||
$var wire 1 * Cn $end
|
||||
$var wire 1 + CnD $end
|
||||
$var wire 1 % D $end
|
||||
$var wire 1 ! F $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$comment Show the parameter values. $end
|
||||
$dumpall
|
||||
$end
|
||||
#0
|
||||
$dumpvars
|
||||
0+
|
||||
1*
|
||||
1)
|
||||
0(
|
||||
1'
|
||||
0&
|
||||
0%
|
||||
0$
|
||||
0#
|
||||
0"
|
||||
1!
|
||||
$end
|
||||
#50
|
||||
1+
|
||||
1%
|
||||
#100
|
||||
0+
|
||||
0*
|
||||
0%
|
||||
1$
|
||||
#150
|
||||
1%
|
||||
#200
|
||||
0!
|
||||
1*
|
||||
0)
|
||||
0%
|
||||
0$
|
||||
1#
|
||||
#250
|
||||
1!
|
||||
1+
|
||||
1%
|
||||
#300
|
||||
0+
|
||||
1(
|
||||
0*
|
||||
0%
|
||||
1$
|
||||
#350
|
||||
1%
|
||||
#400
|
126
iverilog/tobb/labs/lab2_prep/src/lab
Normal file
126
iverilog/tobb/labs/lab2_prep/src/lab
Normal file
@ -0,0 +1,126 @@
|
||||
#! /c/Source/iverilog-install/bin/vvp
|
||||
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
|
||||
S_000001e2946aad20 .scope module, "tb" "tb" 2 1;
|
||||
.timescale 0 0;
|
||||
v000001e29475e7f0_0 .var "r1", 0 0;
|
||||
v000001e29475e6b0_0 .var "r2", 0 0;
|
||||
v000001e29475ec50_0 .var "r3", 0 0;
|
||||
v000001e29475e430_0 .var "r4", 0 0;
|
||||
v000001e29475ecf0_0 .net "w1", 0 0, L_000001e29475f0f0; 1 drivers
|
||||
S_000001e294717fc0 .scope module, "uut" "lab2" 2 6, 3 1 0, S_000001e2946aad20;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "C";
|
||||
.port_info 3 /INPUT 1 "D";
|
||||
.port_info 4 /OUTPUT 1 "F";
|
||||
L_000001e2947183d0 .functor NOT 1, v000001e29475e7f0_0, C4<0>, C4<0>, C4<0>;
|
||||
L_000001e2946e2bc0 .functor AND 1, L_000001e2947183d0, v000001e29475e6b0_0, v000001e29475ec50_0, C4<1>;
|
||||
L_000001e2946e2d20 .functor NOT 1, v000001e29475e6b0_0, C4<0>, C4<0>, C4<0>;
|
||||
L_000001e29475f390 .functor AND 1, v000001e29475e7f0_0, v000001e29475e430_0, C4<1>, C4<1>;
|
||||
L_000001e29475f4e0 .functor NOT 1, v000001e29475ec50_0, C4<0>, C4<0>, C4<0>;
|
||||
L_000001e29475f780 .functor AND 1, L_000001e29475f4e0, v000001e29475e430_0, C4<1>, C4<1>;
|
||||
L_000001e29475f0f0 .functor OR 1, L_000001e2946e2bc0, L_000001e2946e2d20, L_000001e29475f390, L_000001e29475f780;
|
||||
v000001e2946e2a40_0 .net "A", 0 0, v000001e29475e7f0_0; 1 drivers
|
||||
v000001e2946e28d0_0 .net "AD", 0 0, L_000001e29475f390; 1 drivers
|
||||
v000001e2946a9e10_0 .net "An", 0 0, L_000001e2947183d0; 1 drivers
|
||||
v000001e2946aaeb0_0 .net "AnBC", 0 0, L_000001e2946e2bc0; 1 drivers
|
||||
v000001e294718150_0 .net "B", 0 0, v000001e29475e6b0_0; 1 drivers
|
||||
v000001e2947181f0_0 .net "Bn", 0 0, L_000001e2946e2d20; 1 drivers
|
||||
v000001e294718290_0 .net "C", 0 0, v000001e29475ec50_0; 1 drivers
|
||||
v000001e294718330_0 .net "Cn", 0 0, L_000001e29475f4e0; 1 drivers
|
||||
v000001e294714e50_0 .net "CnD", 0 0, L_000001e29475f780; 1 drivers
|
||||
v000001e294714ef0_0 .net "D", 0 0, v000001e29475e430_0; 1 drivers
|
||||
v000001e29475e390_0 .net "F", 0 0, L_000001e29475f0f0; alias, 1 drivers
|
||||
.scope S_000001e2946aad20;
|
||||
T_0 ;
|
||||
%vpi_call 2 17 "$dumpfile", "dmp.vcd" {0 0 0};
|
||||
%vpi_call 2 18 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e7f0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e6b0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475ec50_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e430_0, 0, 1;
|
||||
%delay 50, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e7f0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e6b0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475ec50_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475e430_0, 0, 1;
|
||||
%delay 50, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e7f0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e6b0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475ec50_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e430_0, 0, 1;
|
||||
%delay 50, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e7f0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e6b0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475ec50_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475e430_0, 0, 1;
|
||||
%delay 50, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e7f0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475e6b0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475ec50_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e430_0, 0, 1;
|
||||
%delay 50, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e7f0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475e6b0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475ec50_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475e430_0, 0, 1;
|
||||
%delay 50, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e7f0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475e6b0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475ec50_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e430_0, 0, 1;
|
||||
%delay 50, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e7f0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475e6b0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475ec50_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475e430_0, 0, 1;
|
||||
%delay 50, 0;
|
||||
%vpi_call 2 27 "$display", v000001e29475ecf0_0 {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"tb.v";
|
||||
"lab2.v";
|
43
iverilog/tobb/labs/lab2_prep/src/lab2
Normal file
43
iverilog/tobb/labs/lab2_prep/src/lab2
Normal file
@ -0,0 +1,43 @@
|
||||
#! /c/Source/iverilog-install/bin/vvp
|
||||
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
|
||||
S_0000016d6fd625e0 .scope module, "lab2" "lab2" 2 1;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "C";
|
||||
.port_info 3 /INPUT 1 "D";
|
||||
.port_info 4 /OUTPUT 1 "F";
|
||||
o0000016d6fd96f98 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
L_0000016d6fd62f70 .functor NOT 1, o0000016d6fd96f98, C4<0>, C4<0>, C4<0>;
|
||||
o0000016d6fd97058 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
o0000016d6fd970b8 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
L_0000016d6fedb7d0 .functor AND 1, L_0000016d6fd62f70, o0000016d6fd97058, o0000016d6fd970b8, C4<1>;
|
||||
L_0000016d6fedb840 .functor NOT 1, o0000016d6fd97058, C4<0>, C4<0>, C4<0>;
|
||||
o0000016d6fd97148 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
L_0000016d6fedb8b0 .functor AND 1, o0000016d6fd96f98, o0000016d6fd97148, C4<1>, C4<1>;
|
||||
L_0000016d6fedb920 .functor NOT 1, o0000016d6fd970b8, C4<0>, C4<0>, C4<0>;
|
||||
L_0000016d6fedb990 .functor AND 1, L_0000016d6fedb920, o0000016d6fd97148, C4<1>, C4<1>;
|
||||
L_0000016d6fedba00 .functor OR 1, L_0000016d6fedb7d0, L_0000016d6fedb840, L_0000016d6fedb8b0, L_0000016d6fedb990;
|
||||
v0000016d6fd62b30_0 .net "A", 0 0, o0000016d6fd96f98; 0 drivers
|
||||
v0000016d6fd62d50_0 .net "AD", 0 0, L_0000016d6fedb8b0; 1 drivers
|
||||
v0000016d6fd62770_0 .net "An", 0 0, L_0000016d6fd62f70; 1 drivers
|
||||
v0000016d6fd62810_0 .net "AnBC", 0 0, L_0000016d6fedb7d0; 1 drivers
|
||||
v0000016d6fd628b0_0 .net "B", 0 0, o0000016d6fd97058; 0 drivers
|
||||
v0000016d6fededb0_0 .net "Bn", 0 0, L_0000016d6fedb840; 1 drivers
|
||||
v0000016d6fedee50_0 .net "C", 0 0, o0000016d6fd970b8; 0 drivers
|
||||
v0000016d6fedeef0_0 .net "Cn", 0 0, L_0000016d6fedb920; 1 drivers
|
||||
v0000016d6fedb600_0 .net "CnD", 0 0, L_0000016d6fedb990; 1 drivers
|
||||
v0000016d6fedb730_0 .net "D", 0 0, o0000016d6fd97148; 0 drivers
|
||||
v0000016d6fd90c30_0 .net "F", 0 0, L_0000016d6fedba00; 1 drivers
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 3;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"lab2.v";
|
24
iverilog/tobb/labs/lab2_prep/src/lab2.v
Normal file
24
iverilog/tobb/labs/lab2_prep/src/lab2.v
Normal file
@ -0,0 +1,24 @@
|
||||
module lab2(
|
||||
input A,
|
||||
input B,
|
||||
input C,
|
||||
input D,
|
||||
output F
|
||||
);
|
||||
|
||||
wire An, Bn, Cn;
|
||||
wire AnBC, AD, CnD;
|
||||
|
||||
not n1 (An, A);
|
||||
and (AnBC, An, B, C);
|
||||
|
||||
not (Bn, B);
|
||||
and (AD, A, D);
|
||||
|
||||
not (Cn, C);
|
||||
and (CnD, Cn, D);
|
||||
|
||||
or (F, AnBC, Bn, AD, CnD);
|
||||
|
||||
|
||||
endmodule
|
43
iverilog/tobb/labs/lab2_prep/src/labwave
Normal file
43
iverilog/tobb/labs/lab2_prep/src/labwave
Normal file
@ -0,0 +1,43 @@
|
||||
#! /c/Source/iverilog-install/bin/vvp
|
||||
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
|
||||
S_000001e0df4625e0 .scope module, "f_lab2" "f_lab2" 2 1;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "C";
|
||||
.port_info 3 /INPUT 1 "D";
|
||||
.port_info 4 /OUTPUT 1 "F";
|
||||
o000001e0df496fd8 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
L_000001e0df462f70 .functor NOT 1, o000001e0df496fd8, C4<0>, C4<0>, C4<0>;
|
||||
o000001e0df497098 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
o000001e0df4970f8 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
L_000001e0df64aa10 .functor AND 1, L_000001e0df462f70, o000001e0df497098, o000001e0df4970f8, C4<1>;
|
||||
L_000001e0df64aa80 .functor NOT 1, o000001e0df497098, C4<0>, C4<0>, C4<0>;
|
||||
o000001e0df497188 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
L_000001e0df64aaf0 .functor AND 1, o000001e0df496fd8, o000001e0df497188, C4<1>, C4<1>;
|
||||
L_000001e0df64ab60 .functor NOT 1, o000001e0df4970f8, C4<0>, C4<0>, C4<0>;
|
||||
L_000001e0df64abd0 .functor AND 1, L_000001e0df64ab60, o000001e0df497188, C4<1>, C4<1>;
|
||||
L_000001e0df64ac40 .functor OR 1, L_000001e0df64aa10, L_000001e0df64aa80, L_000001e0df64aaf0, L_000001e0df64abd0;
|
||||
v000001e0df462b30_0 .net "A", 0 0, o000001e0df496fd8; 0 drivers
|
||||
v000001e0df462d50_0 .net "AD", 0 0, L_000001e0df64aaf0; 1 drivers
|
||||
v000001e0df462770_0 .net "An", 0 0, L_000001e0df462f70; 1 drivers
|
||||
v000001e0df462810_0 .net "AnBC", 0 0, L_000001e0df64aa10; 1 drivers
|
||||
v000001e0df4628b0_0 .net "B", 0 0, o000001e0df497098; 0 drivers
|
||||
v000001e0df64ed90_0 .net "Bn", 0 0, L_000001e0df64aa80; 1 drivers
|
||||
v000001e0df64ee30_0 .net "C", 0 0, o000001e0df4970f8; 0 drivers
|
||||
v000001e0df64eed0_0 .net "Cn", 0 0, L_000001e0df64ab60; 1 drivers
|
||||
v000001e0df64a840_0 .net "CnD", 0 0, L_000001e0df64abd0; 1 drivers
|
||||
v000001e0df64a970_0 .net "D", 0 0, o000001e0df497188; 0 drivers
|
||||
v000001e0df492660_0 .net "F", 0 0, L_000001e0df64ac40; 1 drivers
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 3;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
".\f_lab2.v";
|
32
iverilog/tobb/labs/lab2_prep/src/tb.v
Normal file
32
iverilog/tobb/labs/lab2_prep/src/tb.v
Normal file
@ -0,0 +1,32 @@
|
||||
module tb();
|
||||
|
||||
reg r1, r2, r3, r4;
|
||||
wire w1;
|
||||
|
||||
lab2 uut(
|
||||
.A(r1),
|
||||
.B(r2),
|
||||
.C(r3),
|
||||
.D(r4),
|
||||
.F(w1)
|
||||
);
|
||||
|
||||
// test uut(r1, r2, w1, w2, w3);
|
||||
|
||||
initial begin
|
||||
$dumpfile("dmp.vcd");
|
||||
$dumpvars;
|
||||
r1 = 1'b0; r2 = 1'b0; r3 = 1'b0; r4 = 1'b0; #50;
|
||||
r1 = 1'b0; r2 = 1'b0; r3 = 1'b0; r4 = 1'b1; #50;
|
||||
r1 = 1'b0; r2 = 1'b0; r3 = 1'b1; r4 = 1'b0; #50;
|
||||
r1 = 1'b0; r2 = 1'b0; r3 = 1'b1; r4 = 1'b1; #50;
|
||||
r1 = 1'b0; r2 = 1'b1; r3 = 1'b0; r4 = 1'b0; #50;
|
||||
r1 = 1'b0; r2 = 1'b1; r3 = 1'b0; r4 = 1'b1; #50;
|
||||
r1 = 1'b0; r2 = 1'b1; r3 = 1'b1; r4 = 1'b0; #50;
|
||||
r1 = 1'b0; r2 = 1'b1; r3 = 1'b1; r4 = 1'b1; #50;
|
||||
$display(w1);
|
||||
end
|
||||
|
||||
|
||||
|
||||
endmodule
|
27
iverilog/tobb/labs/lab3/impl/gwsynthesis/lab3.log
Normal file
27
iverilog/tobb/labs/lab3/impl/gwsynthesis/lab3.log
Normal file
@ -0,0 +1,27 @@
|
||||
GowinSynthesis start
|
||||
Running parser ...
|
||||
Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\fullAdder.v'
|
||||
Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\halfAdder.v'
|
||||
Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\mult2bit.v'
|
||||
Compiling module 'mult2bit'("C:\cygwin64\home\koray\verilog\lab3\src\mult2bit.v":1)
|
||||
Compiling module 'halfAdder'("C:\cygwin64\home\koray\verilog\lab3\src\halfAdder.v":1)
|
||||
NOTE (EX0101) : Current top module is "mult2bit"
|
||||
[5%] Running netlist conversion ...
|
||||
Running device independent optimization ...
|
||||
[10%] Optimizing Phase 0 completed
|
||||
[15%] Optimizing Phase 1 completed
|
||||
[25%] Optimizing Phase 2 completed
|
||||
Running inference ...
|
||||
[30%] Inferring Phase 0 completed
|
||||
[40%] Inferring Phase 1 completed
|
||||
[50%] Inferring Phase 2 completed
|
||||
[55%] Inferring Phase 3 completed
|
||||
Running technical mapping ...
|
||||
[60%] Tech-Mapping Phase 0 completed
|
||||
[65%] Tech-Mapping Phase 1 completed
|
||||
[75%] Tech-Mapping Phase 2 completed
|
||||
[80%] Tech-Mapping Phase 3 completed
|
||||
[90%] Tech-Mapping Phase 4 completed
|
||||
[95%] Generate netlist file "C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg" completed
|
||||
[100%] Generate report file "C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3_syn.rpt.html" completed
|
||||
GowinSynthesis finish
|
21
iverilog/tobb/labs/lab3/impl/gwsynthesis/lab3.prj
Normal file
21
iverilog/tobb/labs/lab3/impl/gwsynthesis/lab3.prj
Normal file
@ -0,0 +1,21 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE gowin-synthesis-project>
|
||||
<Project>
|
||||
<Version>beta</Version>
|
||||
<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
|
||||
<FileList>
|
||||
<File path="C:\cygwin64\home\koray\verilog\lab3\src\fullAdder.v" type="verilog"/>
|
||||
<File path="C:\cygwin64\home\koray\verilog\lab3\src\halfAdder.v" type="verilog"/>
|
||||
<File path="C:\cygwin64\home\koray\verilog\lab3\src\mult2bit.v" type="verilog"/>
|
||||
</FileList>
|
||||
<OptionList>
|
||||
<Option type="disable_insert_pad" value="0"/>
|
||||
<Option type="global_freq" value="100.000"/>
|
||||
<Option type="looplimit" value="2000"/>
|
||||
<Option type="output_file" value="C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg"/>
|
||||
<Option type="print_all_synthesis_warning" value="0"/>
|
||||
<Option type="ram_rw_check" value="0"/>
|
||||
<Option type="verilog_language" value="verilog-2001"/>
|
||||
<Option type="vhdl_language" value="vhdl-1993"/>
|
||||
</OptionList>
|
||||
</Project>
|
144
iverilog/tobb/labs/lab3/impl/gwsynthesis/lab3.vg
Normal file
144
iverilog/tobb/labs/lab3/impl/gwsynthesis/lab3.vg
Normal file
@ -0,0 +1,144 @@
|
||||
//
|
||||
//Written by GowinSynthesis
|
||||
//Tool Version "V1.9.9.02"
|
||||
//Sat May 4 01:07:38 2024
|
||||
|
||||
//Source file index table:
|
||||
//file0 "\C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v"
|
||||
//file1 "\C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v"
|
||||
//file2 "\C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v"
|
||||
`timescale 100 ps/100 ps
|
||||
module halfAdder (
|
||||
A_d,
|
||||
B_d,
|
||||
C_d
|
||||
)
|
||||
;
|
||||
input [1:0] A_d;
|
||||
input [1:0] B_d;
|
||||
output [1:1] C_d;
|
||||
wire VCC;
|
||||
wire GND;
|
||||
LUT4 C_d_1_s (
|
||||
.F(C_d[1]),
|
||||
.I0(A_d[1]),
|
||||
.I1(B_d[0]),
|
||||
.I2(A_d[0]),
|
||||
.I3(B_d[1])
|
||||
);
|
||||
defparam C_d_1_s.INIT=16'h7888;
|
||||
VCC VCC_cZ (
|
||||
.V(VCC)
|
||||
);
|
||||
GND GND_cZ (
|
||||
.G(GND)
|
||||
);
|
||||
endmodule /* halfAdder */
|
||||
module halfAdder_0 (
|
||||
A_d,
|
||||
B_d,
|
||||
C_d
|
||||
)
|
||||
;
|
||||
input [1:0] A_d;
|
||||
input [1:0] B_d;
|
||||
output [3:2] C_d;
|
||||
wire VCC;
|
||||
wire GND;
|
||||
LUT4 C_d_3_s (
|
||||
.F(C_d[3]),
|
||||
.I0(A_d[0]),
|
||||
.I1(B_d[0]),
|
||||
.I2(A_d[1]),
|
||||
.I3(B_d[1])
|
||||
);
|
||||
defparam C_d_3_s.INIT=16'h7000;
|
||||
LUT4 C_d_2_s (
|
||||
.F(C_d[2]),
|
||||
.I0(A_d[1]),
|
||||
.I1(B_d[0]),
|
||||
.I2(A_d[0]),
|
||||
.I3(B_d[1])
|
||||
);
|
||||
defparam C_d_2_s.INIT=16'h8000;
|
||||
VCC VCC_cZ (
|
||||
.V(VCC)
|
||||
);
|
||||
GND GND_cZ (
|
||||
.G(GND)
|
||||
);
|
||||
endmodule /* halfAdder_0 */
|
||||
module mult2bit (
|
||||
A,
|
||||
B,
|
||||
C
|
||||
)
|
||||
;
|
||||
input [1:0] A;
|
||||
input [1:0] B;
|
||||
output [3:0] C;
|
||||
wire [1:0] A_d;
|
||||
wire [1:0] B_d;
|
||||
wire [0:0] C_d;
|
||||
wire [1:1] C_d_0;
|
||||
wire [3:2] C_d_1;
|
||||
wire VCC;
|
||||
wire GND;
|
||||
IBUF A_0_ibuf (
|
||||
.O(A_d[0]),
|
||||
.I(A[0])
|
||||
);
|
||||
IBUF A_1_ibuf (
|
||||
.O(A_d[1]),
|
||||
.I(A[1])
|
||||
);
|
||||
IBUF B_0_ibuf (
|
||||
.O(B_d[0]),
|
||||
.I(B[0])
|
||||
);
|
||||
IBUF B_1_ibuf (
|
||||
.O(B_d[1]),
|
||||
.I(B[1])
|
||||
);
|
||||
OBUF C_0_obuf (
|
||||
.O(C[0]),
|
||||
.I(C_d[0])
|
||||
);
|
||||
OBUF C_1_obuf (
|
||||
.O(C[1]),
|
||||
.I(C_d_0[1])
|
||||
);
|
||||
OBUF C_2_obuf (
|
||||
.O(C[2]),
|
||||
.I(C_d_1[2])
|
||||
);
|
||||
OBUF C_3_obuf (
|
||||
.O(C[3]),
|
||||
.I(C_d_1[3])
|
||||
);
|
||||
LUT2 C_d_0_s (
|
||||
.F(C_d[0]),
|
||||
.I0(B_d[0]),
|
||||
.I1(A_d[0])
|
||||
);
|
||||
defparam C_d_0_s.INIT=4'h8;
|
||||
halfAdder h0 (
|
||||
.A_d(A_d[1:0]),
|
||||
.B_d(B_d[1:0]),
|
||||
.C_d(C_d_0[1])
|
||||
);
|
||||
halfAdder_0 h1 (
|
||||
.A_d(A_d[1:0]),
|
||||
.B_d(B_d[1:0]),
|
||||
.C_d(C_d_1[3:2])
|
||||
);
|
||||
VCC VCC_cZ (
|
||||
.V(VCC)
|
||||
);
|
||||
GND GND_cZ (
|
||||
.G(GND)
|
||||
);
|
||||
GSR GSR (
|
||||
.GSRI(VCC)
|
||||
);
|
||||
endmodule /* mult2bit */
|
173
iverilog/tobb/labs/lab3/impl/gwsynthesis/lab3_syn.rpt.html
Normal file
173
iverilog/tobb/labs/lab3/impl/gwsynthesis/lab3_syn.rpt.html
Normal file
@ -0,0 +1,173 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>synthesis Report</title>
|
||||
<style type="text/css">
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
|
||||
div#main_wrapper{ width: 100%; }
|
||||
div#content { margin-left: 350px; margin-right: 30px; }
|
||||
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
|
||||
div#catalog ul { list-style-type: none; }
|
||||
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
|
||||
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
|
||||
div#catalog a:visited { color: #0084ff; }
|
||||
div#catalog a:hover { color: #fff; background: #0084ff; }
|
||||
hr { margin-top: 30px; margin-bottom: 30px; }
|
||||
h1, h3 { text-align: center; }
|
||||
h1 {margin-top: 50px; }
|
||||
table, th, td { border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { padding: 5px 5px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
|
||||
table.detail_table td.label { min-width: 100px; width: 8%;}
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="main_wrapper">
|
||||
<div id="catalog_wrapper">
|
||||
<div id="catalog">
|
||||
<ul>
|
||||
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
|
||||
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
|
||||
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
|
||||
<ul>
|
||||
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
|
||||
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
|
||||
</ul>
|
||||
</li>
|
||||
</ul>
|
||||
</div><!-- catalog -->
|
||||
</div><!-- catalog_wrapper -->
|
||||
<div id="content">
|
||||
<h1><a name="about">Synthesis Messages</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Report Title</td>
|
||||
<td>GowinSynthesis Report</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Design File</td>
|
||||
<td>C:\cygwin64\home\koray\verilog\lab3\src\fullAdder.v<br>
|
||||
C:\cygwin64\home\koray\verilog\lab3\src\halfAdder.v<br>
|
||||
C:\cygwin64\home\koray\verilog\lab3\src\mult2bit.v<br>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">GowinSynthesis Constraints File</td>
|
||||
<td>---</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Tool Version</td>
|
||||
<td>V1.9.9.02</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Part Number</td>
|
||||
<td>GW2A-LV18PG256C8/I7</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device</td>
|
||||
<td>GW2A-18</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device Version</td>
|
||||
<td>C</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Created Time</td>
|
||||
<td>Sat May 4 01:07:38 2024
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Legal Announcement</td>
|
||||
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="summary">Synthesis Details</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Top Level Module</td>
|
||||
<td>mult2bit</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Synthesis Process</td>
|
||||
<td>Running parser:<br/> CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.134s, Peak memory usage = 417.762MB<br/>Running netlist conversion:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/> Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/>Running inference:<br/> Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/>Running technical mapping:<br/> Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Tech-Mapping Phase 3: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.308s, Peak memory usage = 417.762MB<br/> Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/>Generate output files:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 417.762MB<br/></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Total Time and Memory Usage</td>
|
||||
<td>CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.447s, Peak memory usage = 417.762MB</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="resource">Resource</a></h1>
|
||||
<h2><a name="usage">Resource Usage Summary</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label"><b>Resource</b></td>
|
||||
<td><b>Usage</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>I/O Port </b></td>
|
||||
<td>8</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>I/O Buf </b></td>
|
||||
<td>8</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    IBUF</td>
|
||||
<td>4</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    OBUF</td>
|
||||
<td>4</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>LUT </b></td>
|
||||
<td>4</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    LUT2</td>
|
||||
<td>1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    LUT4</td>
|
||||
<td>3</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="utilization">Resource Utilization Summary</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label"><b>Resource</b></td>
|
||||
<td><b>Usage</b></td>
|
||||
<td><b>Utilization</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Logic</td>
|
||||
<td>4(4 LUT, 0 ALU) / 20736</td>
|
||||
<td><1%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Register</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">  --Register as Latch</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">  --Register as FF</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">BSRAM</td>
|
||||
<td>0 / 46</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
@ -0,0 +1,66 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>Hierarchy Module Resource</title>
|
||||
<style type="text/css">
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
|
||||
div#main_wrapper{ width: 100%; }
|
||||
h1 {text-align: center; }
|
||||
h1 {margin-top: 36px; }
|
||||
table, th, td { border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { align = "center"; padding: 5px 2px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="main_wrapper">
|
||||
<div id="content">
|
||||
<h1>Hierarchy Module Resource</h1>
|
||||
<table>
|
||||
<tr>
|
||||
<th class="label">MODULE NAME</th>
|
||||
<th class="label">REG NUMBER</th>
|
||||
<th class="label">ALU NUMBER</th>
|
||||
<th class="label">LUT NUMBER</th>
|
||||
<th class="label">DSP NUMBER</th>
|
||||
<th class="label">BSRAM NUMBER</th>
|
||||
<th class="label">SSRAM NUMBER</th>
|
||||
<th class="label">ROM16 NUMBER</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">mult2bit (C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v)</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">1</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
</tr>
|
||||
<td class="label">    |--h0
|
||||
(C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v)</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">1</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
</tr>
|
||||
<td class="label">    |--h1
|
||||
(C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v)</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">2</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
@ -0,0 +1,5 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Module name="mult2bit" Lut="1" T_Lut="4(1)">
|
||||
<SubModule name="h0" Lut="1" T_Lut="1(1)"/>
|
||||
<SubModule name="h1" Lut="2" T_Lut="2(2)"/>
|
||||
</Module>
|
88
iverilog/tobb/labs/lab3/impl/lab3_process_config.json
Normal file
88
iverilog/tobb/labs/lab3/impl/lab3_process_config.json
Normal file
@ -0,0 +1,88 @@
|
||||
{
|
||||
"BACKGROUND_PROGRAMMING" : "off",
|
||||
"COMPRESS" : false,
|
||||
"CPU" : false,
|
||||
"CRC_CHECK" : true,
|
||||
"Clock_Route_Order" : 0,
|
||||
"Correct_Hold_Violation" : true,
|
||||
"DONE" : false,
|
||||
"DOWNLOAD_SPEED" : "default",
|
||||
"Disable_Insert_Pad" : false,
|
||||
"ENABLE_CTP" : false,
|
||||
"ENABLE_MERGE_MODE" : false,
|
||||
"ENCRYPTION_KEY" : false,
|
||||
"ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
|
||||
"ERROR_DECTION_AND_CORRECTION" : false,
|
||||
"ERROR_DECTION_ONLY" : false,
|
||||
"ERROR_INJECTION" : false,
|
||||
"EXTERNAL_MASTER_CONFIG_CLOCK" : false,
|
||||
"Enable_DSRM" : false,
|
||||
"FORMAT" : "binary",
|
||||
"FREQUENCY_DIVIDER" : "",
|
||||
"Generate_Constraint_File_of_Ports" : false,
|
||||
"Generate_IBIS_File" : false,
|
||||
"Generate_Plain_Text_Timing_Report" : false,
|
||||
"Generate_Post_PNR_Simulation_Model_File" : false,
|
||||
"Generate_Post_Place_File" : false,
|
||||
"Generate_SDF_File" : false,
|
||||
"Generate_VHDL_Post_PNR_Simulation_Model_File" : false,
|
||||
"Global_Freq" : "default",
|
||||
"GwSyn_Loop_Limit" : 2000,
|
||||
"HOTBOOT" : false,
|
||||
"I2C" : false,
|
||||
"I2C_SLAVE_ADDR" : "00",
|
||||
"IncludePath" : [
|
||||
|
||||
],
|
||||
"Incremental_Compile" : "",
|
||||
"Initialize_Primitives" : false,
|
||||
"JTAG" : false,
|
||||
"MODE_IO" : false,
|
||||
"MSPI" : false,
|
||||
"MSPI_JUMP" : false,
|
||||
"MULTIBOOT_ADDRESS_WIDTH" : "24",
|
||||
"MULTIBOOT_MODE" : "Normal",
|
||||
"MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000",
|
||||
"MULTIJUMP_ADDRESS_WIDTH" : "24",
|
||||
"MULTIJUMP_MODE" : "Normal",
|
||||
"MULTIJUMP_SPI_FLASH_ADDRESS" : "000000",
|
||||
"Multi_Boot" : true,
|
||||
"OUTPUT_BASE_NAME" : "lab3",
|
||||
"POWER_ON_RESET_MONITOR" : true,
|
||||
"PRINT_BSRAM_VALUE" : true,
|
||||
"PROGRAM_DONE_BYPASS" : false,
|
||||
"PlaceInRegToIob" : true,
|
||||
"PlaceIoRegToIob" : true,
|
||||
"PlaceOutRegToIob" : true,
|
||||
"Place_Option" : "0",
|
||||
"Process_Configuration_Verion" : "1.0",
|
||||
"Promote_Physical_Constraint_Warning_to_Error" : true,
|
||||
"READY" : false,
|
||||
"RECONFIG_N" : false,
|
||||
"Ram_RW_Check" : false,
|
||||
"Replicate_Resources" : false,
|
||||
"Report_Auto-Placed_Io_Information" : false,
|
||||
"Route_Maxfan" : 23,
|
||||
"Route_Option" : "0",
|
||||
"Run_Timing_Driven" : true,
|
||||
"SECURE_MODE" : false,
|
||||
"SECURITY_BIT" : true,
|
||||
"SEU_HANDLER" : false,
|
||||
"SEU_HANDLER_CHECKSUM" : false,
|
||||
"SEU_HANDLER_MODE" : "auto",
|
||||
"SSPI" : false,
|
||||
"STOP_SEU_HANDLER" : false,
|
||||
"Show_All_Warnings" : false,
|
||||
"Synthesize_tool" : "GowinSyn",
|
||||
"TclPre" : "",
|
||||
"TopModule" : "",
|
||||
"USERCODE" : "default",
|
||||
"Unused_Pin" : "As_input_tri_stated_with_pull_up",
|
||||
"VCCAUX" : 3.3,
|
||||
"VCCX" : "3.3",
|
||||
"VHDL_Standard" : "VHDL_Std_1993",
|
||||
"Verilog_Standard" : "Vlg_Std_2001",
|
||||
"WAKE_UP" : "0",
|
||||
"show_all_warnings" : false,
|
||||
"turn_off_bg" : false
|
||||
}
|
12
iverilog/tobb/labs/lab3/impl/pnr/cmd.do
Normal file
12
iverilog/tobb/labs/lab3/impl/pnr/cmd.do
Normal file
@ -0,0 +1,12 @@
|
||||
-d C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg
|
||||
-p GW2A-18C-PBGA256-8
|
||||
-pn GW2A-LV18PG256C8/I7
|
||||
-cfg C:\cygwin64\home\koray\verilog\lab3\impl\pnr\device.cfg
|
||||
-bit
|
||||
-tr
|
||||
-ph
|
||||
-timing
|
||||
-cst_error
|
||||
-correct_hold 1
|
||||
-route_maxfan 23
|
||||
-global_freq 100.000
|
21
iverilog/tobb/labs/lab3/impl/pnr/device.cfg
Normal file
21
iverilog/tobb/labs/lab3/impl/pnr/device.cfg
Normal file
@ -0,0 +1,21 @@
|
||||
set JTAG regular_io = false
|
||||
set SSPI regular_io = false
|
||||
set MSPI regular_io = false
|
||||
set READY regular_io = false
|
||||
set DONE regular_io = false
|
||||
set I2C regular_io = false
|
||||
set RECONFIG_N regular_io = false
|
||||
set CRC_check = true
|
||||
set compress = false
|
||||
set encryption = false
|
||||
set security_bit_enable = true
|
||||
set bsram_init_fuse_print = true
|
||||
set background_programming = off
|
||||
set secure_mode = false
|
||||
set program_done_bypass = false
|
||||
set wake_up = 0
|
||||
set format = binary
|
||||
set power_on_reset_monitor = true
|
||||
set multiboot_spi_flash_address = 0x00000000
|
||||
set vccx = 3.3
|
||||
set unused_pin = default
|
BIN
iverilog/tobb/labs/lab3/impl/pnr/lab3.bin
Normal file
BIN
iverilog/tobb/labs/lab3/impl/pnr/lab3.bin
Normal file
Binary file not shown.
BIN
iverilog/tobb/labs/lab3/impl/pnr/lab3.binx
Normal file
BIN
iverilog/tobb/labs/lab3/impl/pnr/lab3.binx
Normal file
Binary file not shown.
BIN
iverilog/tobb/labs/lab3/impl/pnr/lab3.db
Normal file
BIN
iverilog/tobb/labs/lab3/impl/pnr/lab3.db
Normal file
Binary file not shown.
1378
iverilog/tobb/labs/lab3/impl/pnr/lab3.fs
Normal file
1378
iverilog/tobb/labs/lab3/impl/pnr/lab3.fs
Normal file
File diff suppressed because it is too large
Load Diff
27
iverilog/tobb/labs/lab3/impl/pnr/lab3.log
Normal file
27
iverilog/tobb/labs/lab3/impl/pnr/lab3.log
Normal file
@ -0,0 +1,27 @@
|
||||
Reading netlist file: "C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg"
|
||||
Parsing netlist file "C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg" completed
|
||||
Processing netlist completed
|
||||
Running placement......
|
||||
[10%] Placement Phase 0 completed
|
||||
[20%] Placement Phase 1 completed
|
||||
[30%] Placement Phase 2 completed
|
||||
[50%] Placement Phase 3 completed
|
||||
Running routing......
|
||||
[60%] Routing Phase 0 completed
|
||||
[70%] Routing Phase 1 completed
|
||||
[80%] Routing Phase 2 completed
|
||||
[90%] Routing Phase 3 completed
|
||||
Running timing analysis......
|
||||
[95%] Timing analysis completed
|
||||
Placement and routing completed
|
||||
Bitstream generation in progress......
|
||||
Bitstream generation completed
|
||||
Running power analysis......
|
||||
[100%] Power analysis completed
|
||||
Generate file "C:\cygwin64\home\koray\verilog\lab3\impl\pnr\lab3.power.html" completed
|
||||
Generate file "C:\cygwin64\home\koray\verilog\lab3\impl\pnr\lab3.pin.html" completed
|
||||
Generate file "C:\cygwin64\home\koray\verilog\lab3\impl\pnr\lab3.rpt.html" completed
|
||||
Generate file "C:\cygwin64\home\koray\verilog\lab3\impl\pnr\lab3.rpt.txt" completed
|
||||
Generate file "C:\cygwin64\home\koray\verilog\lab3\impl\pnr\lab3.tr.html" completed
|
||||
Sat May 4 01:07:45 2024
|
||||
|
3591
iverilog/tobb/labs/lab3/impl/pnr/lab3.pin.html
Normal file
3591
iverilog/tobb/labs/lab3/impl/pnr/lab3.pin.html
Normal file
File diff suppressed because it is too large
Load Diff
266
iverilog/tobb/labs/lab3/impl/pnr/lab3.power.html
Normal file
266
iverilog/tobb/labs/lab3/impl/pnr/lab3.power.html
Normal file
@ -0,0 +1,266 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//ENhttp://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>Power Analysis Report</title>
|
||||
<style type="text/css">
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
|
||||
div#main_wrapper { width: 100%; }
|
||||
div#content { margin-left: 350px; margin-right: 30px; }
|
||||
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
|
||||
div#catalog ul { list-style-type: none; }
|
||||
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
|
||||
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
|
||||
div#catalog a:visited { color: #0084ff; }
|
||||
div#catalog a:hover { color: #fff; background: #0084ff; }
|
||||
hr { margin-top: 30px; margin-bottom: 30px; }
|
||||
h1, h3 { text-align: center; }
|
||||
h1 {margin-top: 50px; }
|
||||
table, th, td {white-space:pre; border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { padding: 5px 5px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
|
||||
table.thermal_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
|
||||
table.Configure_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
|
||||
table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="main_wrapper">
|
||||
<div id="catalog_wrapper">
|
||||
<div id="catalog">
|
||||
<ul>
|
||||
<li><a href="#Message" style=" font-size: 16px;">Power Messages</a>
|
||||
</li>
|
||||
<li><a href="#Summary" style=" font-size: 16px;">Power Summary</a>
|
||||
<ul>
|
||||
<li><a href="#Power_Info" style=" font-size: 14px;">Power Information</a></li>
|
||||
<li><a href="#Thermal_Info" style=" font-size: 14px;">Thermal Information</a></li>
|
||||
<li><a href="#Configure_Info" style=" font-size: 14px;">Configure Information</a></li>
|
||||
<li><a href="#Supply_Summary" style=" font-size: 14px;">Supply Information</a></li>
|
||||
</ul>
|
||||
</li>
|
||||
<li><a href="#Detail" style=" font-size: 16px;">Power Details</a>
|
||||
<ul>
|
||||
<li><a href="#By_Block_Type" style=" font-size: 14px;">Power By Block Type</a></li>
|
||||
<li><a href="#By_Hierarchy" style=" font-size: 14px;">Power By Hierarchy</a></li>
|
||||
<li><a href="#By_Clock_Domain" style=" font-size: 14px;">Power By Clock Domain</a></li>
|
||||
</ul>
|
||||
</li>
|
||||
</ul>
|
||||
</div><!-- catalog -->
|
||||
</div><!-- catalog_wrapper -->
|
||||
<div id="content">
|
||||
<h1><a name="Message">Power Messages</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Report Title</td>
|
||||
<td>Power Analysis Report</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Design File</td>
|
||||
<td>C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Physical Constraints File</td>
|
||||
<td>---</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Timing Constraints File</td>
|
||||
<td>---</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Tool Version</td>
|
||||
<td>V1.9.9.02</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Part Number</td>
|
||||
<td>GW2A-LV18PG256C8/I7</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device</td>
|
||||
<td>GW2A-18</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device Version</td>
|
||||
<td>C</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Created Time</td>
|
||||
<td>Sat May 4 01:07:45 2024
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Legal Announcement</td>
|
||||
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="Summary">Power Summary</a></h1>
|
||||
<h2><a name="Power_Info">Power Information:</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Total Power (mW)</td>
|
||||
<td>92.439</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Quiescent Power (mW)</td>
|
||||
<td>91.608</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Dynamic Power (mW)</td>
|
||||
<td>0.832</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="Thermal_Info">Thermal Information:</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Junction Temperature</td>
|
||||
<td>27.960</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Theta JA</td>
|
||||
<td>32.020</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Max Allowed Ambient Temperature</td>
|
||||
<td>82.040</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="Configure_Info">Configure Information:</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Default IO Toggle Rate</td>
|
||||
<td>0.125</td>
|
||||
</tr>
|
||||
<td class="label">Default Remain Toggle Rate</td>
|
||||
<td>0.125</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Use Vectorless Estimation</td>
|
||||
<td>false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Filter Glitches</td>
|
||||
<td>false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Related Vcd File</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Related Saif File</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Use Custom Theta JA</td>
|
||||
<td>false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Air Flow</td>
|
||||
<td>LFM_0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Heat Sink</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Use Custom Theta SA</td>
|
||||
<td>false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Board Thermal Model</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Use Custom Theta JB</td>
|
||||
<td>false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Ambient Temperature</td>
|
||||
<td>25.000
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="Supply_Summary">Supply Information:</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<th class="label">Voltage Source</th>
|
||||
<th class="label">Voltage</th>
|
||||
<th class="label">Dynamic Current(mA)</th>
|
||||
<th class="label">Quiescent Current(mA)</th>
|
||||
<th class="label">Power(mW)</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>VCC</td>
|
||||
<td>1.000</td>
|
||||
<td>0.158</td>
|
||||
<td>61.510</td>
|
||||
<td>61.668</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>VCCX</td>
|
||||
<td>2.500</td>
|
||||
<td>0.158</td>
|
||||
<td>11.364</td>
|
||||
<td>28.803</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>VCCIO18</td>
|
||||
<td>1.800</td>
|
||||
<td>0.155</td>
|
||||
<td>0.938</td>
|
||||
<td>1.968</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="Detail">Power Details</a></h1>
|
||||
<h2><a name="By_Block_Type">Power By Block Type:</a></h2>
|
||||
<table class="detail_table">
|
||||
<tr>
|
||||
<th class="label">Block Type</th>
|
||||
<th class="label">Total Power(mW)</th>
|
||||
<th class="label">Static Power(mW)</th>
|
||||
<th class="label">Average Toggle Rate(millions of transitions/sec)</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>IO</td>
|
||||
<td>3.335
|
||||
<td>2.503
|
||||
<td>6.250
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2>
|
||||
<table class="detail_table">
|
||||
<tr>
|
||||
<th class="label">Hierarchy Entity</th>
|
||||
<th class="label">Total Power(mW)</th>
|
||||
<th class="label">Block Dynamic Power(mW)</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>mult2bit</td>
|
||||
<td>0.000</td>
|
||||
<td>0.000(0.000)</td>
|
||||
<tr>
|
||||
<td>mult2bit/h0/</td>
|
||||
<td>0.000</td>
|
||||
<td>0.000(0.000)</td>
|
||||
<tr>
|
||||
<td>mult2bit/h1/</td>
|
||||
<td>0.000</td>
|
||||
<td>0.000(0.000)</td>
|
||||
</table>
|
||||
<h2><a name="By_Clock_Domain">Power By Clock Domain:</a></h2>
|
||||
<table class="detail_table">
|
||||
<tr>
|
||||
<th class="label">Clock Domain</th>
|
||||
<th class="label">Clock Frequency(Mhz)</th>
|
||||
<th class="label">Total Dynamic Power(mW)</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>NO CLOCK DOMAIN</td>
|
||||
<td>0.000</td>
|
||||
<td>0.000</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
3837
iverilog/tobb/labs/lab3/impl/pnr/lab3.rpt.html
Normal file
3837
iverilog/tobb/labs/lab3/impl/pnr/lab3.rpt.html
Normal file
File diff suppressed because it is too large
Load Diff
346
iverilog/tobb/labs/lab3/impl/pnr/lab3.rpt.txt
Normal file
346
iverilog/tobb/labs/lab3/impl/pnr/lab3.rpt.txt
Normal file
@ -0,0 +1,346 @@
|
||||
//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
|
||||
//All rights reserved.
|
||||
|
||||
|
||||
1. PnR Messages
|
||||
|
||||
<Report Title>: PnR Report
|
||||
<Design File>: C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg
|
||||
<Physical Constraints File>: ---
|
||||
<Timing Constraints File>: ---
|
||||
<Tool Version>: V1.9.9.02
|
||||
<Part Number>: GW2A-LV18PG256C8/I7
|
||||
<Device>: GW2A-18
|
||||
<Device Version>: C
|
||||
<Created Time>:Sat May 4 01:07:45 2024
|
||||
|
||||
|
||||
2. PnR Details
|
||||
|
||||
Running placement:
|
||||
Placement Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s
|
||||
Placement Phase 1: CPU time = 0h 0m 0.546s, Elapsed time = 0h 0m 0.545s
|
||||
Placement Phase 2: CPU time = 0h 0m 0.005s, Elapsed time = 0h 0m 0.005s
|
||||
Placement Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
|
||||
Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
|
||||
Running routing:
|
||||
Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
|
||||
Routing Phase 1: CPU time = 0h 0m 0.314s, Elapsed time = 0h 0m 0.314s
|
||||
Routing Phase 2: CPU time = 0h 0m 0.152s, Elapsed time = 0h 0m 0.152s
|
||||
Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
|
||||
Total Routing: CPU time = 0h 0m 0.466s, Elapsed time = 0h 0m 0.466s
|
||||
Generate output files:
|
||||
CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
|
||||
|
||||
Total Time and Memory Usage: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 420MB
|
||||
|
||||
|
||||
3. Resource Usage Summary
|
||||
|
||||
----------------------------------------------------------
|
||||
Resources | Usage
|
||||
----------------------------------------------------------
|
||||
Logic | 4/20736 <1%
|
||||
--LUT,ALU,ROM16 | 4(4 LUT, 0 ALU, 0 ROM16)
|
||||
--SSRAM(RAM16) | 0
|
||||
Register | 0/16173 0%
|
||||
--Logic Register as Latch | 0/15552 0%
|
||||
--Logic Register as FF | 0/15552 0%
|
||||
--I/O Register as Latch | 0/621 0%
|
||||
--I/O Register as FF | 0/621 0%
|
||||
CLS | 3/10368 <1%
|
||||
I/O Port | 8
|
||||
I/O Buf | 8
|
||||
--Input Buf | 4
|
||||
--Output Buf | 4
|
||||
--Inout Buf | 0
|
||||
IOLOGIC | 0%
|
||||
BSRAM | 0%
|
||||
DSP | 0%
|
||||
PLL | 0/4 0%
|
||||
DCS | 0/8 0%
|
||||
DQCE | 0/24 0%
|
||||
OSC | 0/1 0%
|
||||
CLKDIV | 0/8 0%
|
||||
DLLDLY | 0/8 0%
|
||||
DQS | 0/9 0%
|
||||
DHCEN | 0/16 0%
|
||||
==========================================================
|
||||
|
||||
|
||||
|
||||
4. I/O Bank Usage Summary
|
||||
|
||||
-----------------------
|
||||
I/O Bank | Usage
|
||||
-----------------------
|
||||
bank 0 | 4/29(13%)
|
||||
bank 1 | 0/20(0%)
|
||||
bank 2 | 0/20(0%)
|
||||
bank 3 | 0/32(0%)
|
||||
bank 4 | 0/36(0%)
|
||||
bank 5 | 0/36(0%)
|
||||
bank 6 | 0/18(0%)
|
||||
bank 7 | 4/16(25%)
|
||||
=======================
|
||||
|
||||
|
||||
5. Global Clock Usage Summary
|
||||
|
||||
-------------------------------
|
||||
Global Clock | Usage
|
||||
-------------------------------
|
||||
PRIMARY | 0/8(0%)
|
||||
LW | 0/8(0%)
|
||||
GCLK_PIN | 0/8(0%)
|
||||
PLL | 0/4(0%)
|
||||
CLKDIV | 0/8(0%)
|
||||
DLLDLY | 0/8(0%)
|
||||
===============================
|
||||
|
||||
|
||||
6. Global Clock Signals
|
||||
|
||||
-------------------------------------------
|
||||
Signal | Global Clock | Location
|
||||
-------------------------------------------
|
||||
===========================================
|
||||
|
||||
|
||||
7. Pinout by Port Name
|
||||
|
||||
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
Port Name | Diff Pair | Loc./Bank | Constraint | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | BankVccio
|
||||
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
A[0] | | A15/7 | N | in | IOL2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
A[1] | | L15/0 | N | in | IOT2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B[0] | | D16/0 | N | in | IOT4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B[1] | | B12/7 | N | in | IOL7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
C[0] | | E14/0 | N | out | IOT4[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
|
||||
C[1] | | B14/7 | N | out | IOL2[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 1.8
|
||||
C[2] | | C12/7 | N | out | IOL7[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 1.8
|
||||
C[3] | | C16/0 | N | out | IOT5[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
|
||||
==================================================================================================================================================================================================================
|
||||
|
||||
|
||||
|
||||
|
||||
8. All Package Pins
|
||||
|
||||
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
Loc./Bank| Signal | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | Bank Vccio
|
||||
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
L15/0 | A[1] | in | IOT2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D16/0 | B[0] | in | IOT4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E14/0 | C[0] | out | IOT4[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
|
||||
C16/0 | C[3] | out | IOT5[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
|
||||
D15/0 | - | in | IOT5[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E16/0 | - | in | IOT6[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F15/0 | - | in | IOT6[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F13/0 | - | in | IOT8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G12/0 | - | in | IOT8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F14/0 | - | in | IOT9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F16/0 | - | in | IOT9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F12/0 | - | in | IOT12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G13/0 | - | in | IOT12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G15/0 | - | in | IOT13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G14/0 | - | in | IOT13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G11/0 | - | in | IOT14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H12/0 | - | in | IOT14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G16/0 | - | in | IOT16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H15/0 | - | in | IOT16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H13/0 | - | in | IOT18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J12/0 | - | in | IOT18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H14/0 | - | in | IOT20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H16/0 | - | in | IOT20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J16/0 | - | in | IOT22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J14/0 | - | in | IOT22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J15/0 | - | in | IOT24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K16/0 | - | in | IOT24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H11/0 | - | in | IOT27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J13/0 | - | in | IOT27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K14/1 | - | in | IOT30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K15/1 | - | in | IOT30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J11/1 | - | in | IOT32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L12/1 | - | in | IOT32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L16/1 | - | in | IOT34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L14/1 | - | in | IOT34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K13/1 | - | in | IOT36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K12/1 | - | in | IOT36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K11/1 | - | in | IOT38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L13/1 | - | in | IOT38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M14/1 | - | in | IOT40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M15/1 | - | in | IOT40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D14/1 | - | in | IOT44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E15/1 | - | in | IOT44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N15/1 | - | in | IOT48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P16/1 | - | in | IOT48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N16/1 | - | in | IOT52[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N14/1 | - | in | IOT52[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P15/1 | - | in | IOT54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R16/1 | - | in | IOT54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
A4/5 | - | in | IOB2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C5/5 | - | in | IOB2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D6/5 | - | in | IOB3[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E7/5 | - | in | IOB3[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A3/5 | - | in | IOB4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B4/5 | - | in | IOB4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A5/5 | - | in | IOB7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B6/5 | - | in | IOB7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B1/5 | - | in | IOB8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C2/5 | - | in | IOB8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D3/5 | - | in | IOB9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D1/5 | - | in | IOB9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E2/5 | - | in | IOB12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E3/5 | - | in | IOB12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B3/5 | - | in | IOB13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A2/5 | - | in | IOB13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C1/5 | - | in | IOB14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D2/5 | - | in | IOB14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E1/5 | - | in | IOB16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F2/5 | - | in | IOB16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F4/5 | - | in | IOB18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G6/5 | - | in | IOB18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F3/5 | - | in | IOB19[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F1/5 | - | in | IOB19[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G5/5 | - | in | IOB20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G4/5 | - | in | IOB20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G2/5 | - | in | IOB21[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G3/5 | - | in | IOB21[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F5/5 | - | in | IOB22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H6/5 | - | in | IOB22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G1/5 | - | in | IOB24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H2/5 | - | in | IOB24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H4/5 | - | in | IOB26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J6/5 | - | in | IOB26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J1/5 | - | in | IOB27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J3/5 | - | in | IOB27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L2/4 | - | in | IOB30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M1/4 | - | in | IOB30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H3/4 | - | in | IOB32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H1/4 | - | in | IOB32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J2/4 | - | in | IOB34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K1/4 | - | in | IOB34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H5/4 | - | in | IOB35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J4/4 | - | in | IOB35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K3/4 | - | in | IOB36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K2/4 | - | in | IOB36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J5/4 | - | in | IOB37[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K6/4 | - | in | IOB37[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L1/4 | - | in | IOB38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L3/4 | - | in | IOB38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K4/4 | - | in | IOB39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L5/4 | - | in | IOB39[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K5/4 | - | in | IOB40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L4/4 | - | in | IOB40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N2/4 | - | in | IOB41[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P1/4 | - | in | IOB41[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M3/4 | - | in | IOB42[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N1/4 | - | in | IOB42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M2/4 | - | in | IOB43[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N3/4 | - | in | IOB43[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R1/4 | - | in | IOB44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P2/4 | - | in | IOB44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P4/4 | - | in | IOB45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T4/4 | - | in | IOB45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R3/4 | - | in | IOB48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T2/4 | - | in | IOB48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P5/4 | - | in | IOB50[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R5/4 | - | in | IOB50[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R4/4 | - | in | IOB52[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T3/4 | - | in | IOB52[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R6/4 | - | in | IOB54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T5/4 | - | in | IOB54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
B14/7 | C[1] | out | IOL2[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 1.8
|
||||
A15/7 | A[0] | in | IOL2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
C12/7 | C[2] | out | IOL7[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 1.8
|
||||
B12/7 | B[1] | in | IOL7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
B13/7 | - | in | IOL8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A14/7 | - | in | IOL8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F10/7 | - | in | IOL11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B11/7 | - | in | IOL13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A12/7 | - | in | IOL13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A11/7 | - | in | IOL15[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C11/7 | - | in | IOL15[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D10/7 | - | in | IOL17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E10/7 | - | in | IOL17[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D11/7 | - | in | IOL22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A9/7 | - | in | IOL27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C9/7 | - | in | IOL27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C8/6 | - | in | IOL29[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A8/6 | - | in | IOL29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F9/6 | - | in | IOL31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E11/6 | - | in | IOL31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B9/6 | - | in | IOL33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A10/6 | - | in | IOL33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F8/6 | - | in | IOL35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D9/6 | - | in | IOL35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D8/6 | - | in | IOL38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E9/6 | - | in | IOL38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B7/6 | - | in | IOL40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C7/6 | - | in | IOL40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F7/6 | - | in | IOL45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E8/6 | - | in | IOL45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C4/6 | - | in | IOL47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B5/6 | - | in | IOL47[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E6/6 | - | in | IOL53[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D7/6 | - | in | IOL53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
T15/2 | - | in | IOR7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R14/2 | - | in | IOR7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P12/2 | - | in | IOR8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T13/2 | - | in | IOR8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R12/2 | - | in | IOR11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P13/2 | - | in | IOR11[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R11/2 | - | in | IOR17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T12/2 | - | in | IOR17[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R13/2 | - | in | IOR20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T14/2 | - | in | IOR20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M10/2 | - | in | IOR22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N11/2 | - | in | IOR22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T11/2 | - | in | IOR24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P11/2 | - | in | IOR24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C6/2 | - | out | IOR25[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
|
||||
B8/2 | - | in | IOR25[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A7/2 | - | in | IOR26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A6/2 | - | in | IOR26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N10/2 | - | in | IOR27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M11/2 | - | in | IOR27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T7/3 | - | in | IOR29[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R8/3 | - | in | IOR29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M16/3 | - | in | IOR30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B16/3 | - | in | IOR30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C15/3 | - | in | IOR31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B10/3 | - | in | IOR31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A13/3 | - | in | IOR32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C13/3 | - | in | IOR32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P10/3 | - | in | IOR33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R10/3 | - | in | IOR33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M9/3 | - | in | IOR34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L10/3 | - | in | IOR34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R9/3 | - | in | IOR35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T10/3 | - | in | IOR35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M8/3 | - | in | IOR36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N9/3 | - | in | IOR36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T9/3 | - | in | IOR38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P9/3 | - | in | IOR38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C10/3 | - | in | IOR39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N8/3 | - | in | IOR40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L9/3 | - | in | IOR40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P8/3 | - | in | IOR42[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T8/3 | - | in | IOR42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M6/3 | - | in | IOR44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L8/3 | - | in | IOR44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M7/3 | - | in | IOR47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N7/3 | - | in | IOR47[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R7/3 | - | in | IOR49[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P7/3 | - | in | IOR49[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N6/3 | - | in | IOR51[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P6/3 | - | in | IOR53[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T6/3 | - | in | IOR53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
====================================================================================================================================================================================
|
||||
|
||||
|
0
iverilog/tobb/labs/lab3/impl/pnr/lab3.timing_paths
Normal file
0
iverilog/tobb/labs/lab3/impl/pnr/lab3.timing_paths
Normal file
10
iverilog/tobb/labs/lab3/impl/pnr/lab3.tr.html
Normal file
10
iverilog/tobb/labs/lab3/impl/pnr/lab3.tr.html
Normal file
@ -0,0 +1,10 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>Timing Analysis Report</title>
|
||||
</head>
|
||||
<frameset cols="20%, 80%">
|
||||
<frame src="lab3_tr_cata.html" name="cataFrame" />
|
||||
<frame src="lab3_tr_content.html" name="mainFrame"/>
|
||||
</frameset>
|
||||
</html>
|
132
iverilog/tobb/labs/lab3/impl/pnr/lab3_tr_cata.html
Normal file
132
iverilog/tobb/labs/lab3/impl/pnr/lab3_tr_cata.html
Normal file
@ -0,0 +1,132 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>Timing Report Navigation</title>
|
||||
<style type="text/css">
|
||||
@import url(../temp/style.css);
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
|
||||
div#catalog_wrapper { width: 100%; }
|
||||
div#catalog ul { list-style: none; margin-left: -15px; }
|
||||
div#catalog ul li { margin: 3px 0 3px 0; text-align: left; color: #0084ff; white-space: nowrap; word-break: keep-all; }
|
||||
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 4px; margin: 0 0 0 0; }
|
||||
div#catalog a:visited { color: #0084ff; }
|
||||
div#catalog a:hover { color: #fff; background: #0084ff; }
|
||||
div.triangle_fake, div.triangle { display: inline-block; cursor: pointer; width: 8px; height: 0; border-top: 5px solid transparent; border-bottom: 5px solid transparent; }
|
||||
div.triangle_fake { border-left: 5px solid transparent; }
|
||||
div.triangle { border-left: 5px solid #0084ff; }
|
||||
div.triangle:hover { border-left-color: #000; }
|
||||
</style>
|
||||
<script>
|
||||
function onClick(obj){var childs=obj.parentNode.childNodes;for(var i=0;i<childs.length;i++){if(childs[i].tagName=="UL"){if(childs[i].style.display=="none"){childs[i].style.display="block"}else{childs[i].style.display="none"}}}};
|
||||
</script>
|
||||
</head>
|
||||
<body>
|
||||
<div id="catalog_wrapper">
|
||||
<div id="catalog">
|
||||
<ul>
|
||||
<!-- messages begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Message" target="mainFrame" style=" font-size: 16px;">Timing Messages</a></li>
|
||||
<!-- messages end-->
|
||||
<!-- summaries begin-->
|
||||
<li><div class="triangle" onclick="onClick(this)"></div><a href="lab3_tr_content.html#Summary" style=" font-size: 16px;" target="mainFrame">Timing Summaries</a>
|
||||
<ul>
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#STA_Tool_Run_Summary" style=" font-size: 14px;" target="mainFrame">STA Tool Run Summary</a></li>
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Clock_Report" style=" font-size: 14px;" target="mainFrame">Clock Summary</a></li>
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Max_Frequency_Report" style=" font-size: 14px;" target="mainFrame">Max Frequency Summary</a></li>
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Total_Negative_Slack_Report" style=" font-size: 14px;" target="mainFrame">Total Negative Slack Summary</a></li>
|
||||
</ul>
|
||||
</li>
|
||||
<!-- summaries end-->
|
||||
<!-- details begin-->
|
||||
<li><div class="triangle" onclick="onClick(this)"></div><a href="lab3_tr_content.html#Detail" style=" font-size: 16px;" target="mainFrame">Timing Details</a>
|
||||
<ul>
|
||||
<!--All_Path_Slack_Table begin-->
|
||||
<li><div class="triangle" onclick="onClick(this)"></div><a href="lab3_tr_content.html#All_Path_Slack_Table" style=" font-size: 14px;" target="mainFrame">Path Slacks Table</a>
|
||||
<ul>
|
||||
<!--Setup_Slack_Table begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Setup_Slack_Table" style=" font-size: 13px;" target="mainFrame">Setup Paths Table</a>
|
||||
</li>
|
||||
<!--Setup_Slack_Table end-->
|
||||
<!--Hold_Slack_Table begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Hold_Slack_Table" style=" font-size: 13px;" target="mainFrame">Hold Paths Table</a>
|
||||
</li>
|
||||
<!--Hold_Slack_Table end-->
|
||||
<!--Recovery_Slack_Table begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Recovery_Slack_Table" style=" font-size: 13px;" target="mainFrame">Recovery Paths Table</a>
|
||||
</li>
|
||||
<!--Recovery_Slack_Table end-->
|
||||
<!--Removal_Slack_Table begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Removal_Slack_Table" style=" font-size: 13px;" target="mainFrame">Removal Paths Table</a>
|
||||
</li>
|
||||
<!--Removal_Slack_Table end-->
|
||||
</ul>
|
||||
</li><!--All_Path_Slack_Table end-->
|
||||
<!--MIN_PULSE_WIDTH_TABLE begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#MIN_PULSE_WIDTH_TABLE" style=" font-size: 14px;" target="mainFrame">Minimum Pulse Width Table</a>
|
||||
</li>
|
||||
<!--MIN_PULSE_WIDTH_TABLE end-->
|
||||
<!--Timing_Report_by_Analysis_Type begin-->
|
||||
<li><div class="triangle" onclick="onClick(this)"></div><a href="lab3_tr_content.html#Timing_Report_by_Analysis_Type" style=" font-size: 14px;" target="mainFrame">Timing Report By Analysis Type</a>
|
||||
<ul>
|
||||
<!--Setup_Analysis begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Setup_Analysis" style=" font-size: 13px;" target="mainFrame">Setup Analysis Report</a>
|
||||
</li>
|
||||
<!--Setup_Analysis end-->
|
||||
<!--Hold_Analysis begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Hold_Analysis" style=" font-size: 13px;" target="mainFrame">Hold Analysis Report</a>
|
||||
</li>
|
||||
<!--Hold_Analysis end-->
|
||||
<!--Recovery_Analysis begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Recovery_Analysis" style=" font-size: 13px;" target="mainFrame">Recovery Analysis Report</a>
|
||||
</li>
|
||||
<!--Recovery_Analysis end-->
|
||||
<!--Removal_Analysis begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Removal_Analysis" style=" font-size: 13px;" target="mainFrame">Removal Analysis Report</a>
|
||||
</li>
|
||||
<!--Removal_Analysis end-->
|
||||
</ul>
|
||||
</li>
|
||||
<!--Timing_Report_by_Analysis_Type end-->
|
||||
<!--Minimum_Pulse_Width_Report begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Minimum_Pulse_Width_Report" style=" font-size: 14px;" target="mainFrame">Minimum Pulse Width Report</a>
|
||||
</li>
|
||||
<!--Minimum_Pulse_Width_Report end-->
|
||||
<!--High_Fanout_Nets_Report begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#High_Fanout_Nets_Report" style=" font-size: 14px;" target="mainFrame">High Fanout Nets Report</a></li>
|
||||
<!--High_Fanout_Nets_Report end-->
|
||||
<!--Route_Congestions_Report begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Route_Congestions_Report" style=" font-size: 14px;" target="mainFrame">Route Congestions Report</a></li>
|
||||
<!--Route_Congestions_Report end-->
|
||||
<!--Timing_Exceptions_Report begin-->
|
||||
<li><div class="triangle" onclick="onClick(this)"></div><a href="lab3_tr_content.html#Timing_Exceptions_Report" style=" font-size: 14px;" target="mainFrame">Timing Exceptions Report</a>
|
||||
<ul>
|
||||
<!--Setup_Analysis_Exceptions begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Setup_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Setup Analysis Report</a>
|
||||
</li>
|
||||
<!--Setup_Analysis_Exceptions end-->
|
||||
<!--Hold_Analysis_Exceptions begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Hold_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Hold Analysis Report</a>
|
||||
</li>
|
||||
<!--Hold_Analysis_Exceptions end-->
|
||||
<!--Recovery_Analysis_Exceptions begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Recovery_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Recovery Analysis Report</a>
|
||||
</li>
|
||||
<!--Recovery_Analysis_Exceptions end-->
|
||||
<!--Removal_Analysis_Exceptions begin-->
|
||||
<li><div class="triangle_fake" onclick="onClick(this)"></div><a href="lab3_tr_content.html#Removal_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Removal Analysis Report</a>
|
||||
</li>
|
||||
<!--Removal_Analysis_Exceptions end-->
|
||||
</ul>
|
||||
</li>
|
||||
<!--Timing_Exceptions_Report end-->
|
||||
<!--SDC_Report begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#SDC_Report" style=" font-size: 14px;" target="mainFrame">Timing Constraints Report</a></li>
|
||||
<!--SDC_Report end-->
|
||||
</ul>
|
||||
</li>
|
||||
<!-- details end-->
|
||||
</ul>
|
||||
</div><!-- catalog -->
|
||||
</div><!-- catalog_wrapper -->
|
||||
</body>
|
||||
</html>
|
249
iverilog/tobb/labs/lab3/impl/pnr/lab3_tr_content.html
Normal file
249
iverilog/tobb/labs/lab3/impl/pnr/lab3_tr_content.html
Normal file
@ -0,0 +1,249 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>Timing Analysis Report</title>
|
||||
<style type="text/css">
|
||||
@import url(../temp/style.css);
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
|
||||
div#content { width: 100%; margin: }
|
||||
hr { margin-top: 30px; margin-bottom: 30px; }
|
||||
h1, h3 { text-align: center; }
|
||||
h1 {margin-top: 50px; }
|
||||
table, th, td {white-space:pre; border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { padding: 5px 5px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
|
||||
table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="content">
|
||||
<h1><a name="Message">Timing Messages</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Report Title</td>
|
||||
<td>Timing Analysis Report</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Design File</td>
|
||||
<td>C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Physical Constraints File</td>
|
||||
<td>---</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Timing Constraint File</td>
|
||||
<td>---</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Tool Version</td>
|
||||
<td>V1.9.9.02</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Part Number</td>
|
||||
<td>GW2A-LV18PG256C8/I7</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device</td>
|
||||
<td>GW2A-18</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device Version</td>
|
||||
<td>C</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Created Time</td>
|
||||
<td>Sat May 4 01:07:45 2024
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Legal Announcement</td>
|
||||
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="Summary">Timing Summaries</a></h1>
|
||||
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Setup Delay Model</td>
|
||||
<td>Slow 0.95V 85C C8/I7</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Hold Delay Model</td>
|
||||
<td>Fast 1.05V 0C C8/I7</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Numbers of Paths Analyzed</td>
|
||||
<td>14</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Numbers of Endpoints Analyzed</td>
|
||||
<td>4</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Numbers of Falling Endpoints</td>
|
||||
<td>0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Numbers of Setup Violated Endpoints</td>
|
||||
<td>0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Numbers of Hold Violated Endpoints</td>
|
||||
<td>0</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="Clock_Report">Clock Summary:</a></h2>
|
||||
<table class="detail_table">
|
||||
<tr>
|
||||
<th class="label">Clock Name</th>
|
||||
<th class="label">Type</th>
|
||||
<th class="label">Period</th>
|
||||
<th class="label">Frequency(MHz)</th>
|
||||
<th class="label">Rise</th>
|
||||
<th class="label">Fall</th>
|
||||
<th class="label">Source</th>
|
||||
<th class="label">Master</th>
|
||||
<th class="label">Objects</th>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
|
||||
<table>
|
||||
<tr>
|
||||
<th>NO.</th>
|
||||
<th>Clock Name</th>
|
||||
<th>Constraint</th>
|
||||
<th>Actual Fmax</th>
|
||||
<th>Logic Level</th>
|
||||
<th>Entity</th>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
|
||||
<table class="detail_table">
|
||||
<tr>
|
||||
<th class="label">Clock Name</th>
|
||||
<th class="label">Analysis Type</th>
|
||||
<th class="label">Endpoints TNS</th>
|
||||
<th class="label">Number of Endpoints</th>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="Detail">Timing Details</a></h1>
|
||||
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
|
||||
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
|
||||
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
|
||||
<h4>Nothing to report!</h4>
|
||||
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
|
||||
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
|
||||
<h4>Nothing to report!</h4>
|
||||
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
|
||||
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
|
||||
<h4>Nothing to report!</h4>
|
||||
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
|
||||
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
|
||||
<h4>Nothing to report!</h4>
|
||||
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
|
||||
<table class="detail_table">
|
||||
<tr>
|
||||
<th class="label">Number</th>
|
||||
<th class="label">Slack</th>
|
||||
<th class="label">Actual Width</th>
|
||||
<th class="label">Required Width</th>
|
||||
<th class="label">Type</th>
|
||||
<th class="label">Clock</th>
|
||||
<th class="label">Objects</th>
|
||||
</tr>
|
||||
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
|
||||
<h4>Nothing to report!</h4>
|
||||
</table>
|
||||
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
|
||||
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
|
||||
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
|
||||
<h4>No setup paths to report!</h4>
|
||||
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
|
||||
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
|
||||
<h4>No hold paths to report!</h4>
|
||||
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
|
||||
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
|
||||
<h4>No recovery paths to report!</h4>
|
||||
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
|
||||
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
|
||||
<h4>No removal paths to report!</h4>
|
||||
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
|
||||
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
|
||||
<h4>Nothing to report!</h4>
|
||||
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
|
||||
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
|
||||
<table class="detail_table">
|
||||
<tr>
|
||||
<th class="label">FANOUT</th>
|
||||
<th class="label">NET NAME</th>
|
||||
<th class="label">WORST SLACK</th>
|
||||
<th class="label">MAX DELAY</th>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
|
||||
<h4>Report Command:report_route_congestion -max_grids 10</h4>
|
||||
<table class="detail_table">
|
||||
<tr>
|
||||
<th class="label">GRID LOC</th>
|
||||
<th class="label">ROUTE CONGESTIONS</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R2C2</td>
|
||||
<td>8.33%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R2C1</td>
|
||||
<td>5.56%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R1C2</td>
|
||||
<td>2.78%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R2C4</td>
|
||||
<td>2.78%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R7C1</td>
|
||||
<td>2.78%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R1C4</td>
|
||||
<td>2.78%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R28C51</td>
|
||||
<td>1.39%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R2C3</td>
|
||||
<td>1.39%</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
|
||||
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
|
||||
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
|
||||
<h4>No timing exceptions to report!</h4>
|
||||
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
|
||||
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
|
||||
<h4>No timing exceptions to report!</h4>
|
||||
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
|
||||
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
|
||||
<h4>No timing exceptions to report!</h4>
|
||||
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
|
||||
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
|
||||
<h4>No timing exceptions to report!</h4>
|
||||
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
|
||||
<table class="detail_table">
|
||||
<tr>
|
||||
<th class="label">SDC Command Type</th>
|
||||
<th class="label">State</th>
|
||||
<th class="label">Detail Command</th>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</body>
|
||||
</html>
|
54
iverilog/tobb/labs/lab3/impl/temp/rtl_parser.result
Normal file
54
iverilog/tobb/labs/lab3/impl/temp/rtl_parser.result
Normal file
@ -0,0 +1,54 @@
|
||||
[
|
||||
{
|
||||
"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v",
|
||||
"InstLine" : 1,
|
||||
"InstName" : "fullAdder",
|
||||
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "fullAdder",
|
||||
"SubInsts" : [
|
||||
{
|
||||
"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v",
|
||||
"InstLine" : 7,
|
||||
"InstName" : "h0",
|
||||
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "halfAdder"
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v",
|
||||
"InstLine" : 8,
|
||||
"InstName" : "h1",
|
||||
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "halfAdder"
|
||||
}
|
||||
]
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v",
|
||||
"InstLine" : 1,
|
||||
"InstName" : "mult2bit",
|
||||
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "mult2bit",
|
||||
"SubInsts" : [
|
||||
{
|
||||
"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v",
|
||||
"InstLine" : 14,
|
||||
"InstName" : "h0",
|
||||
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "halfAdder"
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v",
|
||||
"InstLine" : 15,
|
||||
"InstName" : "h1",
|
||||
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "halfAdder"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
25
iverilog/tobb/labs/lab3/impl/temp/rtl_parser_arg.json
Normal file
25
iverilog/tobb/labs/lab3/impl/temp/rtl_parser_arg.json
Normal file
@ -0,0 +1,25 @@
|
||||
{
|
||||
"Device" : "GW2A-18C",
|
||||
"Files" : [
|
||||
{
|
||||
"Path" : "C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v",
|
||||
"Type" : "verilog"
|
||||
},
|
||||
{
|
||||
"Path" : "C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v",
|
||||
"Type" : "verilog"
|
||||
},
|
||||
{
|
||||
"Path" : "C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v",
|
||||
"Type" : "verilog"
|
||||
}
|
||||
],
|
||||
"IncludePath" : [
|
||||
|
||||
],
|
||||
"LoopLimit" : 2000,
|
||||
"ResultFile" : "C:/cygwin64/home/koray/verilog/lab3/impl/temp/rtl_parser.result",
|
||||
"Top" : "",
|
||||
"VerilogStd" : "verilog_2001",
|
||||
"VhdlStd" : "vhdl_93"
|
||||
}
|
0
iverilog/tobb/labs/lab3/impl/temp/style.css
Normal file
0
iverilog/tobb/labs/lab3/impl/temp/style.css
Normal file
14
iverilog/tobb/labs/lab3/lab3.gprj
Normal file
14
iverilog/tobb/labs/lab3/lab3.gprj
Normal file
@ -0,0 +1,14 @@
|
||||
<?xml version="1" encoding="UTF-8"?>
|
||||
<!DOCTYPE gowin-fpga-project>
|
||||
<Project>
|
||||
<Template>FPGA</Template>
|
||||
<Version>5</Version>
|
||||
<Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device>
|
||||
<FileList>
|
||||
<File path="src/Adder3Bit.v" type="file.verilog" enable="0"/>
|
||||
<File path="src/fullAdder.v" type="file.verilog" enable="1"/>
|
||||
<File path="src/halfAdder.v" type="file.verilog" enable="1"/>
|
||||
<File path="src/mult2bit.v" type="file.verilog" enable="1"/>
|
||||
<File path="src/tbAdder3Bit.v" type="file.verilog" enable="0"/>
|
||||
</FileList>
|
||||
</Project>
|
24
iverilog/tobb/labs/lab3/lab3.gprj.user
Normal file
24
iverilog/tobb/labs/lab3/lab3.gprj.user
Normal file
@ -0,0 +1,24 @@
|
||||
<?xml version="1" encoding="UTF-8"?>
|
||||
<!DOCTYPE ProjectUserData>
|
||||
<UserConfig>
|
||||
<Version>1.0</Version>
|
||||
<FlowState>
|
||||
<Process ID="Synthesis" State="2"/>
|
||||
<Process ID="Pnr" State="2"/>
|
||||
<Process ID="Gao" State="2"/>
|
||||
<Process ID="Rtl_Gao" State="2"/>
|
||||
</FlowState>
|
||||
<ResultFileList>
|
||||
<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/lab3.vg"/>
|
||||
<ResultFile ResultFileType="RES.pnr.bitstream" ResultFilePath="impl/pnr/lab3.fs"/>
|
||||
<ResultFile ResultFileType="RES.pnr.pin.rpt" ResultFilePath="impl/pnr/lab3.pin.html"/>
|
||||
<ResultFile ResultFileType="RES.pnr.posp.bin" ResultFilePath="impl/pnr/lab3.db"/>
|
||||
<ResultFile ResultFileType="RES.pnr.pwr.rpt" ResultFilePath="impl/pnr/lab3.power.html"/>
|
||||
<ResultFile ResultFileType="RES.pnr.report" ResultFilePath="impl/pnr/lab3.rpt.html"/>
|
||||
<ResultFile ResultFileType="RES.pnr.timing.paths" ResultFilePath="impl/pnr/lab3.timing_paths"/>
|
||||
<ResultFile ResultFileType="RES.pnr.timing.rpt" ResultFilePath="impl/pnr/lab3.tr.html"/>
|
||||
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/lab3_syn.rpt.html"/>
|
||||
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/lab3_syn_rsc.xml"/>
|
||||
</ResultFileList>
|
||||
<Ui>000000ff00000001fd000000020000000000000170000002b1fc0200000001fc00000037000002b10000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000000000030000078000000121fc0100000001fc00000000000007800000009b00fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000005100fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff0000009b00ffffff0000060c000002b100000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e00450064006900740100000099ffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000153ffffffff0000000000000000</Ui>
|
||||
</UserConfig>
|
217
iverilog/tobb/labs/lab3/src/3bit
Normal file
217
iverilog/tobb/labs/lab3/src/3bit
Normal file
@ -0,0 +1,217 @@
|
||||
#! /c/Source/iverilog-install/bin/vvp
|
||||
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
|
||||
S_00000154a426eaa0 .scope module, "tb" "tb" 2 1;
|
||||
.timescale 0 0;
|
||||
v00000154a4316c30_0 .var "A", 2 0;
|
||||
v00000154a4316370_0 .var "B", 2 0;
|
||||
v00000154a4317770_0 .net "C", 3 0, L_00000154a43162d0; 1 drivers
|
||||
S_00000154a426ec30 .scope module, "uut" "Adder3Bit" 2 5, 3 1 0, S_00000154a426eaa0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 3 "A";
|
||||
.port_info 1 /INPUT 3 "B";
|
||||
.port_info 2 /OUTPUT 4 "C";
|
||||
v00000154a4316230_0 .net "A", 2 0, v00000154a4316c30_0; 1 drivers
|
||||
v00000154a43173b0_0 .net "B", 2 0, v00000154a4316370_0; 1 drivers
|
||||
v00000154a4317450_0 .net "C", 3 0, L_00000154a43162d0; alias, 1 drivers
|
||||
v00000154a4316050_0 .net "c1", 0 0, L_00000154a42aabe0; 1 drivers
|
||||
v00000154a43174f0_0 .net "c2", 0 0, L_00000154a42ab200; 1 drivers
|
||||
L_00000154a4315fb0 .part v00000154a4316c30_0, 0, 1;
|
||||
L_00000154a4315b50 .part v00000154a4316370_0, 0, 1;
|
||||
L_00000154a4316190 .part v00000154a4316c30_0, 1, 1;
|
||||
L_00000154a4317590 .part v00000154a4316370_0, 1, 1;
|
||||
L_00000154a4317630 .part v00000154a4316c30_0, 2, 1;
|
||||
L_00000154a4316a50 .part v00000154a4316370_0, 2, 1;
|
||||
L_00000154a43162d0 .concat8 [ 1 1 1 1], L_00000154a42aa8d0, L_00000154a42ab580, L_00000154a42ab660, L_00000154a42aad30;
|
||||
S_00000154a426d820 .scope module, "a0" "halfAdder" 3 8, 4 1 0, S_00000154a426ec30;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "S";
|
||||
.port_info 3 /OUTPUT 1 "C";
|
||||
L_00000154a42aa8d0 .functor XOR 1, L_00000154a4315fb0, L_00000154a4315b50, C4<0>, C4<0>;
|
||||
L_00000154a42aabe0 .functor AND 1, L_00000154a4315fb0, L_00000154a4315b50, C4<1>, C4<1>;
|
||||
v00000154a42aa140_0 .net "A", 0 0, L_00000154a4315fb0; 1 drivers
|
||||
v00000154a42a9c40_0 .net "B", 0 0, L_00000154a4315b50; 1 drivers
|
||||
v00000154a42aa000_0 .net "C", 0 0, L_00000154a42aabe0; alias, 1 drivers
|
||||
v00000154a42a9880_0 .net "S", 0 0, L_00000154a42aa8d0; 1 drivers
|
||||
S_00000154a426d9b0 .scope module, "a1" "fullAdder" 3 10, 5 1 0, S_00000154a426ec30;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "Z";
|
||||
.port_info 3 /OUTPUT 1 "S";
|
||||
.port_info 4 /OUTPUT 1 "C";
|
||||
L_00000154a42ab200 .functor OR 1, L_00000154a42aab70, L_00000154a42aa940, C4<0>, C4<0>;
|
||||
v00000154a42a99c0_0 .net "A", 0 0, L_00000154a4316190; 1 drivers
|
||||
v00000154a42aa6e0_0 .net "B", 0 0, L_00000154a4317590; 1 drivers
|
||||
v00000154a42aa320_0 .net "C", 0 0, L_00000154a42ab200; alias, 1 drivers
|
||||
v00000154a42aa500_0 .net "S", 0 0, L_00000154a42ab580; 1 drivers
|
||||
v00000154a42a9b00_0 .net "W0", 0 0, L_00000154a42ab510; 1 drivers
|
||||
v00000154a42aa640_0 .net "W1", 0 0, L_00000154a42aab70; 1 drivers
|
||||
v00000154a42a9d80_0 .net "W2", 0 0, L_00000154a42aa940; 1 drivers
|
||||
v00000154a42a9ec0_0 .net "Z", 0 0, L_00000154a42aabe0; alias, 1 drivers
|
||||
S_00000154a426c910 .scope module, "h0" "halfAdder" 5 7, 4 1 0, S_00000154a426d9b0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "S";
|
||||
.port_info 3 /OUTPUT 1 "C";
|
||||
L_00000154a42ab510 .functor XOR 1, L_00000154a4316190, L_00000154a4317590, C4<0>, C4<0>;
|
||||
L_00000154a42aab70 .functor AND 1, L_00000154a4316190, L_00000154a4317590, C4<1>, C4<1>;
|
||||
v00000154a42aa0a0_0 .net "A", 0 0, L_00000154a4316190; alias, 1 drivers
|
||||
v00000154a42a9a60_0 .net "B", 0 0, L_00000154a4317590; alias, 1 drivers
|
||||
v00000154a42aa1e0_0 .net "C", 0 0, L_00000154a42aab70; alias, 1 drivers
|
||||
v00000154a42aa280_0 .net "S", 0 0, L_00000154a42ab510; alias, 1 drivers
|
||||
S_00000154a426caa0 .scope module, "h1" "halfAdder" 5 8, 4 1 0, S_00000154a426d9b0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "S";
|
||||
.port_info 3 /OUTPUT 1 "C";
|
||||
L_00000154a42ab580 .functor XOR 1, L_00000154a42ab510, L_00000154a42aabe0, C4<0>, C4<0>;
|
||||
L_00000154a42aa940 .functor AND 1, L_00000154a42ab510, L_00000154a42aabe0, C4<1>, C4<1>;
|
||||
v00000154a42a97e0_0 .net "A", 0 0, L_00000154a42ab510; alias, 1 drivers
|
||||
v00000154a42a9ce0_0 .net "B", 0 0, L_00000154a42aabe0; alias, 1 drivers
|
||||
v00000154a42a9920_0 .net "C", 0 0, L_00000154a42aa940; alias, 1 drivers
|
||||
v00000154a42aa460_0 .net "S", 0 0, L_00000154a42ab580; alias, 1 drivers
|
||||
S_00000154a4282990 .scope module, "a2" "fullAdder" 3 11, 5 1 0, S_00000154a426ec30;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "Z";
|
||||
.port_info 3 /OUTPUT 1 "S";
|
||||
.port_info 4 /OUTPUT 1 "C";
|
||||
L_00000154a42aad30 .functor OR 1, L_00000154a42ab3c0, L_00000154a42aa9b0, C4<0>, C4<0>;
|
||||
v00000154a4316910_0 .net "A", 0 0, L_00000154a4317630; 1 drivers
|
||||
v00000154a43160f0_0 .net "B", 0 0, L_00000154a4316a50; 1 drivers
|
||||
v00000154a4317270_0 .net "C", 0 0, L_00000154a42aad30; 1 drivers
|
||||
v00000154a4316ff0_0 .net "S", 0 0, L_00000154a42ab660; 1 drivers
|
||||
v00000154a4316b90_0 .net "W0", 0 0, L_00000154a42ab350; 1 drivers
|
||||
v00000154a43171d0_0 .net "W1", 0 0, L_00000154a42ab3c0; 1 drivers
|
||||
v00000154a4317310_0 .net "W2", 0 0, L_00000154a42aa9b0; 1 drivers
|
||||
v00000154a43176d0_0 .net "Z", 0 0, L_00000154a42ab200; alias, 1 drivers
|
||||
S_00000154a4282b20 .scope module, "h0" "halfAdder" 5 7, 4 1 0, S_00000154a4282990;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "S";
|
||||
.port_info 3 /OUTPUT 1 "C";
|
||||
L_00000154a42ab350 .functor XOR 1, L_00000154a4317630, L_00000154a4316a50, C4<0>, C4<0>;
|
||||
L_00000154a42ab3c0 .functor AND 1, L_00000154a4317630, L_00000154a4316a50, C4<1>, C4<1>;
|
||||
v00000154a42a9e20_0 .net "A", 0 0, L_00000154a4317630; alias, 1 drivers
|
||||
v00000154a42aa5a0_0 .net "B", 0 0, L_00000154a4316a50; alias, 1 drivers
|
||||
v00000154a4316870_0 .net "C", 0 0, L_00000154a42ab3c0; alias, 1 drivers
|
||||
v00000154a4315c90_0 .net "S", 0 0, L_00000154a42ab350; alias, 1 drivers
|
||||
S_00000154a4282cb0 .scope module, "h1" "halfAdder" 5 8, 4 1 0, S_00000154a4282990;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "S";
|
||||
.port_info 3 /OUTPUT 1 "C";
|
||||
L_00000154a42ab660 .functor XOR 1, L_00000154a42ab350, L_00000154a42ab200, C4<0>, C4<0>;
|
||||
L_00000154a42aa9b0 .functor AND 1, L_00000154a42ab350, L_00000154a42ab200, C4<1>, C4<1>;
|
||||
v00000154a4315ab0_0 .net "A", 0 0, L_00000154a42ab350; alias, 1 drivers
|
||||
v00000154a4316730_0 .net "B", 0 0, L_00000154a42ab200; alias, 1 drivers
|
||||
v00000154a43169b0_0 .net "C", 0 0, L_00000154a42aa9b0; alias, 1 drivers
|
||||
v00000154a4317130_0 .net "S", 0 0, L_00000154a42ab660; alias, 1 drivers
|
||||
.scope S_00000154a426eaa0;
|
||||
T_0 ;
|
||||
%vpi_call 2 8 "$dumpfile", "dmp.vcd" {0 0 0};
|
||||
%vpi_call 2 9 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v00000154a4316c30_0, 0, 3;
|
||||
%pushi/vec4 7, 0, 3;
|
||||
%store/vec4 v00000154a4316370_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%store/vec4 v00000154a4316c30_0, 0, 3;
|
||||
%pushi/vec4 6, 0, 3;
|
||||
%store/vec4 v00000154a4316370_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%store/vec4 v00000154a4316c30_0, 0, 3;
|
||||
%pushi/vec4 5, 0, 3;
|
||||
%store/vec4 v00000154a4316370_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 3, 0, 3;
|
||||
%store/vec4 v00000154a4316c30_0, 0, 3;
|
||||
%pushi/vec4 4, 0, 3;
|
||||
%store/vec4 v00000154a4316370_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 4, 0, 3;
|
||||
%store/vec4 v00000154a4316c30_0, 0, 3;
|
||||
%pushi/vec4 3, 0, 3;
|
||||
%store/vec4 v00000154a4316370_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 5, 0, 3;
|
||||
%store/vec4 v00000154a4316c30_0, 0, 3;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%store/vec4 v00000154a4316370_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 6, 0, 3;
|
||||
%store/vec4 v00000154a4316c30_0, 0, 3;
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%store/vec4 v00000154a4316370_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 7, 0, 3;
|
||||
%store/vec4 v00000154a4316c30_0, 0, 3;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v00000154a4316370_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v00000154a4316c30_0, 0, 3;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v00000154a4316370_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%store/vec4 v00000154a4316c30_0, 0, 3;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v00000154a4316370_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%store/vec4 v00000154a4316c30_0, 0, 3;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v00000154a4316370_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 3, 0, 3;
|
||||
%store/vec4 v00000154a4316c30_0, 0, 3;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v00000154a4316370_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 4, 0, 3;
|
||||
%store/vec4 v00000154a4316c30_0, 0, 3;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v00000154a4316370_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 5, 0, 3;
|
||||
%store/vec4 v00000154a4316c30_0, 0, 3;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v00000154a4316370_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 6, 0, 3;
|
||||
%store/vec4 v00000154a4316c30_0, 0, 3;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v00000154a4316370_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 7, 0, 3;
|
||||
%store/vec4 v00000154a4316c30_0, 0, 3;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v00000154a4316370_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 6;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
".\tb.v";
|
||||
".\Adder3Bit.v";
|
||||
".\halfAdder.v";
|
||||
".\fullAdder.v";
|
142
iverilog/tobb/labs/lab3/src/3dmp.vcd
Normal file
142
iverilog/tobb/labs/lab3/src/3dmp.vcd
Normal file
@ -0,0 +1,142 @@
|
||||
$date
|
||||
Sat May 04 01:15:09 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module fullAdder $end
|
||||
$var wire 1 ! A $end
|
||||
$var wire 1 " B $end
|
||||
$var wire 1 # C $end
|
||||
$var wire 1 $ Z $end
|
||||
$var wire 1 % W2 $end
|
||||
$var wire 1 & W1 $end
|
||||
$var wire 1 ' W0 $end
|
||||
$var wire 1 ( S $end
|
||||
$scope module h0 $end
|
||||
$var wire 1 ! A $end
|
||||
$var wire 1 " B $end
|
||||
$var wire 1 & C $end
|
||||
$var wire 1 ' S $end
|
||||
$upscope $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 ' A $end
|
||||
$var wire 1 $ B $end
|
||||
$var wire 1 % C $end
|
||||
$var wire 1 ( S $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module mtb $end
|
||||
$var wire 4 ) C [3:0] $end
|
||||
$var reg 2 * A [1:0] $end
|
||||
$var reg 2 + B [1:0] $end
|
||||
$scope module uut $end
|
||||
$var wire 2 , A [1:0] $end
|
||||
$var wire 2 - B [1:0] $end
|
||||
$var wire 1 . c1 $end
|
||||
$var wire 1 / c2 $end
|
||||
$var wire 1 0 c5 $end
|
||||
$var wire 1 1 c4 $end
|
||||
$var wire 4 2 C [3:0] $end
|
||||
$scope module h0 $end
|
||||
$var wire 1 . A $end
|
||||
$var wire 1 / B $end
|
||||
$var wire 1 1 C $end
|
||||
$var wire 1 3 S $end
|
||||
$upscope $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 0 A $end
|
||||
$var wire 1 1 B $end
|
||||
$var wire 1 4 C $end
|
||||
$var wire 1 5 S $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$comment Show the parameter values. $end
|
||||
$dumpall
|
||||
$end
|
||||
#0
|
||||
$dumpvars
|
||||
05
|
||||
04
|
||||
03
|
||||
b0 2
|
||||
01
|
||||
00
|
||||
0/
|
||||
0.
|
||||
b11 -
|
||||
b0 ,
|
||||
b11 +
|
||||
b0 *
|
||||
b0 )
|
||||
x(
|
||||
x'
|
||||
x&
|
||||
x%
|
||||
z$
|
||||
x#
|
||||
z"
|
||||
z!
|
||||
$end
|
||||
#10
|
||||
b10 )
|
||||
b10 2
|
||||
13
|
||||
1/
|
||||
b10 +
|
||||
b10 -
|
||||
b1 *
|
||||
b1 ,
|
||||
#20
|
||||
1.
|
||||
0/
|
||||
b1 +
|
||||
b1 -
|
||||
b10 *
|
||||
b10 ,
|
||||
#30
|
||||
b0 )
|
||||
b0 2
|
||||
03
|
||||
0.
|
||||
b0 +
|
||||
b0 -
|
||||
b11 *
|
||||
b11 ,
|
||||
#40
|
||||
b0 *
|
||||
b0 ,
|
||||
#50
|
||||
b1 )
|
||||
b1 2
|
||||
b1 +
|
||||
b1 -
|
||||
b1 *
|
||||
b1 ,
|
||||
#60
|
||||
15
|
||||
10
|
||||
b1000 )
|
||||
b1000 2
|
||||
b10 +
|
||||
b10 -
|
||||
b10 *
|
||||
b10 ,
|
||||
#70
|
||||
05
|
||||
14
|
||||
11
|
||||
1.
|
||||
1/
|
||||
b101 )
|
||||
b101 2
|
||||
b11 +
|
||||
b11 -
|
||||
b11 *
|
||||
b11 ,
|
||||
#80
|
140
iverilog/tobb/labs/lab3/src/Adder3Bit
Normal file
140
iverilog/tobb/labs/lab3/src/Adder3Bit
Normal file
@ -0,0 +1,140 @@
|
||||
#! /c/Source/iverilog-install/bin/vvp
|
||||
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
|
||||
S_000001e07a11e640 .scope module, "tbAdder3Bit" "tbAdder3Bit" 2 1;
|
||||
.timescale 0 0;
|
||||
v000001e07a09f780_0 .var "r1", 2 0;
|
||||
v000001e07a09f5a0_0 .var "r2", 2 0;
|
||||
v000001e07a0a0d60_0 .net "w1", 2 0, L_000001e07a0a0ea0; 1 drivers
|
||||
v000001e07a0a0360_0 .net "w2", 2 0, L_000001e07a0a05e0; 1 drivers
|
||||
S_000001e07a11e7d0 .scope module, "uut" "Adder3Bit" 2 6, 3 1 0, S_000001e07a11e640;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 3 "num1";
|
||||
.port_info 1 /INPUT 3 "num2";
|
||||
.port_info 2 /OUTPUT 3 "Carry";
|
||||
.port_info 3 /OUTPUT 3 "sum";
|
||||
L_000001e07a118f90 .functor XOR 1, L_000001e07a09fdc0, L_000001e07a09f000, C4<0>, C4<0>;
|
||||
L_000001e07a1190e0 .functor AND 1, L_000001e07a0a0400, L_000001e07a0a0220, C4<1>, C4<1>;
|
||||
L_000001e07a119000 .functor XOR 1, L_000001e07a09fbe0, L_000001e07a0a0e00, C4<0>, C4<0>;
|
||||
L_000001e07a1191c0 .functor XOR 1, L_000001e07a119000, L_000001e07a09f8c0, C4<0>, C4<0>;
|
||||
L_000001e07a119310 .functor AND 1, L_000001e07a119000, L_000001e07a09f460, C4<1>, C4<1>;
|
||||
L_000001e07a119070 .functor AND 1, L_000001e07a09fa00, L_000001e07a0a09a0, C4<1>, C4<1>;
|
||||
L_000001e07a0a2d40 .functor OR 1, L_000001e07a119310, L_000001e07a119070, C4<0>, C4<0>;
|
||||
L_000001e07a0a25d0 .functor XOR 1, L_000001e07a09fc80, L_000001e07a0a0b80, C4<0>, C4<0>;
|
||||
L_000001e07a0a2bf0 .functor XOR 1, L_000001e07a0a25d0, L_000001e07a09faa0, C4<0>, C4<0>;
|
||||
L_000001e07a0a24f0 .functor AND 1, L_000001e07a0a25d0, L_000001e07a09f500, C4<1>, C4<1>;
|
||||
L_000001e07a0a2170 .functor AND 1, L_000001e07a09f280, L_000001e07a0a0540, C4<1>, C4<1>;
|
||||
L_000001e07a0a2640 .functor OR 1, L_000001e07a0a24f0, L_000001e07a0a2170, C4<0>, C4<0>;
|
||||
v000001e07a036150_0 .net "Carry", 2 0, L_000001e07a0a05e0; alias, 1 drivers
|
||||
v000001e07a035750_0 .net *"_ivl_1", 0 0, L_000001e07a118f90; 1 drivers
|
||||
v000001e07a0357f0_0 .net *"_ivl_11", 0 0, L_000001e07a0a0400; 1 drivers
|
||||
v000001e07a035d90_0 .net *"_ivl_13", 0 0, L_000001e07a0a0220; 1 drivers
|
||||
v000001e07a036470_0 .net *"_ivl_17", 0 0, L_000001e07a09fbe0; 1 drivers
|
||||
v000001e07a035ed0_0 .net *"_ivl_19", 0 0, L_000001e07a0a0e00; 1 drivers
|
||||
v000001e07a036510_0 .net *"_ivl_21", 0 0, L_000001e07a1191c0; 1 drivers
|
||||
v000001e07a036010_0 .net *"_ivl_25", 0 0, L_000001e07a09f8c0; 1 drivers
|
||||
v000001e07a035890_0 .net *"_ivl_30", 0 0, L_000001e07a09f460; 1 drivers
|
||||
v000001e07a0365b0_0 .net *"_ivl_34", 0 0, L_000001e07a09fa00; 1 drivers
|
||||
v000001e07a035930_0 .net *"_ivl_36", 0 0, L_000001e07a0a09a0; 1 drivers
|
||||
v000001e07a0a04a0_0 .net *"_ivl_38", 0 0, L_000001e07a0a2d40; 1 drivers
|
||||
v000001e07a0a0cc0_0 .net *"_ivl_4", 0 0, L_000001e07a09fdc0; 1 drivers
|
||||
v000001e07a09f1e0_0 .net *"_ivl_45", 0 0, L_000001e07a09fc80; 1 drivers
|
||||
v000001e07a09f140_0 .net *"_ivl_47", 0 0, L_000001e07a0a0b80; 1 drivers
|
||||
v000001e07a0a0a40_0 .net *"_ivl_49", 0 0, L_000001e07a0a2bf0; 1 drivers
|
||||
v000001e07a09f320_0 .net *"_ivl_54", 0 0, L_000001e07a09faa0; 1 drivers
|
||||
v000001e07a09fe60_0 .net *"_ivl_59", 0 0, L_000001e07a09f500; 1 drivers
|
||||
v000001e07a09f960_0 .net *"_ivl_6", 0 0, L_000001e07a09f000; 1 drivers
|
||||
v000001e07a09f820_0 .net *"_ivl_63", 0 0, L_000001e07a09f280; 1 drivers
|
||||
v000001e07a09f6e0_0 .net *"_ivl_65", 0 0, L_000001e07a0a0540; 1 drivers
|
||||
v000001e07a0a0040_0 .net *"_ivl_67", 0 0, L_000001e07a0a2640; 1 drivers
|
||||
v000001e07a09f0a0_0 .net *"_ivl_8", 0 0, L_000001e07a1190e0; 1 drivers
|
||||
v000001e07a09f640_0 .net "num1", 2 0, v000001e07a09f780_0; 1 drivers
|
||||
v000001e07a09f3c0 .array "num12", 0 1;
|
||||
v000001e07a09f3c0_0 .net v000001e07a09f3c0 0, 0 0, L_000001e07a119000; 1 drivers
|
||||
v000001e07a09f3c0_1 .net v000001e07a09f3c0 1, 0 0, L_000001e07a0a25d0; 1 drivers
|
||||
v000001e07a09ff00 .array "num12Carry", 0 1;
|
||||
v000001e07a09ff00_0 .net v000001e07a09ff00 0, 0 0, L_000001e07a119310; 1 drivers
|
||||
v000001e07a09ff00_1 .net v000001e07a09ff00 1, 0 0, L_000001e07a0a24f0; 1 drivers
|
||||
v000001e07a0a0900 .array "num1a2", 0 1;
|
||||
v000001e07a0a0900_0 .net v000001e07a0a0900 0, 0 0, L_000001e07a119070; 1 drivers
|
||||
v000001e07a0a0900_1 .net v000001e07a0a0900 1, 0 0, L_000001e07a0a2170; 1 drivers
|
||||
v000001e07a09fb40_0 .net "num2", 2 0, v000001e07a09f5a0_0; 1 drivers
|
||||
v000001e07a09fd20_0 .net "sum", 2 0, L_000001e07a0a0ea0; alias, 1 drivers
|
||||
L_000001e07a09fdc0 .part v000001e07a09f780_0, 0, 1;
|
||||
L_000001e07a09f000 .part v000001e07a09f5a0_0, 0, 1;
|
||||
L_000001e07a0a0400 .part v000001e07a09f780_0, 0, 1;
|
||||
L_000001e07a0a0220 .part v000001e07a09f5a0_0, 0, 1;
|
||||
L_000001e07a09fbe0 .part v000001e07a09f780_0, 1, 1;
|
||||
L_000001e07a0a0e00 .part v000001e07a09f5a0_0, 1, 1;
|
||||
L_000001e07a09f8c0 .part L_000001e07a0a05e0, 0, 1;
|
||||
L_000001e07a09f460 .part L_000001e07a0a05e0, 0, 1;
|
||||
L_000001e07a09fa00 .part v000001e07a09f780_0, 1, 1;
|
||||
L_000001e07a0a09a0 .part v000001e07a09f5a0_0, 1, 1;
|
||||
L_000001e07a09fc80 .part v000001e07a09f780_0, 2, 1;
|
||||
L_000001e07a0a0b80 .part v000001e07a09f5a0_0, 2, 1;
|
||||
L_000001e07a0a0ea0 .concat8 [ 1 1 1 0], L_000001e07a118f90, L_000001e07a1191c0, L_000001e07a0a2bf0;
|
||||
L_000001e07a09faa0 .part L_000001e07a0a05e0, 1, 1;
|
||||
L_000001e07a09f500 .part L_000001e07a0a05e0, 1, 1;
|
||||
L_000001e07a09f280 .part v000001e07a09f780_0, 2, 1;
|
||||
L_000001e07a0a0540 .part v000001e07a09f5a0_0, 2, 1;
|
||||
L_000001e07a0a05e0 .concat8 [ 1 1 1 0], L_000001e07a1190e0, L_000001e07a0a2d40, L_000001e07a0a2640;
|
||||
.scope S_000001e07a11e640;
|
||||
T_0 ;
|
||||
%vpi_call 2 14 "$dumpfile", "Admp.vcd" {0 0 0};
|
||||
%vpi_call 2 15 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v000001e07a09f780_0, 0, 3;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v000001e07a09f5a0_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%store/vec4 v000001e07a09f780_0, 0, 3;
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%store/vec4 v000001e07a09f5a0_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%store/vec4 v000001e07a09f780_0, 0, 3;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%store/vec4 v000001e07a09f5a0_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 4, 0, 3;
|
||||
%store/vec4 v000001e07a09f780_0, 0, 3;
|
||||
%pushi/vec4 4, 0, 3;
|
||||
%store/vec4 v000001e07a09f5a0_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 3, 0, 3;
|
||||
%store/vec4 v000001e07a09f780_0, 0, 3;
|
||||
%pushi/vec4 3, 0, 3;
|
||||
%store/vec4 v000001e07a09f5a0_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 5, 0, 3;
|
||||
%store/vec4 v000001e07a09f780_0, 0, 3;
|
||||
%pushi/vec4 5, 0, 3;
|
||||
%store/vec4 v000001e07a09f5a0_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 6, 0, 3;
|
||||
%store/vec4 v000001e07a09f780_0, 0, 3;
|
||||
%pushi/vec4 6, 0, 3;
|
||||
%store/vec4 v000001e07a09f5a0_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 7, 0, 3;
|
||||
%store/vec4 v000001e07a09f780_0, 0, 3;
|
||||
%pushi/vec4 7, 0, 3;
|
||||
%store/vec4 v000001e07a09f5a0_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%vpi_call 2 24 "$display", v000001e07a0a0d60_0 {0 0 0};
|
||||
%vpi_call 2 25 "$display", v000001e07a0a0360_0 {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
".\tbAdder3Bit.v";
|
||||
".\Adder3Bit.v";
|
15
iverilog/tobb/labs/lab3/src/Adder3Bit.v
Normal file
15
iverilog/tobb/labs/lab3/src/Adder3Bit.v
Normal file
@ -0,0 +1,15 @@
|
||||
module Adder3Bit (
|
||||
input [2:0] A,
|
||||
input [2:0] B,
|
||||
output [3:0] C
|
||||
);
|
||||
|
||||
wire c1, c2;
|
||||
halfAdder a0(A[0], B[0], C[0], c1);
|
||||
|
||||
fullAdder a1(A[1], B[1], c1, C[1], c2);
|
||||
fullAdder a2(A[2], B[2], c2, C[2], C[3]);
|
||||
|
||||
|
||||
|
||||
endmodule
|
100
iverilog/tobb/labs/lab3/src/Admp.vcd
Normal file
100
iverilog/tobb/labs/lab3/src/Admp.vcd
Normal file
@ -0,0 +1,100 @@
|
||||
$date
|
||||
Sat Apr 13 14:50:50 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module tbAdder3Bit $end
|
||||
$var wire 3 ! w2 [2:0] $end
|
||||
$var wire 3 " w1 [2:0] $end
|
||||
$var reg 3 # r1 [2:0] $end
|
||||
$var reg 3 $ r2 [2:0] $end
|
||||
$scope module uut $end
|
||||
$var wire 3 % num1 [2:0] $end
|
||||
$var wire 3 & num2 [2:0] $end
|
||||
$var wire 3 ' sum [2:0] $end
|
||||
$var wire 3 ( Carry [2:0] $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$comment Show the parameter values. $end
|
||||
$dumpall
|
||||
$end
|
||||
#0
|
||||
$dumpvars
|
||||
b0 (
|
||||
b0 '
|
||||
b0 &
|
||||
b0 %
|
||||
b0 $
|
||||
b0 #
|
||||
b0 "
|
||||
b0 !
|
||||
$end
|
||||
#10
|
||||
b10 "
|
||||
b10 '
|
||||
b1 !
|
||||
b1 (
|
||||
b1 $
|
||||
b1 &
|
||||
b1 #
|
||||
b1 %
|
||||
#20
|
||||
b100 "
|
||||
b100 '
|
||||
b10 !
|
||||
b10 (
|
||||
b10 $
|
||||
b10 &
|
||||
b10 #
|
||||
b10 %
|
||||
#30
|
||||
b0 "
|
||||
b0 '
|
||||
b100 !
|
||||
b100 (
|
||||
b100 $
|
||||
b100 &
|
||||
b100 #
|
||||
b100 %
|
||||
#40
|
||||
b110 "
|
||||
b110 '
|
||||
b11 !
|
||||
b11 (
|
||||
b11 $
|
||||
b11 &
|
||||
b11 #
|
||||
b11 %
|
||||
#50
|
||||
b10 "
|
||||
b10 '
|
||||
b101 !
|
||||
b101 (
|
||||
b101 $
|
||||
b101 &
|
||||
b101 #
|
||||
b101 %
|
||||
#60
|
||||
b100 "
|
||||
b100 '
|
||||
b110 !
|
||||
b110 (
|
||||
b110 $
|
||||
b110 &
|
||||
b110 #
|
||||
b110 %
|
||||
#70
|
||||
b110 "
|
||||
b110 '
|
||||
b111 !
|
||||
b111 (
|
||||
b111 $
|
||||
b111 &
|
||||
b111 #
|
||||
b111 %
|
||||
#80
|
234
iverilog/tobb/labs/lab3/src/dmp.vcd
Normal file
234
iverilog/tobb/labs/lab3/src/dmp.vcd
Normal file
@ -0,0 +1,234 @@
|
||||
$date
|
||||
Fri May 03 11:28:11 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module tb $end
|
||||
$var wire 4 ! C [3:0] $end
|
||||
$var reg 3 " A [2:0] $end
|
||||
$var reg 3 # B [2:0] $end
|
||||
$scope module uut $end
|
||||
$var wire 3 $ A [2:0] $end
|
||||
$var wire 3 % B [2:0] $end
|
||||
$var wire 1 & c2 $end
|
||||
$var wire 1 ' c1 $end
|
||||
$var wire 4 ( C [3:0] $end
|
||||
$scope module a0 $end
|
||||
$var wire 1 ) A $end
|
||||
$var wire 1 * B $end
|
||||
$var wire 1 ' C $end
|
||||
$var wire 1 + S $end
|
||||
$upscope $end
|
||||
$scope module a1 $end
|
||||
$var wire 1 , A $end
|
||||
$var wire 1 - B $end
|
||||
$var wire 1 & C $end
|
||||
$var wire 1 ' Z $end
|
||||
$var wire 1 . W2 $end
|
||||
$var wire 1 / W1 $end
|
||||
$var wire 1 0 W0 $end
|
||||
$var wire 1 1 S $end
|
||||
$scope module h0 $end
|
||||
$var wire 1 , A $end
|
||||
$var wire 1 - B $end
|
||||
$var wire 1 / C $end
|
||||
$var wire 1 0 S $end
|
||||
$upscope $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 0 A $end
|
||||
$var wire 1 ' B $end
|
||||
$var wire 1 . C $end
|
||||
$var wire 1 1 S $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module a2 $end
|
||||
$var wire 1 2 A $end
|
||||
$var wire 1 3 B $end
|
||||
$var wire 1 4 C $end
|
||||
$var wire 1 & Z $end
|
||||
$var wire 1 5 W2 $end
|
||||
$var wire 1 6 W1 $end
|
||||
$var wire 1 7 W0 $end
|
||||
$var wire 1 8 S $end
|
||||
$scope module h0 $end
|
||||
$var wire 1 2 A $end
|
||||
$var wire 1 3 B $end
|
||||
$var wire 1 6 C $end
|
||||
$var wire 1 7 S $end
|
||||
$upscope $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 7 A $end
|
||||
$var wire 1 & B $end
|
||||
$var wire 1 5 C $end
|
||||
$var wire 1 8 S $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$comment Show the parameter values. $end
|
||||
$dumpall
|
||||
$end
|
||||
#0
|
||||
$dumpvars
|
||||
18
|
||||
17
|
||||
06
|
||||
05
|
||||
04
|
||||
13
|
||||
02
|
||||
11
|
||||
10
|
||||
0/
|
||||
0.
|
||||
1-
|
||||
0,
|
||||
1+
|
||||
1*
|
||||
0)
|
||||
b111 (
|
||||
0'
|
||||
0&
|
||||
b111 %
|
||||
b0 $
|
||||
b111 #
|
||||
b0 "
|
||||
b111 !
|
||||
$end
|
||||
#10
|
||||
0*
|
||||
1)
|
||||
b110 #
|
||||
b110 %
|
||||
b1 "
|
||||
b1 $
|
||||
#20
|
||||
1*
|
||||
0-
|
||||
0)
|
||||
1,
|
||||
b101 #
|
||||
b101 %
|
||||
b10 "
|
||||
b10 $
|
||||
#30
|
||||
0*
|
||||
1)
|
||||
b100 #
|
||||
b100 %
|
||||
b11 "
|
||||
b11 $
|
||||
#40
|
||||
1*
|
||||
1-
|
||||
03
|
||||
0)
|
||||
0,
|
||||
12
|
||||
b11 #
|
||||
b11 %
|
||||
b100 "
|
||||
b100 $
|
||||
#50
|
||||
0*
|
||||
1)
|
||||
b10 #
|
||||
b10 %
|
||||
b101 "
|
||||
b101 $
|
||||
#60
|
||||
1*
|
||||
0-
|
||||
0)
|
||||
1,
|
||||
b1 #
|
||||
b1 %
|
||||
b110 "
|
||||
b110 $
|
||||
#70
|
||||
0*
|
||||
1)
|
||||
b0 #
|
||||
b0 %
|
||||
b111 "
|
||||
b111 $
|
||||
#80
|
||||
01
|
||||
08
|
||||
b0 !
|
||||
b0 (
|
||||
0+
|
||||
00
|
||||
07
|
||||
0)
|
||||
0,
|
||||
02
|
||||
b0 "
|
||||
b0 $
|
||||
#90
|
||||
b1 !
|
||||
b1 (
|
||||
1+
|
||||
1)
|
||||
b1 "
|
||||
b1 $
|
||||
#100
|
||||
11
|
||||
b10 !
|
||||
b10 (
|
||||
0+
|
||||
10
|
||||
0)
|
||||
1,
|
||||
b10 "
|
||||
b10 $
|
||||
#110
|
||||
b11 !
|
||||
b11 (
|
||||
1+
|
||||
1)
|
||||
b11 "
|
||||
b11 $
|
||||
#120
|
||||
01
|
||||
18
|
||||
b100 !
|
||||
b100 (
|
||||
0+
|
||||
00
|
||||
17
|
||||
0)
|
||||
0,
|
||||
12
|
||||
b100 "
|
||||
b100 $
|
||||
#130
|
||||
b101 !
|
||||
b101 (
|
||||
1+
|
||||
1)
|
||||
b101 "
|
||||
b101 $
|
||||
#140
|
||||
11
|
||||
b110 !
|
||||
b110 (
|
||||
0+
|
||||
10
|
||||
0)
|
||||
1,
|
||||
b110 "
|
||||
b110 $
|
||||
#150
|
||||
b111 !
|
||||
b111 (
|
||||
1+
|
||||
1)
|
||||
b111 "
|
||||
b111 $
|
||||
#160
|
12
iverilog/tobb/labs/lab3/src/fullAdder.v
Normal file
12
iverilog/tobb/labs/lab3/src/fullAdder.v
Normal file
@ -0,0 +1,12 @@
|
||||
module fullAdder(
|
||||
input A, B, Z,
|
||||
output S, C
|
||||
);
|
||||
wire W0, W1, W2;
|
||||
|
||||
halfAdder h0(A, B, W0, W1);
|
||||
halfAdder h1(W0, Z, S, W2);
|
||||
|
||||
or(C, W1, W2);
|
||||
|
||||
endmodule
|
9
iverilog/tobb/labs/lab3/src/halfAdder.v
Normal file
9
iverilog/tobb/labs/lab3/src/halfAdder.v
Normal file
@ -0,0 +1,9 @@
|
||||
module halfAdder(
|
||||
input A, B,
|
||||
output S, C
|
||||
);
|
||||
|
||||
xor(S, A, B);
|
||||
and(C, A, B);
|
||||
|
||||
endmodule
|
23
iverilog/tobb/labs/lab3/src/mtb.v
Normal file
23
iverilog/tobb/labs/lab3/src/mtb.v
Normal file
@ -0,0 +1,23 @@
|
||||
module mtb();
|
||||
|
||||
reg[1:0] A, B;
|
||||
wire [3:0] C;
|
||||
mult2bit uut(A,B,C);
|
||||
|
||||
initial begin
|
||||
$dumpfile("3dmp.vcd");
|
||||
$dumpvars;
|
||||
|
||||
A = 2'd0; B = 2'd3; #10;
|
||||
A = 2'd1; B = 2'd2; #10;
|
||||
A = 2'd2; B = 2'd1; #10;
|
||||
A = 2'd3; B = 2'd0; #10;
|
||||
|
||||
A = 2'd0; B = 2'd0; #10;
|
||||
A = 2'd1; B = 2'd1; #10;
|
||||
A = 2'd2; B = 2'd2; #10;
|
||||
A = 2'd3; B = 2'd3; #10;
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
169
iverilog/tobb/labs/lab3/src/mult2
Normal file
169
iverilog/tobb/labs/lab3/src/mult2
Normal file
@ -0,0 +1,169 @@
|
||||
#! /c/Source/iverilog-install/bin/vvp
|
||||
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
|
||||
S_0000025ecd40d010 .scope module, "fullAdder" "fullAdder" 2 1;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "Z";
|
||||
.port_info 3 /OUTPUT 1 "S";
|
||||
.port_info 4 /OUTPUT 1 "C";
|
||||
L_0000025ecd257f60 .functor OR 1, L_0000025ecd258660, L_0000025ecd2585f0, C4<0>, C4<0>;
|
||||
o0000025ecd26dfb8 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
v0000025ecd25a670_0 .net "A", 0 0, o0000025ecd26dfb8; 0 drivers
|
||||
o0000025ecd26dfe8 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
v0000025ecd25ae90_0 .net "B", 0 0, o0000025ecd26dfe8; 0 drivers
|
||||
v0000025ecd25a710_0 .net "C", 0 0, L_0000025ecd257f60; 1 drivers
|
||||
v0000025ecd25a8f0_0 .net "S", 0 0, L_0000025ecd258580; 1 drivers
|
||||
v0000025ecd25afd0_0 .net "W0", 0 0, L_0000025ecd2584a0; 1 drivers
|
||||
v0000025ecd25a990_0 .net "W1", 0 0, L_0000025ecd258660; 1 drivers
|
||||
v0000025ecd25aa30_0 .net "W2", 0 0, L_0000025ecd2585f0; 1 drivers
|
||||
o0000025ecd26e138 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
v0000025ecd25b070_0 .net "Z", 0 0, o0000025ecd26e138; 0 drivers
|
||||
S_0000025ecd40e9d0 .scope module, "h0" "halfAdder" 2 7, 3 1 0, S_0000025ecd40d010;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "S";
|
||||
.port_info 3 /OUTPUT 1 "C";
|
||||
L_0000025ecd2584a0 .functor XOR 1, o0000025ecd26dfb8, o0000025ecd26dfe8, C4<0>, C4<0>;
|
||||
L_0000025ecd258660 .functor AND 1, o0000025ecd26dfb8, o0000025ecd26dfe8, C4<1>, C4<1>;
|
||||
v0000025ecd25a530_0 .net "A", 0 0, o0000025ecd26dfb8; alias, 0 drivers
|
||||
v0000025ecd25adf0_0 .net "B", 0 0, o0000025ecd26dfe8; alias, 0 drivers
|
||||
v0000025ecd25a5d0_0 .net "C", 0 0, L_0000025ecd258660; alias, 1 drivers
|
||||
v0000025ecd25b2f0_0 .net "S", 0 0, L_0000025ecd2584a0; alias, 1 drivers
|
||||
S_0000025ecd40eb60 .scope module, "h1" "halfAdder" 2 8, 3 1 0, S_0000025ecd40d010;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "S";
|
||||
.port_info 3 /OUTPUT 1 "C";
|
||||
L_0000025ecd258580 .functor XOR 1, L_0000025ecd2584a0, o0000025ecd26e138, C4<0>, C4<0>;
|
||||
L_0000025ecd2585f0 .functor AND 1, L_0000025ecd2584a0, o0000025ecd26e138, C4<1>, C4<1>;
|
||||
v0000025ecd25b110_0 .net "A", 0 0, L_0000025ecd2584a0; alias, 1 drivers
|
||||
v0000025ecd25a850_0 .net "B", 0 0, o0000025ecd26e138; alias, 0 drivers
|
||||
v0000025ecd25b1b0_0 .net "C", 0 0, L_0000025ecd2585f0; alias, 1 drivers
|
||||
v0000025ecd25a3f0_0 .net "S", 0 0, L_0000025ecd258580; alias, 1 drivers
|
||||
S_0000025ecd40d1a0 .scope module, "mtb" "mtb" 4 1;
|
||||
.timescale 0 0;
|
||||
v0000025ecd2c1fb0_0 .var "A", 1 0;
|
||||
v0000025ecd2c1bf0_0 .var "B", 1 0;
|
||||
v0000025ecd2c1f10_0 .net "C", 3 0, L_0000025ecd2c0f70; 1 drivers
|
||||
S_0000025ecd26aae0 .scope module, "uut" "mult2bit" 4 5, 5 1 0, S_0000025ecd40d1a0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 2 "A";
|
||||
.port_info 1 /INPUT 2 "B";
|
||||
.port_info 2 /OUTPUT 4 "C";
|
||||
L_0000025ecd257fd0 .functor AND 1, L_0000025ecd2c1dd0, L_0000025ecd2c0ed0, C4<1>, C4<1>;
|
||||
L_0000025ecd2c2a60 .functor AND 1, L_0000025ecd2c2230, L_0000025ecd2c0890, C4<1>, C4<1>;
|
||||
L_0000025ecd2c2de0 .functor AND 1, L_0000025ecd2c0b10, L_0000025ecd2c22d0, C4<1>, C4<1>;
|
||||
L_0000025ecd2c28a0 .functor AND 1, L_0000025ecd2c2410, L_0000025ecd2c24b0, C4<1>, C4<1>;
|
||||
v0000025ecd2c15b0_0 .net "A", 1 0, v0000025ecd2c1fb0_0; 1 drivers
|
||||
v0000025ecd2c1d30_0 .net "B", 1 0, v0000025ecd2c1bf0_0; 1 drivers
|
||||
v0000025ecd2c0bb0_0 .net "C", 3 0, L_0000025ecd2c0f70; alias, 1 drivers
|
||||
v0000025ecd2c1e70_0 .net *"_ivl_1", 0 0, L_0000025ecd2c1dd0; 1 drivers
|
||||
v0000025ecd2c1830_0 .net *"_ivl_11", 0 0, L_0000025ecd2c22d0; 1 drivers
|
||||
v0000025ecd2c0c50_0 .net *"_ivl_12", 0 0, L_0000025ecd2c28a0; 1 drivers
|
||||
v0000025ecd2c2370_0 .net *"_ivl_15", 0 0, L_0000025ecd2c2410; 1 drivers
|
||||
v0000025ecd2c18d0_0 .net *"_ivl_17", 0 0, L_0000025ecd2c24b0; 1 drivers
|
||||
v0000025ecd2c2690_0 .net *"_ivl_3", 0 0, L_0000025ecd2c0ed0; 1 drivers
|
||||
v0000025ecd2c0a70_0 .net *"_ivl_5", 0 0, L_0000025ecd2c2230; 1 drivers
|
||||
v0000025ecd2c0cf0_0 .net *"_ivl_7", 0 0, L_0000025ecd2c0890; 1 drivers
|
||||
v0000025ecd2c1c90_0 .net *"_ivl_9", 0 0, L_0000025ecd2c0b10; 1 drivers
|
||||
v0000025ecd2c1470_0 .net "c1", 0 0, L_0000025ecd257fd0; 1 drivers
|
||||
v0000025ecd2c2190_0 .net "c2", 0 0, L_0000025ecd2c2a60; 1 drivers
|
||||
v0000025ecd2c1650_0 .net "c4", 0 0, L_0000025ecd2c2f30; 1 drivers
|
||||
v0000025ecd2c0d90_0 .net "c5", 0 0, L_0000025ecd2c2de0; 1 drivers
|
||||
L_0000025ecd2c1dd0 .part v0000025ecd2c1fb0_0, 1, 1;
|
||||
L_0000025ecd2c0ed0 .part v0000025ecd2c1bf0_0, 0, 1;
|
||||
L_0000025ecd2c2230 .part v0000025ecd2c1fb0_0, 0, 1;
|
||||
L_0000025ecd2c0890 .part v0000025ecd2c1bf0_0, 1, 1;
|
||||
L_0000025ecd2c0b10 .part v0000025ecd2c1fb0_0, 1, 1;
|
||||
L_0000025ecd2c22d0 .part v0000025ecd2c1bf0_0, 1, 1;
|
||||
L_0000025ecd2c2410 .part v0000025ecd2c1fb0_0, 0, 1;
|
||||
L_0000025ecd2c24b0 .part v0000025ecd2c1bf0_0, 0, 1;
|
||||
L_0000025ecd2c0f70 .concat8 [ 1 1 1 1], L_0000025ecd2c28a0, L_0000025ecd2c35c0, L_0000025ecd2c2fa0, L_0000025ecd2c32b0;
|
||||
S_0000025ecd26ac70 .scope module, "h0" "halfAdder" 5 14, 3 1 0, S_0000025ecd26aae0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "S";
|
||||
.port_info 3 /OUTPUT 1 "C";
|
||||
L_0000025ecd2c35c0 .functor XOR 1, L_0000025ecd257fd0, L_0000025ecd2c2a60, C4<0>, C4<0>;
|
||||
L_0000025ecd2c2f30 .functor AND 1, L_0000025ecd257fd0, L_0000025ecd2c2a60, C4<1>, C4<1>;
|
||||
v0000025ecd25ab70_0 .net "A", 0 0, L_0000025ecd257fd0; alias, 1 drivers
|
||||
v0000025ecd25acb0_0 .net "B", 0 0, L_0000025ecd2c2a60; alias, 1 drivers
|
||||
v0000025ecd25ad50_0 .net "C", 0 0, L_0000025ecd2c2f30; alias, 1 drivers
|
||||
v0000025ecd25af30_0 .net "S", 0 0, L_0000025ecd2c35c0; 1 drivers
|
||||
S_0000025ecd232990 .scope module, "h1" "halfAdder" 5 15, 3 1 0, S_0000025ecd26aae0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "S";
|
||||
.port_info 3 /OUTPUT 1 "C";
|
||||
L_0000025ecd2c32b0 .functor XOR 1, L_0000025ecd2c2de0, L_0000025ecd2c2f30, C4<0>, C4<0>;
|
||||
L_0000025ecd2c2fa0 .functor AND 1, L_0000025ecd2c2de0, L_0000025ecd2c2f30, C4<1>, C4<1>;
|
||||
v0000025ecd2c25f0_0 .net "A", 0 0, L_0000025ecd2c2de0; alias, 1 drivers
|
||||
v0000025ecd2c1330_0 .net "B", 0 0, L_0000025ecd2c2f30; alias, 1 drivers
|
||||
v0000025ecd2c09d0_0 .net "C", 0 0, L_0000025ecd2c2fa0; 1 drivers
|
||||
v0000025ecd2c1b50_0 .net "S", 0 0, L_0000025ecd2c32b0; 1 drivers
|
||||
.scope S_0000025ecd40d1a0;
|
||||
T_0 ;
|
||||
%vpi_call 4 8 "$dumpfile", "3dmp.vcd" {0 0 0};
|
||||
%vpi_call 4 9 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1fb0_0, 0, 2;
|
||||
%pushi/vec4 3, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1bf0_0, 0, 2;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1fb0_0, 0, 2;
|
||||
%pushi/vec4 2, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1bf0_0, 0, 2;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 2, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1fb0_0, 0, 2;
|
||||
%pushi/vec4 1, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1bf0_0, 0, 2;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 3, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1fb0_0, 0, 2;
|
||||
%pushi/vec4 0, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1bf0_0, 0, 2;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1fb0_0, 0, 2;
|
||||
%pushi/vec4 0, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1bf0_0, 0, 2;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1fb0_0, 0, 2;
|
||||
%pushi/vec4 1, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1bf0_0, 0, 2;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 2, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1fb0_0, 0, 2;
|
||||
%pushi/vec4 2, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1bf0_0, 0, 2;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 3, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1fb0_0, 0, 2;
|
||||
%pushi/vec4 3, 0, 2;
|
||||
%store/vec4 v0000025ecd2c1bf0_0, 0, 2;
|
||||
%delay 10, 0;
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 6;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
".\fullAdder.v";
|
||||
".\halfAdder.v";
|
||||
".\mtb.v";
|
||||
".\mult2bit.v";
|
17
iverilog/tobb/labs/lab3/src/mult2bit.v
Normal file
17
iverilog/tobb/labs/lab3/src/mult2bit.v
Normal file
@ -0,0 +1,17 @@
|
||||
module mult2bit (
|
||||
input [1:0] A,
|
||||
input [1:0] B,
|
||||
output [3:0] C
|
||||
);
|
||||
|
||||
wire c1, c2, c4, c5;
|
||||
|
||||
and a0(c1, A[1], B[0]);
|
||||
and a1(c2, A[0], B[1]);
|
||||
and a2(c5, A[1], B[1]);
|
||||
and a3(C[0], A[0], B[0]);
|
||||
|
||||
halfAdder h0(c1, c2, C[1], c4);
|
||||
halfAdder h1(c5, c4, C[3], C[2]);
|
||||
|
||||
endmodule
|
31
iverilog/tobb/labs/lab3/src/tb.v
Normal file
31
iverilog/tobb/labs/lab3/src/tb.v
Normal file
@ -0,0 +1,31 @@
|
||||
module tb();
|
||||
|
||||
reg [2:0] A, B;
|
||||
wire [3:0] C;
|
||||
Adder3Bit uut(A, B, C);
|
||||
|
||||
initial begin
|
||||
$dumpfile("dmp.vcd");
|
||||
$dumpvars;
|
||||
|
||||
A = 3'd0; B = 3'd7; #10;
|
||||
A = 3'd1; B = 3'd6; #10;
|
||||
A = 3'd2; B = 3'd5; #10;
|
||||
A = 3'd3; B = 3'd4; #10;
|
||||
A = 3'd4; B = 3'd3; #10;
|
||||
A = 3'd5; B = 3'd2; #10;
|
||||
A = 3'd6; B = 3'd1; #10;
|
||||
A = 3'd7; B = 3'd0; #10;
|
||||
|
||||
A = 3'd0; B = 3'd0; #10;
|
||||
A = 3'd1; B = 3'd0; #10;
|
||||
A = 3'd2; B = 3'd0; #10;
|
||||
A = 3'd3; B = 3'd0; #10;
|
||||
A = 3'd4; B = 3'd0; #10;
|
||||
A = 3'd5; B = 3'd0; #10;
|
||||
A = 3'd6; B = 3'd0; #10;
|
||||
A = 3'd7; B = 3'd0; #10;
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
13
iverilog/tobb/labs/lab3_solution/adder3bit.v
Normal file
13
iverilog/tobb/labs/lab3_solution/adder3bit.v
Normal file
@ -0,0 +1,13 @@
|
||||
module adder3bit(
|
||||
input [2:0] A,
|
||||
input [2:0] B,
|
||||
output [3:0] C
|
||||
);
|
||||
|
||||
|
||||
wire c1, c2, c3, c4;
|
||||
ha a0(A[0], B[0], C[0], c1);
|
||||
fa a1(A[1], B[1], c1, C[1], c2);
|
||||
fa a2(A[2], B[2], c2, C[2], C[3]);
|
||||
|
||||
endmodule
|
12
iverilog/tobb/labs/lab3_solution/fa.v
Normal file
12
iverilog/tobb/labs/lab3_solution/fa.v
Normal file
@ -0,0 +1,12 @@
|
||||
module fa(
|
||||
input X, Y, Z,
|
||||
output S, C
|
||||
);
|
||||
|
||||
wire W0, W1, W2;
|
||||
|
||||
ha h0(X, Y, W0, W1);
|
||||
ha h1(W0, Z, S, W2);
|
||||
or(C, W1, W2);
|
||||
|
||||
endmodule
|
9
iverilog/tobb/labs/lab3_solution/ha.v
Normal file
9
iverilog/tobb/labs/lab3_solution/ha.v
Normal file
@ -0,0 +1,9 @@
|
||||
module ha(
|
||||
input X, Y,
|
||||
output S, C
|
||||
);
|
||||
|
||||
xor(S, X, Y);
|
||||
and(C, X, Y);
|
||||
|
||||
endmodule
|
3
iverilog/tobb/labs/lab3_solution/run.sh
Normal file
3
iverilog/tobb/labs/lab3_solution/run.sh
Normal file
@ -0,0 +1,3 @@
|
||||
iverilog *.v &&
|
||||
vvp a.out &&
|
||||
gtkwave dmp.vcd
|
31
iverilog/tobb/labs/lab3_solution/tb.v
Normal file
31
iverilog/tobb/labs/lab3_solution/tb.v
Normal file
@ -0,0 +1,31 @@
|
||||
module tb();
|
||||
|
||||
reg [2:0] A, B;
|
||||
wire [3:0] C;
|
||||
adder3bit uut(A, B, C);
|
||||
|
||||
initial begin
|
||||
$dumpfile("dmp.vcd");
|
||||
$dumpvars;
|
||||
|
||||
A = 3'd0; B = 3'd7; #10;
|
||||
A = 3'd1; B = 3'd6; #10;
|
||||
A = 3'd2; B = 3'd5; #10;
|
||||
A = 3'd3; B = 3'd4; #10;
|
||||
A = 3'd4; B = 3'd3; #10;
|
||||
A = 3'd5; B = 3'd2; #10;
|
||||
A = 3'd6; B = 3'd1; #10;
|
||||
A = 3'd7; B = 3'd0; #10;
|
||||
|
||||
A = 3'd0; B = 3'd0; #10;
|
||||
A = 3'd1; B = 3'd0; #10;
|
||||
A = 3'd2; B = 3'd0; #10;
|
||||
A = 3'd3; B = 3'd0; #10;
|
||||
A = 3'd4; B = 3'd0; #10;
|
||||
A = 3'd5; B = 3'd0; #10;
|
||||
A = 3'd6; B = 3'd0; #10;
|
||||
A = 3'd7; B = 3'd0; #10;
|
||||
|
||||
end
|
||||
|
||||
endmodule
|
22
iverilog/tobb/labs/lab4/lab4.v
Normal file
22
iverilog/tobb/labs/lab4/lab4.v
Normal file
@ -0,0 +1,22 @@
|
||||
module lab4(
|
||||
input [8:0] signal,
|
||||
output reg [3:0] S
|
||||
);
|
||||
|
||||
always@(*) begin
|
||||
S = 4'b0000;
|
||||
if (signal[8] == 1) begin //First most significant bit -> sum
|
||||
S = signal[5:3] + signal[2:0];
|
||||
end
|
||||
else if (signal[7] == 1) begin
|
||||
S = signal[5:3] - signal [2:0];
|
||||
end
|
||||
else if (signal[6] == 1) begin
|
||||
S = signal[5:3] & signal [2:0];
|
||||
end
|
||||
else if (signal[6] == 0) begin
|
||||
S = signal[5:3] | signal [2:0];
|
||||
end
|
||||
|
||||
end
|
||||
endmodule
|
114
iverilog/tobb/labs/lab4/lab4o
Normal file
114
iverilog/tobb/labs/lab4/lab4o
Normal file
@ -0,0 +1,114 @@
|
||||
#! /usr/bin/vvp
|
||||
:ivl_version "11.0 (stable)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
|
||||
S_0x55d6490fdb70 .scope module, "lab4tb" "lab4tb" 2 1;
|
||||
.timescale 0 0;
|
||||
v0x55d64910fee0_0 .var "s1", 8 0;
|
||||
v0x55d64910ffa0_0 .net "s2", 3 0, v0x55d6490c37f0_0; 1 drivers
|
||||
S_0x55d6490fdd00 .scope module, "uut" "lab4" 2 6, 3 1 0, S_0x55d6490fdb70;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 9 "signal";
|
||||
.port_info 1 /OUTPUT 4 "S";
|
||||
v0x55d6490c37f0_0 .var "S", 3 0;
|
||||
v0x55d6490c3c00_0 .net "signal", 8 0, v0x55d64910fee0_0; 1 drivers
|
||||
E_0x55d6490c2340 .event edge, v0x55d6490c3c00_0;
|
||||
.scope S_0x55d6490fdd00;
|
||||
T_0 ;
|
||||
%wait E_0x55d6490c2340;
|
||||
%pushi/vec4 0, 0, 4;
|
||||
%store/vec4 v0x55d6490c37f0_0, 0, 4;
|
||||
%load/vec4 v0x55d6490c3c00_0;
|
||||
%parti/s 1, 8, 5;
|
||||
%pad/u 32;
|
||||
%cmpi/e 1, 0, 32;
|
||||
%jmp/0xz T_0.0, 4;
|
||||
%load/vec4 v0x55d6490c3c00_0;
|
||||
%parti/s 3, 3, 3;
|
||||
%pad/u 4;
|
||||
%load/vec4 v0x55d6490c3c00_0;
|
||||
%parti/s 3, 0, 2;
|
||||
%pad/u 4;
|
||||
%add;
|
||||
%store/vec4 v0x55d6490c37f0_0, 0, 4;
|
||||
%jmp T_0.1;
|
||||
T_0.0 ;
|
||||
%load/vec4 v0x55d6490c3c00_0;
|
||||
%parti/s 1, 7, 4;
|
||||
%pad/u 32;
|
||||
%cmpi/e 1, 0, 32;
|
||||
%jmp/0xz T_0.2, 4;
|
||||
%load/vec4 v0x55d6490c3c00_0;
|
||||
%parti/s 3, 3, 3;
|
||||
%pad/u 4;
|
||||
%load/vec4 v0x55d6490c3c00_0;
|
||||
%parti/s 3, 0, 2;
|
||||
%pad/u 4;
|
||||
%sub;
|
||||
%store/vec4 v0x55d6490c37f0_0, 0, 4;
|
||||
%jmp T_0.3;
|
||||
T_0.2 ;
|
||||
%load/vec4 v0x55d6490c3c00_0;
|
||||
%parti/s 1, 6, 4;
|
||||
%pad/u 32;
|
||||
%cmpi/e 1, 0, 32;
|
||||
%jmp/0xz T_0.4, 4;
|
||||
%load/vec4 v0x55d6490c3c00_0;
|
||||
%parti/s 3, 3, 3;
|
||||
%pad/u 4;
|
||||
%load/vec4 v0x55d6490c3c00_0;
|
||||
%parti/s 3, 0, 2;
|
||||
%pad/u 4;
|
||||
%and;
|
||||
%store/vec4 v0x55d6490c37f0_0, 0, 4;
|
||||
%jmp T_0.5;
|
||||
T_0.4 ;
|
||||
%load/vec4 v0x55d6490c3c00_0;
|
||||
%parti/s 1, 6, 4;
|
||||
%pad/u 32;
|
||||
%cmpi/e 0, 0, 32;
|
||||
%jmp/0xz T_0.6, 4;
|
||||
%load/vec4 v0x55d6490c3c00_0;
|
||||
%parti/s 3, 3, 3;
|
||||
%pad/u 4;
|
||||
%load/vec4 v0x55d6490c3c00_0;
|
||||
%parti/s 3, 0, 2;
|
||||
%pad/u 4;
|
||||
%or;
|
||||
%store/vec4 v0x55d6490c37f0_0, 0, 4;
|
||||
T_0.6 ;
|
||||
T_0.5 ;
|
||||
T_0.3 ;
|
||||
T_0.1 ;
|
||||
%jmp T_0;
|
||||
.thread T_0, $push;
|
||||
.scope S_0x55d6490fdb70;
|
||||
T_1 ;
|
||||
%vpi_call 2 12 "$dumpfile", "lab4v.vcd" {0 0 0};
|
||||
%vpi_call 2 13 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 297, 0, 9;
|
||||
%store/vec4 v0x55d64910fee0_0, 0, 9;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 169, 0, 9;
|
||||
%store/vec4 v0x55d64910fee0_0, 0, 9;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 105, 0, 9;
|
||||
%store/vec4 v0x55d64910fee0_0, 0, 9;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 41, 0, 9;
|
||||
%store/vec4 v0x55d64910fee0_0, 0, 9;
|
||||
%delay 10, 0;
|
||||
%vpi_call 2 19 "$display", "Done" {0 0 0};
|
||||
%end;
|
||||
.thread T_1;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"lab4tb.v";
|
||||
"lab4.v";
|
22
iverilog/tobb/labs/lab4/lab4tb.v
Normal file
22
iverilog/tobb/labs/lab4/lab4tb.v
Normal file
@ -0,0 +1,22 @@
|
||||
module lab4tb();
|
||||
|
||||
reg [8:0] s1;
|
||||
wire [3:0] s2;
|
||||
|
||||
lab4 uut(
|
||||
.signal(s1),
|
||||
.S(s2)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("lab4v.vcd");
|
||||
$dumpvars;
|
||||
|
||||
s1 = 9'b100_101_001; #10;
|
||||
s1 = 9'b010_101_001; #10;
|
||||
s1 = 9'b001_101_001; #10;
|
||||
s1 = 9'b000_101_001; #10;
|
||||
$display("Done");
|
||||
end
|
||||
|
||||
endmodule
|
41
iverilog/tobb/labs/lab4/lab4v.vcd
Normal file
41
iverilog/tobb/labs/lab4/lab4v.vcd
Normal file
@ -0,0 +1,41 @@
|
||||
$date
|
||||
Fri Jul 5 05:10:51 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module lab4tb $end
|
||||
$var wire 4 ! s2 [3:0] $end
|
||||
$var reg 9 " s1 [8:0] $end
|
||||
$scope module uut $end
|
||||
$var wire 9 # signal [8:0] $end
|
||||
$var reg 4 $ S [3:0] $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
#0
|
||||
$dumpvars
|
||||
b110 $
|
||||
b100101001 #
|
||||
b100101001 "
|
||||
b110 !
|
||||
$end
|
||||
#10
|
||||
b100 !
|
||||
b100 $
|
||||
b10101001 "
|
||||
b10101001 #
|
||||
#20
|
||||
b1 !
|
||||
b1 $
|
||||
b1101001 "
|
||||
b1101001 #
|
||||
#30
|
||||
b101 !
|
||||
b101 $
|
||||
b101001 "
|
||||
b101001 #
|
||||
#40
|
28
iverilog/tobb/labs/lab5/1.v
Normal file
28
iverilog/tobb/labs/lab5/1.v
Normal file
@ -0,0 +1,28 @@
|
||||
module timer (
|
||||
input clock,
|
||||
input reset,
|
||||
input gate,
|
||||
input [2:0] counter,
|
||||
input way,
|
||||
output reg [5:0] count
|
||||
);
|
||||
reg [5:0] countReg;
|
||||
|
||||
|
||||
always@(posedge clock or posedge reset) begin
|
||||
if (reset) begin
|
||||
countReg <= 6'd0;
|
||||
end
|
||||
else if (gate) begin
|
||||
if (way && (countReg != 6'b111_111)) begin
|
||||
countReg <= countReg + counter;
|
||||
end
|
||||
else if (!way && (countReg != 6'b000_000)) begin
|
||||
countReg <= countReg - counter;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
assign count = countReg;
|
||||
|
||||
endmodule
|
68
iverilog/tobb/labs/lab5/lab5
Normal file
68
iverilog/tobb/labs/lab5/lab5
Normal file
@ -0,0 +1,68 @@
|
||||
#! /usr/bin/vvp
|
||||
:ivl_version "11.0 (stable)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
|
||||
S_0x55ec01128cc0 .scope module, "seqBlinkTB" "seqBlinkTB" 2 1;
|
||||
.timescale 0 0;
|
||||
v0x55ec01139850_0 .var "clock", 0 0;
|
||||
v0x55ec01139920_0 .net "leds", 3 0, v0x55ec01139650_0; 1 drivers
|
||||
S_0x55ec01128e50 .scope module, "uut" "seqBlink" 2 6, 3 1 0, S_0x55ec01128cc0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "clock";
|
||||
.port_info 1 /OUTPUT 4 "leds";
|
||||
v0x55ec010f07f0_0 .net "clock", 0 0, v0x55ec01139850_0; 1 drivers
|
||||
v0x55ec010f0c00_0 .var "count", 1 0;
|
||||
v0x55ec01139650_0 .var "leds", 3 0;
|
||||
v0x55ec01139710_0 .var "start", 3 0;
|
||||
E_0x55ec01127bc0 .event posedge, v0x55ec010f07f0_0;
|
||||
.scope S_0x55ec01128e50;
|
||||
T_0 ;
|
||||
%pushi/vec4 0, 0, 2;
|
||||
%store/vec4 v0x55ec010f0c00_0, 0, 2;
|
||||
%pushi/vec4 1, 0, 4;
|
||||
%store/vec4 v0x55ec01139710_0, 0, 4;
|
||||
%end;
|
||||
.thread T_0;
|
||||
.scope S_0x55ec01128e50;
|
||||
T_1 ;
|
||||
%wait E_0x55ec01127bc0;
|
||||
%load/vec4 v0x55ec010f0c00_0;
|
||||
%addi 1, 0, 2;
|
||||
%assign/vec4 v0x55ec010f0c00_0, 0;
|
||||
%load/vec4 v0x55ec01139710_0;
|
||||
%ix/getv 4, v0x55ec010f0c00_0;
|
||||
%shiftl 4;
|
||||
%assign/vec4 v0x55ec01139650_0, 0;
|
||||
%jmp T_1;
|
||||
.thread T_1;
|
||||
.scope S_0x55ec01128cc0;
|
||||
T_2 ;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x55ec01139850_0, 0, 1;
|
||||
T_2.0 ;
|
||||
%delay 5, 0;
|
||||
%load/vec4 v0x55ec01139850_0;
|
||||
%inv;
|
||||
%store/vec4 v0x55ec01139850_0, 0, 1;
|
||||
%jmp T_2.0;
|
||||
%end;
|
||||
.thread T_2;
|
||||
.scope S_0x55ec01128cc0;
|
||||
T_3 ;
|
||||
%vpi_call 2 16 "$dumpfile", "lab5v.vcd" {0 0 0};
|
||||
%vpi_call 2 17 "$dumpvars" {0 0 0};
|
||||
%delay 100, 0;
|
||||
%vpi_call 2 21 "$finish" {0 0 0};
|
||||
%end;
|
||||
.thread T_3;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"seqBlinkTB.v";
|
||||
"seqBlink.v";
|
122
iverilog/tobb/labs/lab5/lab5t.vcd
Normal file
122
iverilog/tobb/labs/lab5/lab5t.vcd
Normal file
@ -0,0 +1,122 @@
|
||||
$date
|
||||
Mon Jul 8 05:12:15 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module timerTB $end
|
||||
$var wire 6 ! count [5:0] $end
|
||||
$var reg 1 " clock $end
|
||||
$var reg 3 # counter [2:0] $end
|
||||
$var reg 1 $ gate $end
|
||||
$var reg 1 % reset $end
|
||||
$var reg 1 & way $end
|
||||
$scope module uut $end
|
||||
$var wire 1 " clock $end
|
||||
$var wire 3 ' counter [2:0] $end
|
||||
$var wire 1 $ gate $end
|
||||
$var wire 1 % reset $end
|
||||
$var wire 1 & way $end
|
||||
$var reg 6 ( count [5:0] $end
|
||||
$var reg 6 ) countReg [5:0] $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
#0
|
||||
$dumpvars
|
||||
b101011 )
|
||||
b101011 (
|
||||
b10 '
|
||||
1&
|
||||
1%
|
||||
1$
|
||||
b10 #
|
||||
0"
|
||||
b101011 !
|
||||
$end
|
||||
#5
|
||||
b0 !
|
||||
b0 (
|
||||
b0 )
|
||||
1"
|
||||
#10
|
||||
0"
|
||||
#15
|
||||
1"
|
||||
#20
|
||||
0"
|
||||
#25
|
||||
1"
|
||||
#30
|
||||
0"
|
||||
#35
|
||||
1"
|
||||
#40
|
||||
0"
|
||||
#45
|
||||
1"
|
||||
#50
|
||||
0"
|
||||
#55
|
||||
1"
|
||||
#60
|
||||
0"
|
||||
#65
|
||||
1"
|
||||
#70
|
||||
0"
|
||||
#75
|
||||
1"
|
||||
#80
|
||||
0"
|
||||
#85
|
||||
1"
|
||||
#90
|
||||
0"
|
||||
#95
|
||||
1"
|
||||
#100
|
||||
0"
|
||||
#105
|
||||
1"
|
||||
#110
|
||||
0"
|
||||
#115
|
||||
1"
|
||||
#120
|
||||
0"
|
||||
#125
|
||||
1"
|
||||
#130
|
||||
0"
|
||||
#135
|
||||
1"
|
||||
#140
|
||||
0"
|
||||
#145
|
||||
1"
|
||||
#150
|
||||
0"
|
||||
#155
|
||||
1"
|
||||
#160
|
||||
0"
|
||||
#165
|
||||
1"
|
||||
#170
|
||||
0"
|
||||
#175
|
||||
1"
|
||||
#180
|
||||
0"
|
||||
#185
|
||||
1"
|
||||
#190
|
||||
0"
|
||||
#195
|
||||
1"
|
||||
#200
|
||||
0"
|
98
iverilog/tobb/labs/lab5/lab5v.vcd
Normal file
98
iverilog/tobb/labs/lab5/lab5v.vcd
Normal file
@ -0,0 +1,98 @@
|
||||
$date
|
||||
Sun Jul 7 02:46:47 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module seqBlinkTB $end
|
||||
$var wire 4 ! leds [3:0] $end
|
||||
$var reg 1 " clock $end
|
||||
$scope module uut $end
|
||||
$var wire 1 " clock $end
|
||||
$var reg 2 # count [1:0] $end
|
||||
$var reg 4 $ leds [3:0] $end
|
||||
$var reg 4 % start [3:0] $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
#0
|
||||
$dumpvars
|
||||
b1 %
|
||||
bx $
|
||||
b0 #
|
||||
0"
|
||||
bx !
|
||||
$end
|
||||
#5
|
||||
b1 !
|
||||
b1 $
|
||||
b1 #
|
||||
1"
|
||||
#10
|
||||
0"
|
||||
#15
|
||||
b10 !
|
||||
b10 $
|
||||
b10 #
|
||||
1"
|
||||
#20
|
||||
0"
|
||||
#25
|
||||
b100 !
|
||||
b100 $
|
||||
b11 #
|
||||
1"
|
||||
#30
|
||||
0"
|
||||
#35
|
||||
b1000 !
|
||||
b1000 $
|
||||
b0 #
|
||||
1"
|
||||
#40
|
||||
0"
|
||||
#45
|
||||
b1 !
|
||||
b1 $
|
||||
b1 #
|
||||
1"
|
||||
#50
|
||||
0"
|
||||
#55
|
||||
b10 !
|
||||
b10 $
|
||||
b10 #
|
||||
1"
|
||||
#60
|
||||
0"
|
||||
#65
|
||||
b100 !
|
||||
b100 $
|
||||
b11 #
|
||||
1"
|
||||
#70
|
||||
0"
|
||||
#75
|
||||
b1000 !
|
||||
b1000 $
|
||||
b0 #
|
||||
1"
|
||||
#80
|
||||
0"
|
||||
#85
|
||||
b1 !
|
||||
b1 $
|
||||
b1 #
|
||||
1"
|
||||
#90
|
||||
0"
|
||||
#95
|
||||
b10 !
|
||||
b10 $
|
||||
b10 #
|
||||
1"
|
||||
#100
|
||||
0"
|
36
iverilog/tobb/labs/lab5/seqBlink.v
Normal file
36
iverilog/tobb/labs/lab5/seqBlink.v
Normal file
@ -0,0 +1,36 @@
|
||||
module seqBlink (
|
||||
input clock,
|
||||
output reg [3:0] led
|
||||
);
|
||||
|
||||
reg [2:0] fsm = 0;
|
||||
|
||||
reg [31:0] clkcnt = 0;
|
||||
reg newclk = 0;
|
||||
|
||||
always@(posedge clock) begin
|
||||
clkcnt <= clkcnt + 1'b1;
|
||||
if (clkcnt > 9_000_000) begin
|
||||
clkcnt <= 0;
|
||||
newclk <= ~newclk;
|
||||
end
|
||||
end
|
||||
|
||||
always@(posedge newclk) begin
|
||||
if (fsm == 3'd7) begin
|
||||
fsm <= 0;
|
||||
end else begin
|
||||
fsm <= fsm + 1;
|
||||
end
|
||||
case (fsm)
|
||||
3'b000 : led <= 4'b0111;
|
||||
3'b001 : led <= 4'b1011;
|
||||
3'b010 : led <= 4'b1101;
|
||||
3'b011 : led <= 4'b1110;
|
||||
3'b100 : led <= 4'b1101;
|
||||
3'b101 : led <= 4'b1011;
|
||||
3'b110 : led <= 4'b0111;
|
||||
default: led <= 4'b0000;
|
||||
endcase
|
||||
end
|
||||
endmodule
|
24
iverilog/tobb/labs/lab5/seqBlinkTB.v
Normal file
24
iverilog/tobb/labs/lab5/seqBlinkTB.v
Normal file
@ -0,0 +1,24 @@
|
||||
module seqBlinkTB();
|
||||
|
||||
reg clock;
|
||||
wire [3:0] leds;
|
||||
|
||||
seqBlink uut(clock, leds);
|
||||
|
||||
initial begin
|
||||
clock = 0;
|
||||
forever begin
|
||||
#5 clock = ~clock;
|
||||
end
|
||||
end
|
||||
|
||||
initial begin
|
||||
$dumpfile("lab5v.vcd");
|
||||
$dumpvars;
|
||||
|
||||
#100;
|
||||
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
30
iverilog/tobb/labs/lab5/timer.v
Normal file
30
iverilog/tobb/labs/lab5/timer.v
Normal file
@ -0,0 +1,30 @@
|
||||
module timer (
|
||||
input clock,
|
||||
input reset,
|
||||
input gate,
|
||||
input [2:0] counter,
|
||||
input way,
|
||||
output reg [5:0] count
|
||||
);
|
||||
reg [5:0] countReg = 6'b101_011;
|
||||
|
||||
|
||||
always@(posedge clock) begin
|
||||
if (reset) begin
|
||||
countReg <= 6'd0;
|
||||
end
|
||||
else if (gate) begin
|
||||
if (way && (countReg != 6'b111_111)) begin
|
||||
countReg <= countReg + counter;
|
||||
end
|
||||
else if (!way && (countReg != 6'b000_000)) begin
|
||||
countReg <= countReg - counter;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always@(*) begin
|
||||
count = countReg;
|
||||
end
|
||||
|
||||
endmodule
|
27
iverilog/tobb/labs/lab5/timerTB.v
Normal file
27
iverilog/tobb/labs/lab5/timerTB.v
Normal file
@ -0,0 +1,27 @@
|
||||
module timerTB ();
|
||||
reg clock;
|
||||
reg reset;
|
||||
reg gate;
|
||||
reg [2:0] counter;
|
||||
reg way;
|
||||
wire [5:0] count;
|
||||
|
||||
timer uut (clock,reset,gate,counter,way,count);
|
||||
|
||||
initial begin
|
||||
clock = 0;
|
||||
forever begin
|
||||
#5 clock = ~clock;
|
||||
end
|
||||
end
|
||||
|
||||
initial begin
|
||||
$dumpfile("lab5t.vcd");
|
||||
$dumpvars;
|
||||
|
||||
reset = 1'b0; gate = 1'b1; counter = 3'b010; way = 1'b1;
|
||||
#200;
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
137
iverilog/tobb/labs/lab5/vlab5
Normal file
137
iverilog/tobb/labs/lab5/vlab5
Normal file
@ -0,0 +1,137 @@
|
||||
#! /usr/bin/vvp
|
||||
:ivl_version "11.0 (stable)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
|
||||
S_0x55928b0bbf60 .scope module, "timerTB" "timerTB" 2 1;
|
||||
.timescale 0 0;
|
||||
v0x55928b0d05d0_0 .var "clock", 0 0;
|
||||
v0x55928b0d0690_0 .net "count", 5 0, v0x55928b0d0000_0; 1 drivers
|
||||
v0x55928b0d0760_0 .var "counter", 2 0;
|
||||
v0x55928b0d0860_0 .var "gate", 0 0;
|
||||
v0x55928b0d0930_0 .var "reset", 0 0;
|
||||
v0x55928b0d0a20_0 .var "way", 0 0;
|
||||
S_0x55928b0bc0f0 .scope module, "uut" "timer" 2 9, 3 1 0, S_0x55928b0bbf60;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "clock";
|
||||
.port_info 1 /INPUT 1 "reset";
|
||||
.port_info 2 /INPUT 1 "gate";
|
||||
.port_info 3 /INPUT 3 "counter";
|
||||
.port_info 4 /INPUT 1 "way";
|
||||
.port_info 5 /OUTPUT 6 "count";
|
||||
v0x55928b0a8600_0 .net "clock", 0 0, v0x55928b0d05d0_0; 1 drivers
|
||||
v0x55928b0d0000_0 .var "count", 5 0;
|
||||
v0x55928b0d00e0_0 .var "countReg", 5 0;
|
||||
v0x55928b0d01a0_0 .net "counter", 2 0, v0x55928b0d0760_0; 1 drivers
|
||||
v0x55928b0d0280_0 .net "gate", 0 0, v0x55928b0d0860_0; 1 drivers
|
||||
v0x55928b0d0390_0 .net "reset", 0 0, v0x55928b0d0930_0; 1 drivers
|
||||
v0x55928b0d0450_0 .net "way", 0 0, v0x55928b0d0a20_0; 1 drivers
|
||||
E_0x55928b0b8e60 .event edge, v0x55928b0d00e0_0;
|
||||
E_0x55928b0b9330 .event posedge, v0x55928b0a8600_0;
|
||||
.scope S_0x55928b0bc0f0;
|
||||
T_0 ;
|
||||
%pushi/vec4 43, 0, 6;
|
||||
%store/vec4 v0x55928b0d00e0_0, 0, 6;
|
||||
%end;
|
||||
.thread T_0;
|
||||
.scope S_0x55928b0bc0f0;
|
||||
T_1 ;
|
||||
%wait E_0x55928b0b9330;
|
||||
%load/vec4 v0x55928b0d0390_0;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_1.0, 8;
|
||||
%pushi/vec4 0, 0, 6;
|
||||
%assign/vec4 v0x55928b0d00e0_0, 0;
|
||||
%jmp T_1.1;
|
||||
T_1.0 ;
|
||||
%load/vec4 v0x55928b0d0280_0;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_1.2, 8;
|
||||
%load/vec4 v0x55928b0d0450_0;
|
||||
%load/vec4 v0x55928b0d00e0_0;
|
||||
%pushi/vec4 63, 0, 6;
|
||||
%cmp/ne;
|
||||
%flag_get/vec4 4;
|
||||
%and;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_1.4, 8;
|
||||
%load/vec4 v0x55928b0d00e0_0;
|
||||
%load/vec4 v0x55928b0d01a0_0;
|
||||
%pad/u 6;
|
||||
%add;
|
||||
%assign/vec4 v0x55928b0d00e0_0, 0;
|
||||
%jmp T_1.5;
|
||||
T_1.4 ;
|
||||
%load/vec4 v0x55928b0d0450_0;
|
||||
%nor/r;
|
||||
%load/vec4 v0x55928b0d00e0_0;
|
||||
%pushi/vec4 0, 0, 6;
|
||||
%cmp/ne;
|
||||
%flag_get/vec4 4;
|
||||
%and;
|
||||
%flag_set/vec4 8;
|
||||
%jmp/0xz T_1.6, 8;
|
||||
%load/vec4 v0x55928b0d00e0_0;
|
||||
%load/vec4 v0x55928b0d01a0_0;
|
||||
%pad/u 6;
|
||||
%sub;
|
||||
%assign/vec4 v0x55928b0d00e0_0, 0;
|
||||
T_1.6 ;
|
||||
T_1.5 ;
|
||||
T_1.2 ;
|
||||
T_1.1 ;
|
||||
%jmp T_1;
|
||||
.thread T_1;
|
||||
.scope S_0x55928b0bc0f0;
|
||||
T_2 ;
|
||||
%wait E_0x55928b0b8e60;
|
||||
%load/vec4 v0x55928b0d00e0_0;
|
||||
%store/vec4 v0x55928b0d0000_0, 0, 6;
|
||||
%jmp T_2;
|
||||
.thread T_2, $push;
|
||||
.scope S_0x55928b0bbf60;
|
||||
T_3 ;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x55928b0d05d0_0, 0, 1;
|
||||
T_3.0 ;
|
||||
%delay 5, 0;
|
||||
%load/vec4 v0x55928b0d05d0_0;
|
||||
%inv;
|
||||
%store/vec4 v0x55928b0d05d0_0, 0, 1;
|
||||
%jmp T_3.0;
|
||||
%end;
|
||||
.thread T_3;
|
||||
.scope S_0x55928b0bbf60;
|
||||
T_4 ;
|
||||
%vpi_call 2 19 "$dumpfile", "lab5t.vcd" {0 0 0};
|
||||
%vpi_call 2 20 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x55928b0d0930_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x55928b0d0860_0, 0, 1;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%store/vec4 v0x55928b0d0760_0, 0, 3;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x55928b0d0a20_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x55928b0d0930_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x55928b0d0860_0, 0, 1;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%store/vec4 v0x55928b0d0760_0, 0, 3;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x55928b0d0a20_0, 0, 1;
|
||||
%delay 200, 0;
|
||||
%vpi_call 2 25 "$finish" {0 0 0};
|
||||
%end;
|
||||
.thread T_4;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"timerTB.v";
|
||||
"timer.v";
|
35
iverilog/tobb/labs/lab6/bibp.v
Normal file
35
iverilog/tobb/labs/lab6/bibp.v
Normal file
@ -0,0 +1,35 @@
|
||||
module bibp #(parameter UZUNLUK = 8)(
|
||||
input [UZUNLUK + 2:0] buyruk,
|
||||
/* output reg [(UZUNLUK/2) - 1:0] v1,
|
||||
output reg [(UZUNLUK/2) - 1:0] v2, */
|
||||
output reg [(UZUNLUK/2):0] sonuc
|
||||
);
|
||||
|
||||
/* localparam halfUZUNLUK = UZUNLUK / 2;
|
||||
localparam v1 = buyruk[UZUNLUK - 1 : halfUZUNLUK];
|
||||
localparam v2 = buyruk[halfUZUNLUK - 1 : 0];
|
||||
*/
|
||||
|
||||
/*assign v1 = buyruk[UZUNLUK - 1 : UZUNLUK/2];
|
||||
assign v2 = buyruk[UZUNLUK/2 : 0];*/
|
||||
|
||||
// wire [(UZUNLUK/2) - 1:0] v1,v2;
|
||||
|
||||
// !!! LOCALPARAM IVERILOG DA PROBLEMLI OLDUGU ICIN KULLANILMIYOR !!!
|
||||
|
||||
always@(*) begin
|
||||
$display("%d", buyruk[UZUNLUK - 1 : UZUNLUK/2]);
|
||||
$display("%d", buyruk[(UZUNLUK/2) - 1 : 0]);
|
||||
$display("%d", buyruk[UZUNLUK - 1 : UZUNLUK/2] - buyruk[(UZUNLUK/2) - 1 : 0]);
|
||||
case(buyruk[UZUNLUK+2:UZUNLUK])
|
||||
3'b000: sonuc = buyruk[(UZUNLUK - 1) : UZUNLUK/2] + buyruk[(UZUNLUK/2) - 1 : 0];
|
||||
3'b001: sonuc = buyruk[(UZUNLUK - 1) : UZUNLUK/2] - buyruk[(UZUNLUK/2) - 1 : 0]; // SUBTRACTION ?????? CHECK!!!
|
||||
3'b010: sonuc = {1'b0, buyruk[UZUNLUK - 1 : UZUNLUK/2] & buyruk[(UZUNLUK/2) - 1 : 0]};
|
||||
3'b011: sonuc = {1'b0, buyruk[UZUNLUK - 1 : UZUNLUK/2] | buyruk[(UZUNLUK/2) - 1 : 0]};
|
||||
3'b100: sonuc = {1'b0, buyruk[UZUNLUK - 1 : UZUNLUK/2] ^ buyruk[(UZUNLUK/2) - 1 : 0]};
|
||||
default: sonuc = -1;
|
||||
endcase
|
||||
$display("%b", sonuc);
|
||||
end
|
||||
|
||||
endmodule
|
16
iverilog/tobb/labs/lab6/bibpTB.v
Normal file
16
iverilog/tobb/labs/lab6/bibpTB.v
Normal file
@ -0,0 +1,16 @@
|
||||
module bibpTB();
|
||||
|
||||
parameter UZUNLUK = 8;
|
||||
reg [UZUNLUK+2:0] buyruk;
|
||||
wire [UZUNLUK/2:0] sonuc;
|
||||
|
||||
bibp #(.UZUNLUK(UZUNLUK)) uut(.buyruk(buyruk), .sonuc(sonuc));
|
||||
|
||||
initial begin
|
||||
$dumpfile("vbibp.vcd");
|
||||
$dumpvars;
|
||||
|
||||
buyruk = 11'b111_0101_0100; #10;
|
||||
$finish;
|
||||
end
|
||||
endmodule
|
BIN
iverilog/tobb/labs/lab6/obj_dir/Vbibp
Normal file
BIN
iverilog/tobb/labs/lab6/obj_dir/Vbibp
Normal file
Binary file not shown.
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user