rearrangement

iverilog/tobb/labs/lab3/src/3dmp.vcd

@@ -0,0 +1,142 @@
+$date
+	Sat May 04 01:15:09 2024
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module fullAdder $end
+$var wire 1 ! A $end
+$var wire 1 " B $end
+$var wire 1 # C $end
+$var wire 1 $ Z $end
+$var wire 1 % W2 $end
+$var wire 1 & W1 $end
+$var wire 1 ' W0 $end
+$var wire 1 ( S $end
+$scope module h0 $end
+$var wire 1 ! A $end
+$var wire 1 " B $end
+$var wire 1 & C $end
+$var wire 1 ' S $end
+$upscope $end
+$scope module h1 $end
+$var wire 1 ' A $end
+$var wire 1 $ B $end
+$var wire 1 % C $end
+$var wire 1 ( S $end
+$upscope $end
+$upscope $end
+$scope module mtb $end
+$var wire 4 ) C [3:0] $end
+$var reg 2 * A [1:0] $end
+$var reg 2 + B [1:0] $end
+$scope module uut $end
+$var wire 2 , A [1:0] $end
+$var wire 2 - B [1:0] $end
+$var wire 1 . c1 $end
+$var wire 1 / c2 $end
+$var wire 1 0 c5 $end
+$var wire 1 1 c4 $end
+$var wire 4 2 C [3:0] $end
+$scope module h0 $end
+$var wire 1 . A $end
+$var wire 1 / B $end
+$var wire 1 1 C $end
+$var wire 1 3 S $end
+$upscope $end
+$scope module h1 $end
+$var wire 1 0 A $end
+$var wire 1 1 B $end
+$var wire 1 4 C $end
+$var wire 1 5 S $end
+$upscope $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+$comment Show the parameter values. $end
+$dumpall
+$end
+#0
+$dumpvars
+05
+04
+03
+b0 2
+01
+00
+0/
+0.
+b11 -
+b0 ,
+b11 +
+b0 *
+b0 )
+x(
+x'
+x&
+x%
+z$
+x#
+z"
+z!
+$end
+#10
+b10 )
+b10 2
+13
+1/
+b10 +
+b10 -
+b1 *
+b1 ,
+#20
+1.
+0/
+b1 +
+b1 -
+b10 *
+b10 ,
+#30
+b0 )
+b0 2
+03
+0.
+b0 +
+b0 -
+b11 *
+b11 ,
+#40
+b0 *
+b0 ,
+#50
+b1 )
+b1 2
+b1 +
+b1 -
+b1 *
+b1 ,
+#60
+15
+10
+b1000 )
+b1000 2
+b10 +
+b10 -
+b10 *
+b10 ,
+#70
+05
+14
+11
+1.
+1/
+b101 )
+b101 2
+b11 +
+b11 -
+b11 *
+b11 ,
+#80