iverilog

2024-10-08 14:35:09 +03:00
parent 927028192e
commit 1ec83b26a1
12 changed files with 530 additions and 0 deletions
--- a/iverilog/lab2/fulladder.v
+++ b/iverilog/lab2/fulladder.v
@ -0,0 +1,13 @@
+module fullAdder (
+    input A,
+    input B,
+    input Cin,
+    output S,
+    output Cout
+);
+    wire AxB, AnB1, AnB2;
+    halfadder h1(A, B, AxB, AnB2);
+    halfadder h2(AxB, Cin, S, AnB1);
+
+    or o1(Cout, AnB1, AnB2);
+endmodule