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iverilog

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k0rrluna
2024-10-08 14:35:09 +03:00
parent 927028192e
commit 1ec83b26a1
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iverilog/lab2/halfadder.v Normal file
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module halfadder (
input A,
input B,
output S,
output C
);
xor x1(S, A, B);
and a1(C, A, B);
endmodule