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iverilog

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k0rrluna
2024-10-08 14:35:09 +03:00
parent 927028192e
commit 1ec83b26a1
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18
iverilog/lab2/halfaddertb.v Normal file
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module halfaddertb ();
reg A, B;
wire S, C;
halfadder uut(
.A(A), .B(B), .S(S), .C(C)
);
initial begin
$dumpfile("hadmp.vcd");
$dumpvars;
A = 1'b0; B = 1'b0; #10;
A = 1'b0; B = 1'b1; #10;
A = 1'b1; B = 1'b0; #10;
A = 1'b1; B = 1'b1; #10;
end
endmodule