xorGate

2024-12-09 22:57:42 +03:00
parent 6f6f491135
commit 2acbfd9d8d
29 changed files with 1478 additions and 1231 deletions
--- a/iverilog/tobb/lab2/fulladder.v
+++ b/iverilog/tobb/lab2/fulladder.v
@ -0,0 +1,16 @@
+module fulladder (
+    input  A,
+    input  B,
+    input  Cin,
+    output S,
+    output Cout
+);
+  wire AxB, AnB1, AnB2;
+
+
+  halfadder h1 (A,B,AxB,AnB2);
+
+  halfadder h2 (AxB,Cin,S,AnB1);
+
+  or o1 (Cout,AnB1,AnB2);
+endmodule