verilog

labs/lab5/seqBlinkTB.v

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+module seqBlinkTB();
+
+reg clock;
+wire [3:0] leds;
+
+seqBlink uut(clock, leds);
+
+initial begin
+    clock = 0;
+    forever begin
+        #5 clock = ~clock;
+    end
+end
+
+initial begin
+    $dumpfile("lab5v.vcd");
+    $dumpvars;
+
+    #100;
+    
+    $finish;
+end
+
+endmodule