subtraction & multiplier
This commit is contained in:
@ -1,38 +0,0 @@
|
||||
$date
|
||||
Wed Nov 6 15:42:14 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module htb $end
|
||||
$var wire 4 ! hammingValue [3:0] $end
|
||||
$var reg 8 " value1 [7:0] $end
|
||||
$var reg 8 # value2 [7:0] $end
|
||||
$scope module uut $end
|
||||
$var wire 8 $ value1 [7:0] $end
|
||||
$var wire 8 % value2 [7:0] $end
|
||||
$var reg 4 & hammingValue [3:0] $end
|
||||
$var integer 32 ' i [31:0] $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
#0
|
||||
$dumpvars
|
||||
b1000 '
|
||||
b100 &
|
||||
b10111111 %
|
||||
b10110000 $
|
||||
b10111111 #
|
||||
b10110000 "
|
||||
b100 !
|
||||
$end
|
||||
#10
|
||||
b1000 '
|
||||
b0 !
|
||||
b0 &
|
||||
b10111111 "
|
||||
b10111111 $
|
||||
#20
|
||||
@ -1,83 +0,0 @@
|
||||
#! /usr/bin/vvp
|
||||
:ivl_version "11.0 (stable)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
|
||||
S_0x55be1d5c3f90 .scope module, "htb" "htb" 2 1;
|
||||
.timescale 0 0;
|
||||
v0x55be1d5d5ae0_0 .net "hammingValue", 3 0, v0x55be1d58ab00_0; 1 drivers
|
||||
v0x55be1d5d5bd0_0 .var "value1", 7 0;
|
||||
v0x55be1d5d5ca0_0 .var "value2", 7 0;
|
||||
S_0x55be1d5c4120 .scope module, "uut" "hamming" 2 7, 3 1 0, S_0x55be1d5c3f90;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 8 "value1";
|
||||
.port_info 1 /INPUT 8 "value2";
|
||||
.port_info 2 /OUTPUT 4 "hammingValue";
|
||||
v0x55be1d58ab00_0 .var "hammingValue", 3 0;
|
||||
v0x55be1d58af10_0 .var/i "i", 31 0;
|
||||
v0x55be1d5d58c0_0 .net "value1", 7 0, v0x55be1d5d5bd0_0; 1 drivers
|
||||
v0x55be1d5d5980_0 .net "value2", 7 0, v0x55be1d5d5ca0_0; 1 drivers
|
||||
E_0x55be1d589690 .event edge, v0x55be1d5d58c0_0, v0x55be1d5d5980_0, v0x55be1d58ab00_0;
|
||||
.scope S_0x55be1d5c4120;
|
||||
T_0 ;
|
||||
%pushi/vec4 0, 0, 32;
|
||||
%store/vec4 v0x55be1d58af10_0, 0, 32;
|
||||
%end;
|
||||
.thread T_0;
|
||||
.scope S_0x55be1d5c4120;
|
||||
T_1 ;
|
||||
%wait E_0x55be1d589690;
|
||||
%pushi/vec4 0, 0, 4;
|
||||
%store/vec4 v0x55be1d58ab00_0, 0, 4;
|
||||
%pushi/vec4 0, 0, 32;
|
||||
%store/vec4 v0x55be1d58af10_0, 0, 32;
|
||||
T_1.0 ;
|
||||
%load/vec4 v0x55be1d58af10_0;
|
||||
%cmpi/s 8, 0, 32;
|
||||
%jmp/0xz T_1.1, 5;
|
||||
%load/vec4 v0x55be1d5d58c0_0;
|
||||
%load/vec4 v0x55be1d58af10_0;
|
||||
%part/s 1;
|
||||
%load/vec4 v0x55be1d5d5980_0;
|
||||
%load/vec4 v0x55be1d58af10_0;
|
||||
%part/s 1;
|
||||
%cmp/ne;
|
||||
%jmp/0xz T_1.2, 4;
|
||||
%load/vec4 v0x55be1d58ab00_0;
|
||||
%addi 1, 0, 4;
|
||||
%store/vec4 v0x55be1d58ab00_0, 0, 4;
|
||||
T_1.2 ;
|
||||
%load/vec4 v0x55be1d58af10_0;
|
||||
%addi 1, 0, 32;
|
||||
%store/vec4 v0x55be1d58af10_0, 0, 32;
|
||||
%jmp T_1.0;
|
||||
T_1.1 ;
|
||||
%jmp T_1;
|
||||
.thread T_1, $push;
|
||||
.scope S_0x55be1d5c3f90;
|
||||
T_2 ;
|
||||
%vpi_call 2 14 "$dumpfile", "ham.vcd" {0 0 0};
|
||||
%vpi_call 2 15 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 176, 0, 8;
|
||||
%store/vec4 v0x55be1d5d5bd0_0, 0, 8;
|
||||
%pushi/vec4 191, 0, 8;
|
||||
%store/vec4 v0x55be1d5d5ca0_0, 0, 8;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 191, 0, 8;
|
||||
%store/vec4 v0x55be1d5d5bd0_0, 0, 8;
|
||||
%pushi/vec4 191, 0, 8;
|
||||
%store/vec4 v0x55be1d5d5ca0_0, 0, 8;
|
||||
%delay 10, 0;
|
||||
%vpi_call 2 18 "$display", v0x55be1d5d5ae0_0 {0 0 0};
|
||||
%end;
|
||||
.thread T_2;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"htb.v";
|
||||
"hamming.v";
|
||||
@ -1,17 +0,0 @@
|
||||
module hamming (
|
||||
input[7:0] value1,
|
||||
input[7:0] value2,
|
||||
output reg[3:0] hammingValue
|
||||
);
|
||||
|
||||
integer i = 0;
|
||||
|
||||
always @(*) begin
|
||||
hammingValue = 0;
|
||||
for(i = 0; i < 8; i = i+1) begin
|
||||
if (value1[i] != value2[i]) begin
|
||||
hammingValue = hammingValue + 1;
|
||||
end
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
@ -1,20 +0,0 @@
|
||||
module htb ();
|
||||
|
||||
reg [7:0] value1;
|
||||
reg [7:0] value2;
|
||||
wire [3:0] hammingValue;
|
||||
|
||||
hamming uut (
|
||||
.value1(value1),
|
||||
.value2(value2),
|
||||
.hammingValue(hammingValue)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("ham.vcd");
|
||||
$dumpvars;
|
||||
value1 = 8'hB0; value2 = 8'hBF; #10;
|
||||
value1 = 8'hBF; value2 = 8'hBF; #10;
|
||||
$display(hammingValue);
|
||||
end
|
||||
endmodule
|
||||
@ -1,40 +0,0 @@
|
||||
$date
|
||||
Tue Oct 8 10:23:08 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module halfaddertb $end
|
||||
$var wire 1 ! S $end
|
||||
$var wire 1 " C $end
|
||||
$var reg 1 # A $end
|
||||
$var reg 1 $ B $end
|
||||
$scope module uut $end
|
||||
$var wire 1 # A $end
|
||||
$var wire 1 $ B $end
|
||||
$var wire 1 " C $end
|
||||
$var wire 1 ! S $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
#0
|
||||
$dumpvars
|
||||
0$
|
||||
0#
|
||||
0"
|
||||
0!
|
||||
$end
|
||||
#10
|
||||
1!
|
||||
1$
|
||||
#20
|
||||
0$
|
||||
1#
|
||||
#30
|
||||
0!
|
||||
1"
|
||||
1$
|
||||
#40
|
||||
@ -1,59 +0,0 @@
|
||||
#! /usr/bin/vvp
|
||||
:ivl_version "11.0 (stable)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
|
||||
S_0x5583f1e33260 .scope module, "halfaddertb" "halfaddertb" 2 1;
|
||||
.timescale 0 0;
|
||||
v0x5583f1e44440_0 .var "A", 0 0;
|
||||
v0x5583f1e44500_0 .var "B", 0 0;
|
||||
v0x5583f1e445d0_0 .net "C", 0 0, L_0x5583f1e44900; 1 drivers
|
||||
v0x5583f1e446d0_0 .net "S", 0 0, L_0x5583f1e447a0; 1 drivers
|
||||
S_0x5583f1e333f0 .scope module, "uut" "halfadder" 2 5, 3 1 0, S_0x5583f1e33260;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "S";
|
||||
.port_info 3 /OUTPUT 1 "C";
|
||||
L_0x5583f1e447a0 .functor XOR 1, v0x5583f1e44440_0, v0x5583f1e44500_0, C4<0>, C4<0>;
|
||||
L_0x5583f1e44900 .functor AND 1, v0x5583f1e44440_0, v0x5583f1e44500_0, C4<1>, C4<1>;
|
||||
v0x5583f1dfbc00_0 .net "A", 0 0, v0x5583f1e44440_0; 1 drivers
|
||||
v0x5583f1e44140_0 .net "B", 0 0, v0x5583f1e44500_0; 1 drivers
|
||||
v0x5583f1e44200_0 .net "C", 0 0, L_0x5583f1e44900; alias, 1 drivers
|
||||
v0x5583f1e442d0_0 .net "S", 0 0, L_0x5583f1e447a0; alias, 1 drivers
|
||||
.scope S_0x5583f1e33260;
|
||||
T_0 ;
|
||||
%vpi_call 2 10 "$dumpfile", "hadmp.vcd" {0 0 0};
|
||||
%vpi_call 2 11 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5583f1e44440_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5583f1e44500_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5583f1e44440_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5583f1e44500_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5583f1e44440_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x5583f1e44500_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5583f1e44440_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x5583f1e44500_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"halfaddertb.v";
|
||||
"halfadder.v";
|
||||
@ -1,9 +0,0 @@
|
||||
module halfadder (
|
||||
input A,
|
||||
input B,
|
||||
output S,
|
||||
output C
|
||||
);
|
||||
xor x1(S, A, B);
|
||||
and a1(C, A, B);
|
||||
endmodule
|
||||
@ -1,18 +0,0 @@
|
||||
module halfaddertb ();
|
||||
reg A, B;
|
||||
wire S, C;
|
||||
|
||||
halfadder uut(
|
||||
.A(A), .B(B), .S(S), .C(C)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("hadmp.vcd");
|
||||
$dumpvars;
|
||||
A = 1'b0; B = 1'b0; #10;
|
||||
A = 1'b0; B = 1'b1; #10;
|
||||
A = 1'b1; B = 1'b0; #10;
|
||||
A = 1'b1; B = 1'b1; #10;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@ -1,202 +0,0 @@
|
||||
#! /usr/bin/vvp
|
||||
:ivl_version "11.0 (stable)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
|
||||
S_0x5555993ec6a0 .scope module, "tb" "tb" 2 1;
|
||||
.timescale 0 0;
|
||||
v0x5555994063f0_0 .net "bitti_mi", 0 0, L_0x5555994068b0; 1 drivers
|
||||
v0x5555994064b0_0 .net "cevrim", 4 0, L_0x5555994067c0; 1 drivers
|
||||
v0x555599406550_0 .var "clk", 0 0;
|
||||
v0x555599406650_0 .var "parca", 2 0;
|
||||
v0x555599406720_0 .net "yukseklik", 4 0, v0x555599406270_0; 1 drivers
|
||||
S_0x5555993ec830 .scope module, "uut" "tetris" 2 10, 3 1 0, S_0x5555993ec6a0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "clk";
|
||||
.port_info 1 /INPUT 3 "parca";
|
||||
.port_info 2 /OUTPUT 5 "yukseklik";
|
||||
.port_info 3 /OUTPUT 5 "cevrim";
|
||||
.port_info 4 /OUTPUT 1 "bitti_mi";
|
||||
L_0x5555994067c0 .functor BUFZ 5, v0x555599405d00_0, C4<00000>, C4<00000>, C4<00000>;
|
||||
L_0x7f7b9f218018 .functor BUFT 1, C4<10000>, C4<0>, C4<0>, C4<0>;
|
||||
v0x5555993ec9e0_0 .net/2u *"_ivl_2", 4 0, L_0x7f7b9f218018; 1 drivers
|
||||
v0x555599405b80_0 .net "bitti_mi", 0 0, L_0x5555994068b0; alias, 1 drivers
|
||||
v0x555599405c40_0 .net "cevrim", 4 0, L_0x5555994067c0; alias, 1 drivers
|
||||
v0x555599405d00_0 .var "cevrim_r", 4 0;
|
||||
v0x555599405de0_0 .net "clk", 0 0, v0x555599406550_0; 1 drivers
|
||||
v0x555599405ef0_0 .net "parca", 2 0, v0x555599406650_0; 1 drivers
|
||||
v0x555599405fd0_0 .var "y_0", 4 0;
|
||||
v0x5555994060b0_0 .var "y_1", 4 0;
|
||||
v0x555599406190_0 .var "y_2", 4 0;
|
||||
v0x555599406270_0 .var "yukseklik", 4 0;
|
||||
E_0x5555993e7d70 .event posedge, v0x555599405b80_0;
|
||||
E_0x5555993af500 .event posedge, v0x555599405de0_0;
|
||||
L_0x5555994068b0 .cmp/eq 5, v0x555599405d00_0, L_0x7f7b9f218018;
|
||||
.scope S_0x5555993ec830;
|
||||
T_0 ;
|
||||
%pushi/vec4 0, 0, 5;
|
||||
%store/vec4 v0x555599405d00_0, 0, 5;
|
||||
%pushi/vec4 0, 0, 5;
|
||||
%store/vec4 v0x555599405fd0_0, 0, 5;
|
||||
%pushi/vec4 0, 0, 5;
|
||||
%store/vec4 v0x5555994060b0_0, 0, 5;
|
||||
%pushi/vec4 0, 0, 5;
|
||||
%store/vec4 v0x555599406190_0, 0, 5;
|
||||
%end;
|
||||
.thread T_0;
|
||||
.scope S_0x5555993ec830;
|
||||
T_1 ;
|
||||
%wait E_0x5555993af500;
|
||||
%load/vec4 v0x555599405c40_0;
|
||||
%cmpi/ne 16, 0, 5;
|
||||
%jmp/0xz T_1.0, 4;
|
||||
%load/vec4 v0x555599405d00_0;
|
||||
%addi 1, 0, 5;
|
||||
%assign/vec4 v0x555599405d00_0, 0;
|
||||
%load/vec4 v0x555599405fd0_0;
|
||||
%pushi/vec4 0, 0, 4;
|
||||
%load/vec4 v0x555599405ef0_0;
|
||||
%parti/s 1, 0, 2;
|
||||
%concat/vec4; draw_concat_vec4
|
||||
%add;
|
||||
%assign/vec4 v0x555599405fd0_0, 0;
|
||||
%load/vec4 v0x5555994060b0_0;
|
||||
%pushi/vec4 0, 0, 4;
|
||||
%load/vec4 v0x555599405ef0_0;
|
||||
%parti/s 1, 1, 2;
|
||||
%concat/vec4; draw_concat_vec4
|
||||
%add;
|
||||
%assign/vec4 v0x5555994060b0_0, 0;
|
||||
%load/vec4 v0x555599406190_0;
|
||||
%pushi/vec4 0, 0, 4;
|
||||
%load/vec4 v0x555599405ef0_0;
|
||||
%parti/s 1, 2, 3;
|
||||
%concat/vec4; draw_concat_vec4
|
||||
%add;
|
||||
%assign/vec4 v0x555599406190_0, 0;
|
||||
T_1.0 ;
|
||||
%jmp T_1;
|
||||
.thread T_1;
|
||||
.scope S_0x5555993ec830;
|
||||
T_2 ;
|
||||
%wait E_0x5555993e7d70;
|
||||
%load/vec4 v0x5555994060b0_0;
|
||||
%load/vec4 v0x555599405fd0_0;
|
||||
%cmp/u;
|
||||
%jmp/0xz T_2.0, 5;
|
||||
%load/vec4 v0x555599406190_0;
|
||||
%load/vec4 v0x555599405fd0_0;
|
||||
%cmp/u;
|
||||
%jmp/0xz T_2.2, 5;
|
||||
%load/vec4 v0x555599405fd0_0;
|
||||
%assign/vec4 v0x555599406270_0, 0;
|
||||
%jmp T_2.3;
|
||||
T_2.2 ;
|
||||
%load/vec4 v0x555599406190_0;
|
||||
%assign/vec4 v0x555599406270_0, 0;
|
||||
T_2.3 ;
|
||||
%jmp T_2.1;
|
||||
T_2.0 ;
|
||||
%load/vec4 v0x5555994060b0_0;
|
||||
%load/vec4 v0x555599405fd0_0;
|
||||
%cmp/u;
|
||||
%jmp/0xz T_2.4, 5;
|
||||
%load/vec4 v0x555599406190_0;
|
||||
%load/vec4 v0x5555994060b0_0;
|
||||
%cmp/u;
|
||||
%jmp/0xz T_2.6, 5;
|
||||
%load/vec4 v0x5555994060b0_0;
|
||||
%assign/vec4 v0x555599406270_0, 0;
|
||||
%jmp T_2.7;
|
||||
T_2.6 ;
|
||||
%load/vec4 v0x555599406190_0;
|
||||
%assign/vec4 v0x555599406270_0, 0;
|
||||
T_2.7 ;
|
||||
T_2.4 ;
|
||||
T_2.1 ;
|
||||
%jmp T_2;
|
||||
.thread T_2;
|
||||
.scope S_0x5555993ec6a0;
|
||||
T_3 ;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x555599406550_0, 0, 1;
|
||||
%end;
|
||||
.thread T_3;
|
||||
.scope S_0x5555993ec6a0;
|
||||
T_4 ;
|
||||
%load/vec4 v0x555599406550_0;
|
||||
%inv;
|
||||
%store/vec4 v0x555599406550_0, 0, 1;
|
||||
%delay 5, 0;
|
||||
%jmp T_4;
|
||||
.thread T_4;
|
||||
.scope S_0x5555993ec6a0;
|
||||
T_5 ;
|
||||
%vpi_call 2 23 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 5, 0, 3;
|
||||
%store/vec4 v0x555599406650_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v0x555599406650_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 5, 0, 3;
|
||||
%store/vec4 v0x555599406650_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v0x555599406650_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 5, 0, 3;
|
||||
%store/vec4 v0x555599406650_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v0x555599406650_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 5, 0, 3;
|
||||
%store/vec4 v0x555599406650_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v0x555599406650_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 5, 0, 3;
|
||||
%store/vec4 v0x555599406650_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v0x555599406650_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 5, 0, 3;
|
||||
%store/vec4 v0x555599406650_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v0x555599406650_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 5, 0, 3;
|
||||
%store/vec4 v0x555599406650_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v0x555599406650_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 5, 0, 3;
|
||||
%store/vec4 v0x555599406650_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v0x555599406650_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 5, 0, 3;
|
||||
%store/vec4 v0x555599406650_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v0x555599406650_0, 0, 3;
|
||||
%delay 10, 0;
|
||||
%vpi_call 2 42 "$finish" {0 0 0};
|
||||
%end;
|
||||
.thread T_5;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"tb.v";
|
||||
"tetris.v";
|
||||
Binary file not shown.
@ -1,92 +0,0 @@
|
||||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Model implementation (design independent parts)
|
||||
|
||||
#include "Vtb.h"
|
||||
#include "Vtb__Syms.h"
|
||||
|
||||
//============================================================
|
||||
// Constructors
|
||||
|
||||
Vtb::Vtb(VerilatedContext* _vcontextp__, const char* _vcname__)
|
||||
: VerilatedModel{*_vcontextp__}
|
||||
, vlSymsp{new Vtb__Syms(contextp(), _vcname__, this)}
|
||||
, rootp{&(vlSymsp->TOP)}
|
||||
{
|
||||
// Register model with the context
|
||||
contextp()->addModel(this);
|
||||
}
|
||||
|
||||
Vtb::Vtb(const char* _vcname__)
|
||||
: Vtb(Verilated::threadContextp(), _vcname__)
|
||||
{
|
||||
}
|
||||
|
||||
//============================================================
|
||||
// Destructor
|
||||
|
||||
Vtb::~Vtb() {
|
||||
delete vlSymsp;
|
||||
}
|
||||
|
||||
//============================================================
|
||||
// Evaluation function
|
||||
|
||||
#ifdef VL_DEBUG
|
||||
void Vtb___024root___eval_debug_assertions(Vtb___024root* vlSelf);
|
||||
#endif // VL_DEBUG
|
||||
void Vtb___024root___eval_static(Vtb___024root* vlSelf);
|
||||
void Vtb___024root___eval_initial(Vtb___024root* vlSelf);
|
||||
void Vtb___024root___eval_settle(Vtb___024root* vlSelf);
|
||||
void Vtb___024root___eval(Vtb___024root* vlSelf);
|
||||
|
||||
void Vtb::eval_step() {
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate Vtb::eval_step\n"); );
|
||||
#ifdef VL_DEBUG
|
||||
// Debug assertions
|
||||
Vtb___024root___eval_debug_assertions(&(vlSymsp->TOP));
|
||||
#endif // VL_DEBUG
|
||||
if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) {
|
||||
vlSymsp->__Vm_didInit = true;
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ Initial\n"););
|
||||
Vtb___024root___eval_static(&(vlSymsp->TOP));
|
||||
Vtb___024root___eval_initial(&(vlSymsp->TOP));
|
||||
Vtb___024root___eval_settle(&(vlSymsp->TOP));
|
||||
}
|
||||
// MTask 0 start
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("MTask0 starting\n"););
|
||||
Verilated::mtaskId(0);
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ Eval\n"););
|
||||
Vtb___024root___eval(&(vlSymsp->TOP));
|
||||
// Evaluate cleanup
|
||||
Verilated::endOfThreadMTask(vlSymsp->__Vm_evalMsgQp);
|
||||
Verilated::endOfEval(vlSymsp->__Vm_evalMsgQp);
|
||||
}
|
||||
|
||||
//============================================================
|
||||
// Events and timing
|
||||
bool Vtb::eventsPending() { return !vlSymsp->TOP.__VdlySched.empty(); }
|
||||
|
||||
uint64_t Vtb::nextTimeSlot() { return vlSymsp->TOP.__VdlySched.nextTimeSlot(); }
|
||||
|
||||
//============================================================
|
||||
// Utilities
|
||||
|
||||
const char* Vtb::name() const {
|
||||
return vlSymsp->name();
|
||||
}
|
||||
|
||||
//============================================================
|
||||
// Invoke final blocks
|
||||
|
||||
void Vtb___024root___eval_final(Vtb___024root* vlSelf);
|
||||
|
||||
VL_ATTR_COLD void Vtb::final() {
|
||||
Vtb___024root___eval_final(&(vlSymsp->TOP));
|
||||
}
|
||||
|
||||
//============================================================
|
||||
// Implementations of abstract methods from VerilatedModel
|
||||
|
||||
const char* Vtb::hierName() const { return vlSymsp->name(); }
|
||||
const char* Vtb::modelName() const { return "Vtb"; }
|
||||
unsigned Vtb::threads() const { return 1; }
|
||||
@ -1,72 +0,0 @@
|
||||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Primary model header
|
||||
//
|
||||
// This header should be included by all source files instantiating the design.
|
||||
// The class here is then constructed to instantiate the design.
|
||||
// See the Verilator manual for examples.
|
||||
|
||||
#ifndef VERILATED_VTB_H_
|
||||
#define VERILATED_VTB_H_ // guard
|
||||
|
||||
#include "verilated.h"
|
||||
|
||||
class Vtb__Syms;
|
||||
class Vtb___024root;
|
||||
|
||||
// This class is the main interface to the Verilated model
|
||||
class Vtb VL_NOT_FINAL : public VerilatedModel {
|
||||
private:
|
||||
// Symbol table holding complete model state (owned by this class)
|
||||
Vtb__Syms* const vlSymsp;
|
||||
|
||||
public:
|
||||
|
||||
// PORTS
|
||||
// The application code writes and reads these signals to
|
||||
// propagate new values into/out from the Verilated model.
|
||||
|
||||
// CELLS
|
||||
// Public to allow access to /* verilator public */ items.
|
||||
// Otherwise the application code can consider these internals.
|
||||
|
||||
// Root instance pointer to allow access to model internals,
|
||||
// including inlined /* verilator public_flat_* */ items.
|
||||
Vtb___024root* const rootp;
|
||||
|
||||
// CONSTRUCTORS
|
||||
/// Construct the model; called by application code
|
||||
/// If contextp is null, then the model will use the default global context
|
||||
/// If name is "", then makes a wrapper with a
|
||||
/// single model invisible with respect to DPI scope names.
|
||||
explicit Vtb(VerilatedContext* contextp, const char* name = "TOP");
|
||||
explicit Vtb(const char* name = "TOP");
|
||||
/// Destroy the model; called (often implicitly) by application code
|
||||
virtual ~Vtb();
|
||||
private:
|
||||
VL_UNCOPYABLE(Vtb); ///< Copying not allowed
|
||||
|
||||
public:
|
||||
// API METHODS
|
||||
/// Evaluate the model. Application must call when inputs change.
|
||||
void eval() { eval_step(); }
|
||||
/// Evaluate when calling multiple units/models per time step.
|
||||
void eval_step();
|
||||
/// Evaluate at end of a timestep for tracing, when using eval_step().
|
||||
/// Application must call after all eval() and before time changes.
|
||||
void eval_end_step() {}
|
||||
/// Simulation complete, run final blocks. Application must call on completion.
|
||||
void final();
|
||||
/// Are there scheduled events to handle?
|
||||
bool eventsPending();
|
||||
/// Returns time at next time slot. Aborts if !eventsPending()
|
||||
uint64_t nextTimeSlot();
|
||||
/// Retrieve name of this model instance (as passed to constructor).
|
||||
const char* name() const;
|
||||
|
||||
// Abstract methods from VerilatedModel
|
||||
const char* hierName() const override final;
|
||||
const char* modelName() const override final;
|
||||
unsigned threads() const override final;
|
||||
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);
|
||||
|
||||
#endif // guard
|
||||
@ -1,65 +0,0 @@
|
||||
# Verilated -*- Makefile -*-
|
||||
# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable
|
||||
#
|
||||
# Execute this makefile from the object directory:
|
||||
# make -f Vtb.mk
|
||||
|
||||
default: Vtb
|
||||
|
||||
### Constants...
|
||||
# Perl executable (from $PERL)
|
||||
PERL = perl
|
||||
# Path to Verilator kit (from $VERILATOR_ROOT)
|
||||
VERILATOR_ROOT = /usr/share/verilator
|
||||
# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE)
|
||||
SYSTEMC_INCLUDE ?=
|
||||
# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR)
|
||||
SYSTEMC_LIBDIR ?=
|
||||
|
||||
### Switches...
|
||||
# C++ code coverage 0/1 (from --prof-c)
|
||||
VM_PROFC = 0
|
||||
# SystemC output mode? 0/1 (from --sc)
|
||||
VM_SC = 0
|
||||
# Legacy or SystemC output mode? 0/1 (from --sc)
|
||||
VM_SP_OR_SC = $(VM_SC)
|
||||
# Deprecated
|
||||
VM_PCLI = 1
|
||||
# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH)
|
||||
VM_SC_TARGET_ARCH = linux
|
||||
|
||||
### Vars...
|
||||
# Design prefix (from --prefix)
|
||||
VM_PREFIX = Vtb
|
||||
# Module prefix (from --prefix)
|
||||
VM_MODPREFIX = Vtb
|
||||
# User CFLAGS (from -CFLAGS on Verilator command line)
|
||||
VM_USER_CFLAGS = \
|
||||
-DVL_TIME_CONTEXT \
|
||||
|
||||
# User LDLIBS (from -LDFLAGS on Verilator command line)
|
||||
VM_USER_LDLIBS = \
|
||||
|
||||
# User .cpp files (from .cpp's on Verilator command line)
|
||||
VM_USER_CLASSES = \
|
||||
|
||||
# User .cpp directories (from .cpp's on Verilator command line)
|
||||
VM_USER_DIR = \
|
||||
|
||||
|
||||
### Default rules...
|
||||
# Include list of all generated classes
|
||||
include Vtb_classes.mk
|
||||
# Include global rules
|
||||
include $(VERILATOR_ROOT)/include/verilated.mk
|
||||
|
||||
### Executable rules... (from --exe)
|
||||
VPATH += $(VM_USER_DIR)
|
||||
|
||||
|
||||
### Link rules... (from --exe)
|
||||
Vtb: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a $(VM_HIER_LIBS)
|
||||
$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) $(LIBS) $(SC_LIBS) -o $@
|
||||
|
||||
|
||||
# Verilated -*- Makefile -*-
|
||||
Binary file not shown.
@ -1,10 +0,0 @@
|
||||
// DESCRIPTION: Generated by verilator_includer via makefile
|
||||
#define VL_INCLUDE_OPT include
|
||||
#include "Vtb.cpp"
|
||||
#include "Vtb___024root__DepSet_hfe20aad3__0.cpp"
|
||||
#include "Vtb___024root__DepSet_ha183790c__0.cpp"
|
||||
#include "Vtb__main.cpp"
|
||||
#include "Vtb___024root__Slow.cpp"
|
||||
#include "Vtb___024root__DepSet_hfe20aad3__0__Slow.cpp"
|
||||
#include "Vtb___024root__DepSet_ha183790c__0__Slow.cpp"
|
||||
#include "Vtb__Syms.cpp"
|
||||
@ -1,12 +0,0 @@
|
||||
Vtb__ALL.o: Vtb__ALL.cpp Vtb.cpp Vtb.h \
|
||||
/usr/share/verilator/include/verilated.h \
|
||||
/usr/share/verilator/include/verilatedos.h \
|
||||
/usr/share/verilator/include/verilated_config.h \
|
||||
/usr/share/verilator/include/verilated_types.h \
|
||||
/usr/share/verilator/include/verilated_funcs.h Vtb__Syms.h \
|
||||
Vtb___024root.h /usr/share/verilator/include/verilated_timing.h \
|
||||
/usr/share/verilator/include/verilated.h \
|
||||
Vtb___024root__DepSet_hfe20aad3__0.cpp \
|
||||
Vtb___024root__DepSet_ha183790c__0.cpp Vtb__main.cpp \
|
||||
Vtb___024root__Slow.cpp Vtb___024root__DepSet_hfe20aad3__0__Slow.cpp \
|
||||
Vtb___024root__DepSet_ha183790c__0__Slow.cpp Vtb__Syms.cpp
|
||||
Binary file not shown.
@ -1,26 +0,0 @@
|
||||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Symbol table implementation internals
|
||||
|
||||
#include "Vtb__Syms.h"
|
||||
#include "Vtb.h"
|
||||
#include "Vtb___024root.h"
|
||||
|
||||
// FUNCTIONS
|
||||
Vtb__Syms::~Vtb__Syms()
|
||||
{
|
||||
}
|
||||
|
||||
Vtb__Syms::Vtb__Syms(VerilatedContext* contextp, const char* namep, Vtb* modelp)
|
||||
: VerilatedSyms{contextp}
|
||||
// Setup internal state of the Syms class
|
||||
, __Vm_modelp{modelp}
|
||||
// Setup module instances
|
||||
, TOP{this, namep}
|
||||
{
|
||||
// Configure time unit / time precision
|
||||
_vm_contextp__->timeunit(-12);
|
||||
_vm_contextp__->timeprecision(-12);
|
||||
// Setup each module's pointers to their submodules
|
||||
// Setup each module's pointer back to symbol table (for public functions)
|
||||
TOP.__Vconfigure(true);
|
||||
}
|
||||
@ -1,37 +0,0 @@
|
||||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Symbol table internal header
|
||||
//
|
||||
// Internal details; most calling programs do not need this header,
|
||||
// unless using verilator public meta comments.
|
||||
|
||||
#ifndef VERILATED_VTB__SYMS_H_
|
||||
#define VERILATED_VTB__SYMS_H_ // guard
|
||||
|
||||
#include "verilated.h"
|
||||
|
||||
// INCLUDE MODEL CLASS
|
||||
|
||||
#include "Vtb.h"
|
||||
|
||||
// INCLUDE MODULE CLASSES
|
||||
#include "Vtb___024root.h"
|
||||
|
||||
// SYMS CLASS (contains all model state)
|
||||
class Vtb__Syms final : public VerilatedSyms {
|
||||
public:
|
||||
// INTERNAL STATE
|
||||
Vtb* const __Vm_modelp;
|
||||
bool __Vm_didInit = false;
|
||||
|
||||
// MODULE INSTANCE STATE
|
||||
Vtb___024root TOP;
|
||||
|
||||
// CONSTRUCTORS
|
||||
Vtb__Syms(VerilatedContext* contextp, const char* namep, Vtb* modelp);
|
||||
~Vtb__Syms();
|
||||
|
||||
// METHODS
|
||||
const char* name() { return TOP.name(); }
|
||||
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);
|
||||
|
||||
#endif // guard
|
||||
@ -1,52 +0,0 @@
|
||||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Design internal header
|
||||
// See Vtb.h for the primary calling header
|
||||
|
||||
#ifndef VERILATED_VTB___024ROOT_H_
|
||||
#define VERILATED_VTB___024ROOT_H_ // guard
|
||||
|
||||
#include "verilated.h"
|
||||
#include "verilated_timing.h"
|
||||
|
||||
class Vtb__Syms;
|
||||
|
||||
class Vtb___024root final : public VerilatedModule {
|
||||
public:
|
||||
|
||||
// DESIGN SPECIFIC STATE
|
||||
CData/*0:0*/ tb__DOT__clk;
|
||||
CData/*0:0*/ tb__DOT__bitti_mi;
|
||||
CData/*2:0*/ tb__DOT__parca;
|
||||
CData/*4:0*/ tb__DOT__yukseklik;
|
||||
CData/*4:0*/ tb__DOT__cevrim;
|
||||
CData/*4:0*/ tb__DOT__uut__DOT__cevrim_r;
|
||||
CData/*4:0*/ tb__DOT__uut__DOT__y_0;
|
||||
CData/*4:0*/ tb__DOT__uut__DOT__y_1;
|
||||
CData/*4:0*/ tb__DOT__uut__DOT__y_2;
|
||||
CData/*4:0*/ __Vdly__tb__DOT__uut__DOT__y_0;
|
||||
CData/*4:0*/ __Vdly__tb__DOT__uut__DOT__y_1;
|
||||
CData/*4:0*/ __Vdly__tb__DOT__uut__DOT__y_2;
|
||||
CData/*0:0*/ __Vtrigrprev__TOP__tb__DOT__clk;
|
||||
CData/*0:0*/ __Vtrigrprev__TOP__tb__DOT__bitti_mi;
|
||||
CData/*0:0*/ __VactContinue;
|
||||
IData/*31:0*/ __VstlIterCount;
|
||||
IData/*31:0*/ __VactIterCount;
|
||||
VlDelayScheduler __VdlySched;
|
||||
VlTriggerVec<1> __VstlTriggered;
|
||||
VlTriggerVec<3> __VactTriggered;
|
||||
VlTriggerVec<3> __VnbaTriggered;
|
||||
|
||||
// INTERNAL VARIABLES
|
||||
Vtb__Syms* const vlSymsp;
|
||||
|
||||
// CONSTRUCTORS
|
||||
Vtb___024root(Vtb__Syms* symsp, const char* v__name);
|
||||
~Vtb___024root();
|
||||
VL_UNCOPYABLE(Vtb___024root);
|
||||
|
||||
// INTERNAL METHODS
|
||||
void __Vconfigure(bool first);
|
||||
} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES);
|
||||
|
||||
|
||||
#endif // guard
|
||||
@ -1,201 +0,0 @@
|
||||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Design implementation internals
|
||||
// See Vtb.h for the primary calling header
|
||||
|
||||
#include "verilated.h"
|
||||
|
||||
#include "Vtb___024root.h"
|
||||
|
||||
VlCoroutine Vtb___024root___eval_initial__TOP__0(Vtb___024root* vlSelf);
|
||||
|
||||
void Vtb___024root___eval_initial(Vtb___024root* vlSelf) {
|
||||
if (false && vlSelf) {} // Prevent unused
|
||||
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_initial\n"); );
|
||||
// Body
|
||||
Vtb___024root___eval_initial__TOP__0(vlSelf);
|
||||
vlSelf->__Vtrigrprev__TOP__tb__DOT__clk = vlSelf->tb__DOT__clk;
|
||||
vlSelf->__Vtrigrprev__TOP__tb__DOT__bitti_mi = vlSelf->tb__DOT__bitti_mi;
|
||||
}
|
||||
|
||||
VL_INLINE_OPT VlCoroutine Vtb___024root___eval_initial__TOP__0(Vtb___024root* vlSelf) {
|
||||
if (false && vlSelf) {} // Prevent unused
|
||||
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_initial__TOP__0\n"); );
|
||||
// Body
|
||||
while (1U) {
|
||||
co_await vlSelf->__VdlySched.delay(5U, "tb.v",
|
||||
20);
|
||||
vlSelf->tb__DOT__clk = (1U & (~ (IData)(vlSelf->tb__DOT__clk)));
|
||||
}
|
||||
vlSelf->tb__DOT__parca = 5U;
|
||||
co_await vlSelf->__VdlySched.delay(0xc8U, "tb.v",
|
||||
21);
|
||||
VL_WRITEF("%2#\n%2#\n%1#\n",5,vlSelf->tb__DOT__yukseklik,
|
||||
5,(IData)(vlSelf->tb__DOT__uut__DOT__cevrim_r),
|
||||
1,vlSelf->tb__DOT__bitti_mi);
|
||||
VL_FINISH_MT("tb.v", 25, "");
|
||||
}
|
||||
|
||||
void Vtb___024root___eval_act(Vtb___024root* vlSelf) {
|
||||
if (false && vlSelf) {} // Prevent unused
|
||||
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_act\n"); );
|
||||
}
|
||||
|
||||
VL_INLINE_OPT void Vtb___024root___nba_sequent__TOP__0(Vtb___024root* vlSelf) {
|
||||
if (false && vlSelf) {} // Prevent unused
|
||||
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___nba_sequent__TOP__0\n"); );
|
||||
// Body
|
||||
vlSelf->__Vdly__tb__DOT__uut__DOT__y_2 = vlSelf->tb__DOT__uut__DOT__y_2;
|
||||
vlSelf->__Vdly__tb__DOT__uut__DOT__y_1 = vlSelf->tb__DOT__uut__DOT__y_1;
|
||||
vlSelf->__Vdly__tb__DOT__uut__DOT__y_0 = vlSelf->tb__DOT__uut__DOT__y_0;
|
||||
if ((0x10U != (IData)(vlSelf->tb__DOT__uut__DOT__cevrim_r))) {
|
||||
vlSelf->__Vdly__tb__DOT__uut__DOT__y_2 = (0x1fU
|
||||
& ((IData)(vlSelf->tb__DOT__uut__DOT__y_2)
|
||||
+
|
||||
(1U
|
||||
& ((IData)(vlSelf->tb__DOT__parca)
|
||||
>> 2U))));
|
||||
vlSelf->__Vdly__tb__DOT__uut__DOT__y_1 = (0x1fU
|
||||
& ((IData)(vlSelf->tb__DOT__uut__DOT__y_1)
|
||||
+
|
||||
(1U
|
||||
& ((IData)(vlSelf->tb__DOT__parca)
|
||||
>> 1U))));
|
||||
vlSelf->__Vdly__tb__DOT__uut__DOT__y_0 = (0x1fU
|
||||
& ((IData)(vlSelf->tb__DOT__uut__DOT__y_0)
|
||||
+
|
||||
(1U
|
||||
& (IData)(vlSelf->tb__DOT__parca))));
|
||||
}
|
||||
if ((0x10U != (IData)(vlSelf->tb__DOT__cevrim))) {
|
||||
vlSelf->tb__DOT__uut__DOT__cevrim_r = (0x1fU
|
||||
& ((IData)(1U)
|
||||
+ (IData)(vlSelf->tb__DOT__uut__DOT__cevrim_r)));
|
||||
}
|
||||
vlSelf->tb__DOT__cevrim = vlSelf->tb__DOT__uut__DOT__cevrim_r;
|
||||
vlSelf->tb__DOT__bitti_mi = (0x10U == (IData)(vlSelf->tb__DOT__uut__DOT__cevrim_r));
|
||||
}
|
||||
|
||||
VL_INLINE_OPT void Vtb___024root___nba_sequent__TOP__1(Vtb___024root* vlSelf) {
|
||||
if (false && vlSelf) {} // Prevent unused
|
||||
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___nba_sequent__TOP__1\n"); );
|
||||
// Body
|
||||
if (((IData)(vlSelf->tb__DOT__uut__DOT__y_0) > (IData)(vlSelf->tb__DOT__uut__DOT__y_1))) {
|
||||
vlSelf->tb__DOT__yukseklik = (((IData)(vlSelf->tb__DOT__uut__DOT__y_0)
|
||||
> (IData)(vlSelf->tb__DOT__uut__DOT__y_2))
|
||||
? (IData)(vlSelf->tb__DOT__uut__DOT__y_0)
|
||||
: (IData)(vlSelf->tb__DOT__uut__DOT__y_2));
|
||||
} else if (((IData)(vlSelf->tb__DOT__uut__DOT__y_0)
|
||||
> (IData)(vlSelf->tb__DOT__uut__DOT__y_1))) {
|
||||
vlSelf->tb__DOT__yukseklik = (((IData)(vlSelf->tb__DOT__uut__DOT__y_1)
|
||||
> (IData)(vlSelf->tb__DOT__uut__DOT__y_2))
|
||||
? (IData)(vlSelf->tb__DOT__uut__DOT__y_1)
|
||||
: (IData)(vlSelf->tb__DOT__uut__DOT__y_2));
|
||||
}
|
||||
}
|
||||
|
||||
VL_INLINE_OPT void Vtb___024root___nba_sequent__TOP__2(Vtb___024root* vlSelf) {
|
||||
if (false && vlSelf) {} // Prevent unused
|
||||
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___nba_sequent__TOP__2\n"); );
|
||||
// Body
|
||||
vlSelf->tb__DOT__uut__DOT__y_0 = vlSelf->__Vdly__tb__DOT__uut__DOT__y_0;
|
||||
vlSelf->tb__DOT__uut__DOT__y_1 = vlSelf->__Vdly__tb__DOT__uut__DOT__y_1;
|
||||
vlSelf->tb__DOT__uut__DOT__y_2 = vlSelf->__Vdly__tb__DOT__uut__DOT__y_2;
|
||||
}
|
||||
|
||||
void Vtb___024root___eval_nba(Vtb___024root* vlSelf) {
|
||||
if (false && vlSelf) {} // Prevent unused
|
||||
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_nba\n"); );
|
||||
// Body
|
||||
if (vlSelf->__VnbaTriggered.at(0U)) {
|
||||
Vtb___024root___nba_sequent__TOP__0(vlSelf);
|
||||
}
|
||||
if (vlSelf->__VnbaTriggered.at(1U)) {
|
||||
Vtb___024root___nba_sequent__TOP__1(vlSelf);
|
||||
}
|
||||
if (vlSelf->__VnbaTriggered.at(0U)) {
|
||||
Vtb___024root___nba_sequent__TOP__2(vlSelf);
|
||||
}
|
||||
}
|
||||
|
||||
void Vtb___024root___eval_triggers__act(Vtb___024root* vlSelf);
|
||||
#ifdef VL_DEBUG
|
||||
VL_ATTR_COLD void Vtb___024root___dump_triggers__act(Vtb___024root* vlSelf);
|
||||
#endif // VL_DEBUG
|
||||
void Vtb___024root___timing_resume(Vtb___024root* vlSelf);
|
||||
#ifdef VL_DEBUG
|
||||
VL_ATTR_COLD void Vtb___024root___dump_triggers__nba(Vtb___024root* vlSelf);
|
||||
#endif // VL_DEBUG
|
||||
|
||||
void Vtb___024root___eval(Vtb___024root* vlSelf) {
|
||||
if (false && vlSelf) {} // Prevent unused
|
||||
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval\n"); );
|
||||
// Init
|
||||
VlTriggerVec<3> __VpreTriggered;
|
||||
IData/*31:0*/ __VnbaIterCount;
|
||||
CData/*0:0*/ __VnbaContinue;
|
||||
// Body
|
||||
__VnbaIterCount = 0U;
|
||||
__VnbaContinue = 1U;
|
||||
while (__VnbaContinue) {
|
||||
__VnbaContinue = 0U;
|
||||
vlSelf->__VnbaTriggered.clear();
|
||||
vlSelf->__VactIterCount = 0U;
|
||||
vlSelf->__VactContinue = 1U;
|
||||
while (vlSelf->__VactContinue) {
|
||||
vlSelf->__VactContinue = 0U;
|
||||
Vtb___024root___eval_triggers__act(vlSelf);
|
||||
if (vlSelf->__VactTriggered.any()) {
|
||||
vlSelf->__VactContinue = 1U;
|
||||
if (VL_UNLIKELY((0x64U < vlSelf->__VactIterCount))) {
|
||||
#ifdef VL_DEBUG
|
||||
Vtb___024root___dump_triggers__act(vlSelf);
|
||||
#endif
|
||||
VL_FATAL_MT("tb.v", 1, "", "Active region did not converge.");
|
||||
}
|
||||
vlSelf->__VactIterCount = ((IData)(1U)
|
||||
+ vlSelf->__VactIterCount);
|
||||
__VpreTriggered.andNot(vlSelf->__VactTriggered, vlSelf->__VnbaTriggered);
|
||||
vlSelf->__VnbaTriggered.set(vlSelf->__VactTriggered);
|
||||
Vtb___024root___timing_resume(vlSelf);
|
||||
Vtb___024root___eval_act(vlSelf);
|
||||
}
|
||||
}
|
||||
if (vlSelf->__VnbaTriggered.any()) {
|
||||
__VnbaContinue = 1U;
|
||||
if (VL_UNLIKELY((0x64U < __VnbaIterCount))) {
|
||||
#ifdef VL_DEBUG
|
||||
Vtb___024root___dump_triggers__nba(vlSelf);
|
||||
#endif
|
||||
VL_FATAL_MT("tb.v", 1, "", "NBA region did not converge.");
|
||||
}
|
||||
__VnbaIterCount = ((IData)(1U) + __VnbaIterCount);
|
||||
Vtb___024root___eval_nba(vlSelf);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void Vtb___024root___timing_resume(Vtb___024root* vlSelf) {
|
||||
if (false && vlSelf) {} // Prevent unused
|
||||
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___timing_resume\n"); );
|
||||
// Body
|
||||
if (vlSelf->__VactTriggered.at(2U)) {
|
||||
vlSelf->__VdlySched.resume();
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef VL_DEBUG
|
||||
void Vtb___024root___eval_debug_assertions(Vtb___024root* vlSelf) {
|
||||
if (false && vlSelf) {} // Prevent unused
|
||||
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_debug_assertions\n"); );
|
||||
}
|
||||
#endif // VL_DEBUG
|
||||
@ -1,165 +0,0 @@
|
||||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Design implementation internals
|
||||
// See Vtb.h for the primary calling header
|
||||
|
||||
#include "verilated.h"
|
||||
|
||||
#include "Vtb___024root.h"
|
||||
|
||||
VL_ATTR_COLD void Vtb___024root___eval_static__TOP(Vtb___024root* vlSelf);
|
||||
|
||||
VL_ATTR_COLD void Vtb___024root___eval_static(Vtb___024root* vlSelf) {
|
||||
if (false && vlSelf) {} // Prevent unused
|
||||
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_static\n"); );
|
||||
// Body
|
||||
Vtb___024root___eval_static__TOP(vlSelf);
|
||||
}
|
||||
|
||||
VL_ATTR_COLD void Vtb___024root___eval_static__TOP(Vtb___024root* vlSelf) {
|
||||
if (false && vlSelf) {} // Prevent unused
|
||||
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_static__TOP\n"); );
|
||||
// Body
|
||||
vlSelf->tb__DOT__clk = 0U;
|
||||
vlSelf->tb__DOT__uut__DOT__cevrim_r = 0U;
|
||||
vlSelf->tb__DOT__uut__DOT__y_0 = 0U;
|
||||
vlSelf->tb__DOT__uut__DOT__y_1 = 0U;
|
||||
vlSelf->tb__DOT__uut__DOT__y_2 = 0U;
|
||||
}
|
||||
|
||||
VL_ATTR_COLD void Vtb___024root___eval_final(Vtb___024root* vlSelf) {
|
||||
if (false && vlSelf) {} // Prevent unused
|
||||
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_final\n"); );
|
||||
}
|
||||
|
||||
VL_ATTR_COLD void Vtb___024root___eval_triggers__stl(Vtb___024root* vlSelf);
|
||||
#ifdef VL_DEBUG
|
||||
VL_ATTR_COLD void Vtb___024root___dump_triggers__stl(Vtb___024root* vlSelf);
|
||||
#endif // VL_DEBUG
|
||||
VL_ATTR_COLD void Vtb___024root___eval_stl(Vtb___024root* vlSelf);
|
||||
|
||||
VL_ATTR_COLD void Vtb___024root___eval_settle(Vtb___024root* vlSelf) {
|
||||
if (false && vlSelf) {} // Prevent unused
|
||||
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_settle\n"); );
|
||||
// Init
|
||||
CData/*0:0*/ __VstlContinue;
|
||||
// Body
|
||||
vlSelf->__VstlIterCount = 0U;
|
||||
__VstlContinue = 1U;
|
||||
while (__VstlContinue) {
|
||||
__VstlContinue = 0U;
|
||||
Vtb___024root___eval_triggers__stl(vlSelf);
|
||||
if (vlSelf->__VstlTriggered.any()) {
|
||||
__VstlContinue = 1U;
|
||||
if (VL_UNLIKELY((0x64U < vlSelf->__VstlIterCount))) {
|
||||
#ifdef VL_DEBUG
|
||||
Vtb___024root___dump_triggers__stl(vlSelf);
|
||||
#endif
|
||||
VL_FATAL_MT("tb.v", 1, "", "Settle region did not converge.");
|
||||
}
|
||||
vlSelf->__VstlIterCount = ((IData)(1U)
|
||||
+ vlSelf->__VstlIterCount);
|
||||
Vtb___024root___eval_stl(vlSelf);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef VL_DEBUG
|
||||
VL_ATTR_COLD void Vtb___024root___dump_triggers__stl(Vtb___024root* vlSelf) {
|
||||
if (false && vlSelf) {} // Prevent unused
|
||||
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___dump_triggers__stl\n"); );
|
||||
// Body
|
||||
if ((1U & (~ (IData)(vlSelf->__VstlTriggered.any())))) {
|
||||
VL_DBG_MSGF(" No triggers active\n");
|
||||
}
|
||||
if (vlSelf->__VstlTriggered.at(0U)) {
|
||||
VL_DBG_MSGF(" 'stl' region trigger index 0 is active: Internal 'stl' trigger - first iteration\n");
|
||||
}
|
||||
}
|
||||
#endif // VL_DEBUG
|
||||
|
||||
VL_ATTR_COLD void Vtb___024root___stl_sequent__TOP__0(Vtb___024root* vlSelf) {
|
||||
if (false && vlSelf) {} // Prevent unused
|
||||
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___stl_sequent__TOP__0\n"); );
|
||||
// Body
|
||||
vlSelf->tb__DOT__cevrim = vlSelf->tb__DOT__uut__DOT__cevrim_r;
|
||||
vlSelf->tb__DOT__bitti_mi = (0x10U == (IData)(vlSelf->tb__DOT__uut__DOT__cevrim_r));
|
||||
}
|
||||
|
||||
VL_ATTR_COLD void Vtb___024root___eval_stl(Vtb___024root* vlSelf) {
|
||||
if (false && vlSelf) {} // Prevent unused
|
||||
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_stl\n"); );
|
||||
// Body
|
||||
if (vlSelf->__VstlTriggered.at(0U)) {
|
||||
Vtb___024root___stl_sequent__TOP__0(vlSelf);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef VL_DEBUG
|
||||
VL_ATTR_COLD void Vtb___024root___dump_triggers__act(Vtb___024root* vlSelf) {
|
||||
if (false && vlSelf) {} // Prevent unused
|
||||
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___dump_triggers__act\n"); );
|
||||
// Body
|
||||
if ((1U & (~ (IData)(vlSelf->__VactTriggered.any())))) {
|
||||
VL_DBG_MSGF(" No triggers active\n");
|
||||
}
|
||||
if (vlSelf->__VactTriggered.at(0U)) {
|
||||
VL_DBG_MSGF(" 'act' region trigger index 0 is active: @(posedge tb.clk)\n");
|
||||
}
|
||||
if (vlSelf->__VactTriggered.at(1U)) {
|
||||
VL_DBG_MSGF(" 'act' region trigger index 1 is active: @(posedge tb.bitti_mi)\n");
|
||||
}
|
||||
if (vlSelf->__VactTriggered.at(2U)) {
|
||||
VL_DBG_MSGF(" 'act' region trigger index 2 is active: @([true] __VdlySched.awaitingCurrentTime())\n");
|
||||
}
|
||||
}
|
||||
#endif // VL_DEBUG
|
||||
|
||||
#ifdef VL_DEBUG
|
||||
VL_ATTR_COLD void Vtb___024root___dump_triggers__nba(Vtb___024root* vlSelf) {
|
||||
if (false && vlSelf) {} // Prevent unused
|
||||
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___dump_triggers__nba\n"); );
|
||||
// Body
|
||||
if ((1U & (~ (IData)(vlSelf->__VnbaTriggered.any())))) {
|
||||
VL_DBG_MSGF(" No triggers active\n");
|
||||
}
|
||||
if (vlSelf->__VnbaTriggered.at(0U)) {
|
||||
VL_DBG_MSGF(" 'nba' region trigger index 0 is active: @(posedge tb.clk)\n");
|
||||
}
|
||||
if (vlSelf->__VnbaTriggered.at(1U)) {
|
||||
VL_DBG_MSGF(" 'nba' region trigger index 1 is active: @(posedge tb.bitti_mi)\n");
|
||||
}
|
||||
if (vlSelf->__VnbaTriggered.at(2U)) {
|
||||
VL_DBG_MSGF(" 'nba' region trigger index 2 is active: @([true] __VdlySched.awaitingCurrentTime())\n");
|
||||
}
|
||||
}
|
||||
#endif // VL_DEBUG
|
||||
|
||||
VL_ATTR_COLD void Vtb___024root___ctor_var_reset(Vtb___024root* vlSelf) {
|
||||
if (false && vlSelf) {} // Prevent unused
|
||||
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___ctor_var_reset\n"); );
|
||||
// Body
|
||||
vlSelf->tb__DOT__parca = VL_RAND_RESET_I(3);
|
||||
vlSelf->tb__DOT__clk = VL_RAND_RESET_I(1);
|
||||
vlSelf->tb__DOT__yukseklik = VL_RAND_RESET_I(5);
|
||||
vlSelf->tb__DOT__cevrim = VL_RAND_RESET_I(5);
|
||||
vlSelf->tb__DOT__bitti_mi = VL_RAND_RESET_I(1);
|
||||
vlSelf->tb__DOT__uut__DOT__cevrim_r = VL_RAND_RESET_I(5);
|
||||
vlSelf->tb__DOT__uut__DOT__y_0 = VL_RAND_RESET_I(5);
|
||||
vlSelf->tb__DOT__uut__DOT__y_1 = VL_RAND_RESET_I(5);
|
||||
vlSelf->tb__DOT__uut__DOT__y_2 = VL_RAND_RESET_I(5);
|
||||
vlSelf->__Vdly__tb__DOT__uut__DOT__y_0 = VL_RAND_RESET_I(5);
|
||||
vlSelf->__Vdly__tb__DOT__uut__DOT__y_1 = VL_RAND_RESET_I(5);
|
||||
vlSelf->__Vdly__tb__DOT__uut__DOT__y_2 = VL_RAND_RESET_I(5);
|
||||
vlSelf->__Vtrigrprev__TOP__tb__DOT__clk = VL_RAND_RESET_I(1);
|
||||
vlSelf->__Vtrigrprev__TOP__tb__DOT__bitti_mi = VL_RAND_RESET_I(1);
|
||||
}
|
||||
@ -1,31 +0,0 @@
|
||||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Design implementation internals
|
||||
// See Vtb.h for the primary calling header
|
||||
|
||||
#include "verilated.h"
|
||||
|
||||
#include "Vtb__Syms.h"
|
||||
#include "Vtb___024root.h"
|
||||
|
||||
#ifdef VL_DEBUG
|
||||
VL_ATTR_COLD void Vtb___024root___dump_triggers__act(Vtb___024root* vlSelf);
|
||||
#endif // VL_DEBUG
|
||||
|
||||
void Vtb___024root___eval_triggers__act(Vtb___024root* vlSelf) {
|
||||
if (false && vlSelf) {} // Prevent unused
|
||||
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_triggers__act\n"); );
|
||||
// Body
|
||||
vlSelf->__VactTriggered.at(0U) = ((IData)(vlSelf->tb__DOT__clk)
|
||||
& (~ (IData)(vlSelf->__Vtrigrprev__TOP__tb__DOT__clk)));
|
||||
vlSelf->__VactTriggered.at(1U) = ((IData)(vlSelf->tb__DOT__bitti_mi)
|
||||
& (~ (IData)(vlSelf->__Vtrigrprev__TOP__tb__DOT__bitti_mi)));
|
||||
vlSelf->__VactTriggered.at(2U) = vlSelf->__VdlySched.awaitingCurrentTime();
|
||||
vlSelf->__Vtrigrprev__TOP__tb__DOT__clk = vlSelf->tb__DOT__clk;
|
||||
vlSelf->__Vtrigrprev__TOP__tb__DOT__bitti_mi = vlSelf->tb__DOT__bitti_mi;
|
||||
#ifdef VL_DEBUG
|
||||
if (VL_UNLIKELY(vlSymsp->_vm_contextp__->debug())) {
|
||||
Vtb___024root___dump_triggers__act(vlSelf);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
@ -1,25 +0,0 @@
|
||||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Design implementation internals
|
||||
// See Vtb.h for the primary calling header
|
||||
|
||||
#include "verilated.h"
|
||||
|
||||
#include "Vtb__Syms.h"
|
||||
#include "Vtb___024root.h"
|
||||
|
||||
#ifdef VL_DEBUG
|
||||
VL_ATTR_COLD void Vtb___024root___dump_triggers__stl(Vtb___024root* vlSelf);
|
||||
#endif // VL_DEBUG
|
||||
|
||||
VL_ATTR_COLD void Vtb___024root___eval_triggers__stl(Vtb___024root* vlSelf) {
|
||||
if (false && vlSelf) {} // Prevent unused
|
||||
Vtb__Syms* const __restrict vlSymsp VL_ATTR_UNUSED = vlSelf->vlSymsp;
|
||||
VL_DEBUG_IF(VL_DBG_MSGF("+ Vtb___024root___eval_triggers__stl\n"); );
|
||||
// Body
|
||||
vlSelf->__VstlTriggered.at(0U) = (0U == vlSelf->__VstlIterCount);
|
||||
#ifdef VL_DEBUG
|
||||
if (VL_UNLIKELY(vlSymsp->_vm_contextp__->debug())) {
|
||||
Vtb___024root___dump_triggers__stl(vlSelf);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
@ -1,26 +0,0 @@
|
||||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: Verilator output: Design implementation internals
|
||||
// See Vtb.h for the primary calling header
|
||||
|
||||
#include "verilated.h"
|
||||
|
||||
#include "Vtb__Syms.h"
|
||||
#include "Vtb___024root.h"
|
||||
|
||||
void Vtb___024root___ctor_var_reset(Vtb___024root* vlSelf);
|
||||
|
||||
Vtb___024root::Vtb___024root(Vtb__Syms* symsp, const char* v__name)
|
||||
: VerilatedModule{v__name}
|
||||
, __VdlySched{*symsp->_vm_contextp__}
|
||||
, vlSymsp{symsp}
|
||||
{
|
||||
// Reset structure values
|
||||
Vtb___024root___ctor_var_reset(this);
|
||||
}
|
||||
|
||||
void Vtb___024root::__Vconfigure(bool first) {
|
||||
if (false && first) {} // Prevent unused
|
||||
}
|
||||
|
||||
Vtb___024root::~Vtb___024root() {
|
||||
}
|
||||
@ -1,34 +0,0 @@
|
||||
// Verilated -*- C++ -*-
|
||||
// DESCRIPTION: main() calling loop, created with Verilator --main
|
||||
|
||||
#include "verilated.h"
|
||||
#include "Vtb.h"
|
||||
|
||||
//======================
|
||||
|
||||
int main(int argc, char** argv, char**) {
|
||||
// Setup context, defaults, and parse command line
|
||||
Verilated::debug(0);
|
||||
const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
|
||||
contextp->commandArgs(argc, argv);
|
||||
|
||||
// Construct the Verilated model, from Vtop.h generated from Verilating
|
||||
const std::unique_ptr<Vtb> topp{new Vtb{contextp.get()}};
|
||||
|
||||
// Simulate until $finish
|
||||
while (!contextp->gotFinish()) {
|
||||
// Evaluate model
|
||||
topp->eval();
|
||||
// Advance time
|
||||
if (!topp->eventsPending()) break;
|
||||
contextp->time(topp->nextTimeSlot());
|
||||
}
|
||||
|
||||
if (!contextp->gotFinish()) {
|
||||
VL_DEBUG_IF(VL_PRINTF("+ Exiting without $finish; no events left\n"););
|
||||
}
|
||||
|
||||
// Final model cleanup
|
||||
topp->final();
|
||||
return 0;
|
||||
}
|
||||
@ -1 +0,0 @@
|
||||
obj_dir/Vtb.cpp obj_dir/Vtb.h obj_dir/Vtb.mk obj_dir/Vtb__Syms.cpp obj_dir/Vtb__Syms.h obj_dir/Vtb___024root.h obj_dir/Vtb___024root__DepSet_ha183790c__0.cpp obj_dir/Vtb___024root__DepSet_ha183790c__0__Slow.cpp obj_dir/Vtb___024root__DepSet_hfe20aad3__0.cpp obj_dir/Vtb___024root__DepSet_hfe20aad3__0__Slow.cpp obj_dir/Vtb___024root__Slow.cpp obj_dir/Vtb__main.cpp obj_dir/Vtb__ver.d obj_dir/Vtb_classes.mk : /usr/bin/verilator_bin /usr/bin/verilator_bin tb.v tetris.v
|
||||
@ -1,20 +0,0 @@
|
||||
# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will.
|
||||
C "--binary tb.v tetris.v --timing"
|
||||
S 12244816 28045 1719496600 881980186 1680199511 0 "/usr/bin/verilator_bin"
|
||||
T 2837 6675 1720894776 185681955 1720894776 185681955 "obj_dir/Vtb.cpp"
|
||||
T 2631 6439 1720894776 185681955 1720894776 185681955 "obj_dir/Vtb.h"
|
||||
T 1722 7381 1720894776 185681955 1720894776 185681955 "obj_dir/Vtb.mk"
|
||||
T 730 216 1720894776 185681955 1720894776 185681955 "obj_dir/Vtb__Syms.cpp"
|
||||
T 884 225 1720894776 185681955 1720894776 185681955 "obj_dir/Vtb__Syms.h"
|
||||
T 1524 6695 1720894776 185681955 1720894776 185681955 "obj_dir/Vtb___024root.h"
|
||||
T 9237 7333 1720894776 185681955 1720894776 185681955 "obj_dir/Vtb___024root__DepSet_ha183790c__0.cpp"
|
||||
T 6922 7184 1720894776 185681955 1720894776 185681955 "obj_dir/Vtb___024root__DepSet_ha183790c__0__Slow.cpp"
|
||||
T 1304 7283 1720894776 185681955 1720894776 185681955 "obj_dir/Vtb___024root__DepSet_hfe20aad3__0.cpp"
|
||||
T 823 7044 1720894776 185681955 1720894776 185681955 "obj_dir/Vtb___024root__DepSet_hfe20aad3__0__Slow.cpp"
|
||||
T 644 6712 1720894776 185681955 1720894776 185681955 "obj_dir/Vtb___024root__Slow.cpp"
|
||||
T 955 7337 1720894776 185681955 1720894776 185681955 "obj_dir/Vtb__main.cpp"
|
||||
T 471 7389 1720894776 185681955 1720894776 185681955 "obj_dir/Vtb__ver.d"
|
||||
T 0 0 1720894776 185681955 1720894776 185681955 "obj_dir/Vtb__verFiles.dat"
|
||||
T 1646 7340 1720894776 185681955 1720894776 185681955 "obj_dir/Vtb_classes.mk"
|
||||
S 376 233 1720894754 765684145 1720894754 765684145 "tb.v"
|
||||
S 820 230 1720894095 565675203 1720894095 565675203 "tetris.v"
|
||||
@ -1,54 +0,0 @@
|
||||
# Verilated -*- Makefile -*-
|
||||
# DESCRIPTION: Verilator output: Make include file with class lists
|
||||
#
|
||||
# This file lists generated Verilated files, for including in higher level makefiles.
|
||||
# See Vtb.mk for the caller.
|
||||
|
||||
### Switches...
|
||||
# C11 constructs required? 0/1 (always on now)
|
||||
VM_C11 = 1
|
||||
# Timing enabled? 0/1
|
||||
VM_TIMING = 1
|
||||
# Coverage output mode? 0/1 (from --coverage)
|
||||
VM_COVERAGE = 0
|
||||
# Parallel builds? 0/1 (from --output-split)
|
||||
VM_PARALLEL_BUILDS = 0
|
||||
# Tracing output mode? 0/1 (from --trace/--trace-fst)
|
||||
VM_TRACE = 0
|
||||
# Tracing output mode in VCD format? 0/1 (from --trace)
|
||||
VM_TRACE_VCD = 0
|
||||
# Tracing output mode in FST format? 0/1 (from --trace-fst)
|
||||
VM_TRACE_FST = 0
|
||||
|
||||
### Object file lists...
|
||||
# Generated module classes, fast-path, compile with highest optimization
|
||||
VM_CLASSES_FAST += \
|
||||
Vtb \
|
||||
Vtb___024root__DepSet_hfe20aad3__0 \
|
||||
Vtb___024root__DepSet_ha183790c__0 \
|
||||
Vtb__main \
|
||||
|
||||
# Generated module classes, non-fast-path, compile with low/medium optimization
|
||||
VM_CLASSES_SLOW += \
|
||||
Vtb___024root__Slow \
|
||||
Vtb___024root__DepSet_hfe20aad3__0__Slow \
|
||||
Vtb___024root__DepSet_ha183790c__0__Slow \
|
||||
|
||||
# Generated support classes, fast-path, compile with highest optimization
|
||||
VM_SUPPORT_FAST += \
|
||||
|
||||
# Generated support classes, non-fast-path, compile with low/medium optimization
|
||||
VM_SUPPORT_SLOW += \
|
||||
Vtb__Syms \
|
||||
|
||||
# Global classes, need linked once per executable, fast-path, compile with highest optimization
|
||||
VM_GLOBAL_FAST += \
|
||||
verilated \
|
||||
verilated_timing \
|
||||
verilated_threads \
|
||||
|
||||
# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization
|
||||
VM_GLOBAL_SLOW += \
|
||||
|
||||
|
||||
# Verilated -*- Makefile -*-
|
||||
@ -1,12 +0,0 @@
|
||||
verilated.o: /usr/share/verilator/include/verilated.cpp \
|
||||
/usr/share/verilator/include/verilated_config.h \
|
||||
/usr/share/verilator/include/verilatedos.h \
|
||||
/usr/share/verilator/include/verilated_imp.h \
|
||||
/usr/share/verilator/include/verilated.h \
|
||||
/usr/share/verilator/include/verilated_types.h \
|
||||
/usr/share/verilator/include/verilated_funcs.h \
|
||||
/usr/share/verilator/include/verilated_syms.h \
|
||||
/usr/share/verilator/include/verilated_sym_props.h \
|
||||
/usr/share/verilator/include/verilated_threads.h \
|
||||
/usr/share/verilator/include/verilated_trace.h \
|
||||
/usr/share/verilator/include/verilated_trace_defs.h
|
||||
Binary file not shown.
@ -1,7 +0,0 @@
|
||||
verilated_threads.o: /usr/share/verilator/include/verilated_threads.cpp \
|
||||
/usr/share/verilator/include/verilatedos.h \
|
||||
/usr/share/verilator/include/verilated_threads.h \
|
||||
/usr/share/verilator/include/verilated.h \
|
||||
/usr/share/verilator/include/verilated_config.h \
|
||||
/usr/share/verilator/include/verilated_types.h \
|
||||
/usr/share/verilator/include/verilated_funcs.h
|
||||
Binary file not shown.
@ -1,7 +0,0 @@
|
||||
verilated_timing.o: /usr/share/verilator/include/verilated_timing.cpp \
|
||||
/usr/share/verilator/include/verilated_timing.h \
|
||||
/usr/share/verilator/include/verilated.h \
|
||||
/usr/share/verilator/include/verilatedos.h \
|
||||
/usr/share/verilator/include/verilated_config.h \
|
||||
/usr/share/verilator/include/verilated_types.h \
|
||||
/usr/share/verilator/include/verilated_funcs.h
|
||||
Binary file not shown.
@ -1,5 +0,0 @@
|
||||
iverilog *.v && vvp a.out
|
||||
if [ -f "dump.vcd" ]; then
|
||||
gtkwave dump.vcd
|
||||
rm dump.vcd
|
||||
fi
|
||||
@ -1,45 +0,0 @@
|
||||
module tb();
|
||||
|
||||
reg [2:0] parca;
|
||||
reg clk = 0;
|
||||
|
||||
wire [4:0] yukseklik;
|
||||
wire [4:0] cevrim;
|
||||
wire bitti_mi;
|
||||
|
||||
tetris uut(
|
||||
.parca(parca),
|
||||
.clk(clk),
|
||||
.yukseklik(yukseklik),
|
||||
.cevrim(cevrim),
|
||||
.bitti_mi(bitti_mi)
|
||||
);
|
||||
|
||||
always begin
|
||||
clk = ~clk; #5;
|
||||
end
|
||||
|
||||
initial begin
|
||||
$dumpvars;
|
||||
parca = 3'b101; #10;
|
||||
parca = 3'b000; #10;
|
||||
parca = 3'b101; #10;
|
||||
parca = 3'b000; #10;
|
||||
parca = 3'b101; #10;
|
||||
parca = 3'b000; #10;
|
||||
parca = 3'b101; #10;
|
||||
parca = 3'b000; #10;
|
||||
parca = 3'b101; #10;
|
||||
parca = 3'b000; #10;
|
||||
parca = 3'b101; #10;
|
||||
parca = 3'b000; #10;
|
||||
parca = 3'b101; #10;
|
||||
parca = 3'b000; #10;
|
||||
parca = 3'b101; #10;
|
||||
parca = 3'b000; #10;
|
||||
parca = 3'b101; #10;
|
||||
parca = 3'b000; #10;
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
@ -1,41 +0,0 @@
|
||||
module tetris(
|
||||
input clk,
|
||||
input [2:0] parca,
|
||||
output reg [4:0] yukseklik,
|
||||
output [4:0] cevrim,
|
||||
output bitti_mi
|
||||
);
|
||||
|
||||
reg [4:0] cevrim_r = 0;
|
||||
reg [4:0] y_0 = 0;
|
||||
reg [4:0] y_1 = 0;
|
||||
reg [4:0] y_2 = 0;
|
||||
assign cevrim = cevrim_r;
|
||||
assign bitti_mi = cevrim_r == 5'b10000;
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (cevrim != 5'b10000) begin
|
||||
cevrim_r <= cevrim_r + 5'd1;
|
||||
y_0 <= y_0 + {4'b0000, parca[0]};
|
||||
y_1 <= y_1 + {4'b0000, parca[1]};
|
||||
y_2 <= y_2 + {4'b0000, parca[2]};
|
||||
end
|
||||
end
|
||||
|
||||
/* always @(posedge bitti_mi)
|
||||
yukseklik <= y_0 > y_1
|
||||
? y_0 > y_2 ? y_0 : y_2
|
||||
: y_1 > y_2 ? y_1 : y_2;
|
||||
*/
|
||||
|
||||
always @(posedge bitti_mi) begin
|
||||
if (y_0 > y_1) begin
|
||||
if (y_0 > y_2) yukseklik <= y_0;
|
||||
else yukseklik <= y_2;
|
||||
end else if (y_0 > y_1) begin
|
||||
if (y_1 > y_2) yukseklik <= y_1;
|
||||
else yukseklik <= y_2;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
@ -1,24 +0,0 @@
|
||||
GowinSynthesis start
|
||||
Running parser ...
|
||||
Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab2\src\BitM.v'
|
||||
Compiling module 'BitM'("C:\cygwin64\home\koray\verilog\lab2\src\BitM.v":1)
|
||||
NOTE (EX0101) : Current top module is "BitM"
|
||||
[5%] Running netlist conversion ...
|
||||
Running device independent optimization ...
|
||||
[10%] Optimizing Phase 0 completed
|
||||
[15%] Optimizing Phase 1 completed
|
||||
[25%] Optimizing Phase 2 completed
|
||||
Running inference ...
|
||||
[30%] Inferring Phase 0 completed
|
||||
[40%] Inferring Phase 1 completed
|
||||
[50%] Inferring Phase 2 completed
|
||||
[55%] Inferring Phase 3 completed
|
||||
Running technical mapping ...
|
||||
[60%] Tech-Mapping Phase 0 completed
|
||||
[65%] Tech-Mapping Phase 1 completed
|
||||
[75%] Tech-Mapping Phase 2 completed
|
||||
[80%] Tech-Mapping Phase 3 completed
|
||||
[90%] Tech-Mapping Phase 4 completed
|
||||
[95%] Generate netlist file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2.vg" completed
|
||||
[100%] Generate report file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2_syn.rpt.html" completed
|
||||
GowinSynthesis finish
|
||||
@ -1,19 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE gowin-synthesis-project>
|
||||
<Project>
|
||||
<Version>beta</Version>
|
||||
<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
|
||||
<FileList>
|
||||
<File path="C:\cygwin64\home\koray\verilog\lab2\src\BitM.v" type="verilog"/>
|
||||
</FileList>
|
||||
<OptionList>
|
||||
<Option type="disable_insert_pad" value="0"/>
|
||||
<Option type="global_freq" value="100.000"/>
|
||||
<Option type="looplimit" value="2000"/>
|
||||
<Option type="output_file" value="C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2.vg"/>
|
||||
<Option type="print_all_synthesis_warning" value="0"/>
|
||||
<Option type="ram_rw_check" value="0"/>
|
||||
<Option type="verilog_language" value="verilog-2001"/>
|
||||
<Option type="vhdl_language" value="vhdl-1993"/>
|
||||
</OptionList>
|
||||
</Project>
|
||||
@ -1,76 +0,0 @@
|
||||
//
|
||||
//Written by GowinSynthesis
|
||||
//Tool Version "V1.9.9.02"
|
||||
//Thu Apr 11 07:46:56 2024
|
||||
|
||||
//Source file index table:
|
||||
//file0 "\C:/cygwin64/home/koray/verilog/lab2/src/BitM.v"
|
||||
`timescale 100 ps/100 ps
|
||||
module BitM (
|
||||
A,
|
||||
B,
|
||||
AlB,
|
||||
AeB,
|
||||
AgB
|
||||
)
|
||||
;
|
||||
input A;
|
||||
input B;
|
||||
output AlB;
|
||||
output AeB;
|
||||
output AgB;
|
||||
wire A_d;
|
||||
wire B_d;
|
||||
wire AlB_d;
|
||||
wire AgB_d;
|
||||
wire AeB_d;
|
||||
wire VCC;
|
||||
wire GND;
|
||||
IBUF A_ibuf (
|
||||
.O(A_d),
|
||||
.I(A)
|
||||
);
|
||||
IBUF B_ibuf (
|
||||
.O(B_d),
|
||||
.I(B)
|
||||
);
|
||||
OBUF AlB_obuf (
|
||||
.O(AlB),
|
||||
.I(AlB_d)
|
||||
);
|
||||
OBUF AeB_obuf (
|
||||
.O(AeB),
|
||||
.I(AeB_d)
|
||||
);
|
||||
OBUF AgB_obuf (
|
||||
.O(AgB),
|
||||
.I(AgB_d)
|
||||
);
|
||||
LUT2 AlB_d_s (
|
||||
.F(AlB_d),
|
||||
.I0(A_d),
|
||||
.I1(B_d)
|
||||
);
|
||||
defparam AlB_d_s.INIT=4'h4;
|
||||
LUT2 AgB_d_s (
|
||||
.F(AgB_d),
|
||||
.I0(B_d),
|
||||
.I1(A_d)
|
||||
);
|
||||
defparam AgB_d_s.INIT=4'h4;
|
||||
LUT2 AeB_d_s (
|
||||
.F(AeB_d),
|
||||
.I0(A_d),
|
||||
.I1(B_d)
|
||||
);
|
||||
defparam AeB_d_s.INIT=4'h9;
|
||||
VCC VCC_cZ (
|
||||
.V(VCC)
|
||||
);
|
||||
GND GND_cZ (
|
||||
.G(GND)
|
||||
);
|
||||
GSR GSR (
|
||||
.GSRI(VCC)
|
||||
);
|
||||
endmodule /* BitM */
|
||||
@ -1,167 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>synthesis Report</title>
|
||||
<style type="text/css">
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
|
||||
div#main_wrapper{ width: 100%; }
|
||||
div#content { margin-left: 350px; margin-right: 30px; }
|
||||
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
|
||||
div#catalog ul { list-style-type: none; }
|
||||
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
|
||||
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
|
||||
div#catalog a:visited { color: #0084ff; }
|
||||
div#catalog a:hover { color: #fff; background: #0084ff; }
|
||||
hr { margin-top: 30px; margin-bottom: 30px; }
|
||||
h1, h3 { text-align: center; }
|
||||
h1 {margin-top: 50px; }
|
||||
table, th, td { border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { padding: 5px 5px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
|
||||
table.detail_table td.label { min-width: 100px; width: 8%;}
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="main_wrapper">
|
||||
<div id="catalog_wrapper">
|
||||
<div id="catalog">
|
||||
<ul>
|
||||
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
|
||||
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
|
||||
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
|
||||
<ul>
|
||||
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
|
||||
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
|
||||
</ul>
|
||||
</li>
|
||||
</ul>
|
||||
</div><!-- catalog -->
|
||||
</div><!-- catalog_wrapper -->
|
||||
<div id="content">
|
||||
<h1><a name="about">Synthesis Messages</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Report Title</td>
|
||||
<td>GowinSynthesis Report</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Design File</td>
|
||||
<td>C:\cygwin64\home\koray\verilog\lab2\src\BitM.v<br>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">GowinSynthesis Constraints File</td>
|
||||
<td>---</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Tool Version</td>
|
||||
<td>V1.9.9.02</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Part Number</td>
|
||||
<td>GW2A-LV18PG256C8/I7</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device</td>
|
||||
<td>GW2A-18</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device Version</td>
|
||||
<td>C</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Created Time</td>
|
||||
<td>Thu Apr 11 07:46:56 2024
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Legal Announcement</td>
|
||||
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="summary">Synthesis Details</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Top Level Module</td>
|
||||
<td>BitM</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Synthesis Process</td>
|
||||
<td>Running parser:<br/> CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.088s, Peak memory usage = 181.887MB<br/>Running netlist conversion:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/> Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/>Running inference:<br/> Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/>Running technical mapping:<br/> Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/> Tech-Mapping Phase 3: CPU time = 0h 0m 0.093s, Elapsed time = 0h 0m 0.132s, Peak memory usage = 181.887MB<br/> Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 181.887MB<br/>Generate output files:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.001s, Peak memory usage = 181.887MB<br/></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Total Time and Memory Usage</td>
|
||||
<td>CPU time = 0h 0m 0.108s, Elapsed time = 0h 0m 0.221s, Peak memory usage = 181.887MB</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="resource">Resource</a></h1>
|
||||
<h2><a name="usage">Resource Usage Summary</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label"><b>Resource</b></td>
|
||||
<td><b>Usage</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>I/O Port </b></td>
|
||||
<td>5</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>I/O Buf </b></td>
|
||||
<td>5</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    IBUF</td>
|
||||
<td>2</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    OBUF</td>
|
||||
<td>3</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>LUT </b></td>
|
||||
<td>3</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    LUT2</td>
|
||||
<td>3</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="utilization">Resource Utilization Summary</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label"><b>Resource</b></td>
|
||||
<td><b>Usage</b></td>
|
||||
<td><b>Utilization</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Logic</td>
|
||||
<td>3(3 LUT, 0 ALU) / 20736</td>
|
||||
<td><1%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Register</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">  --Register as Latch</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">  --Register as FF</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">BSRAM</td>
|
||||
<td>0 / 46</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
||||
@ -1,46 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>Hierarchy Module Resource</title>
|
||||
<style type="text/css">
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
|
||||
div#main_wrapper{ width: 100%; }
|
||||
h1 {text-align: center; }
|
||||
h1 {margin-top: 36px; }
|
||||
table, th, td { border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { align = "center"; padding: 5px 2px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="main_wrapper">
|
||||
<div id="content">
|
||||
<h1>Hierarchy Module Resource</h1>
|
||||
<table>
|
||||
<tr>
|
||||
<th class="label">MODULE NAME</th>
|
||||
<th class="label">REG NUMBER</th>
|
||||
<th class="label">ALU NUMBER</th>
|
||||
<th class="label">LUT NUMBER</th>
|
||||
<th class="label">DSP NUMBER</th>
|
||||
<th class="label">BSRAM NUMBER</th>
|
||||
<th class="label">SSRAM NUMBER</th>
|
||||
<th class="label">ROM16 NUMBER</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">BitM (C:/cygwin64/home/koray/verilog/lab2/src/BitM.v)</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">3</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
||||
@ -1,2 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Module name="BitM" Lut="3" T_Lut="3(3)"/>
|
||||
@ -1,88 +0,0 @@
|
||||
{
|
||||
"BACKGROUND_PROGRAMMING" : "off",
|
||||
"COMPRESS" : false,
|
||||
"CPU" : false,
|
||||
"CRC_CHECK" : true,
|
||||
"Clock_Route_Order" : 0,
|
||||
"Correct_Hold_Violation" : true,
|
||||
"DONE" : false,
|
||||
"DOWNLOAD_SPEED" : "default",
|
||||
"Disable_Insert_Pad" : false,
|
||||
"ENABLE_CTP" : false,
|
||||
"ENABLE_MERGE_MODE" : false,
|
||||
"ENCRYPTION_KEY" : false,
|
||||
"ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
|
||||
"ERROR_DECTION_AND_CORRECTION" : false,
|
||||
"ERROR_DECTION_ONLY" : false,
|
||||
"ERROR_INJECTION" : false,
|
||||
"EXTERNAL_MASTER_CONFIG_CLOCK" : false,
|
||||
"Enable_DSRM" : false,
|
||||
"FORMAT" : "binary",
|
||||
"FREQUENCY_DIVIDER" : "",
|
||||
"Generate_Constraint_File_of_Ports" : false,
|
||||
"Generate_IBIS_File" : false,
|
||||
"Generate_Plain_Text_Timing_Report" : false,
|
||||
"Generate_Post_PNR_Simulation_Model_File" : false,
|
||||
"Generate_Post_Place_File" : false,
|
||||
"Generate_SDF_File" : false,
|
||||
"Generate_VHDL_Post_PNR_Simulation_Model_File" : false,
|
||||
"Global_Freq" : "default",
|
||||
"GwSyn_Loop_Limit" : 2000,
|
||||
"HOTBOOT" : false,
|
||||
"I2C" : false,
|
||||
"I2C_SLAVE_ADDR" : "00",
|
||||
"IncludePath" : [
|
||||
|
||||
],
|
||||
"Incremental_Compile" : "",
|
||||
"Initialize_Primitives" : false,
|
||||
"JTAG" : false,
|
||||
"MODE_IO" : false,
|
||||
"MSPI" : false,
|
||||
"MSPI_JUMP" : false,
|
||||
"MULTIBOOT_ADDRESS_WIDTH" : "24",
|
||||
"MULTIBOOT_MODE" : "Normal",
|
||||
"MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000",
|
||||
"MULTIJUMP_ADDRESS_WIDTH" : "24",
|
||||
"MULTIJUMP_MODE" : "Normal",
|
||||
"MULTIJUMP_SPI_FLASH_ADDRESS" : "000000",
|
||||
"Multi_Boot" : true,
|
||||
"OUTPUT_BASE_NAME" : "lab2",
|
||||
"POWER_ON_RESET_MONITOR" : true,
|
||||
"PRINT_BSRAM_VALUE" : true,
|
||||
"PROGRAM_DONE_BYPASS" : false,
|
||||
"PlaceInRegToIob" : true,
|
||||
"PlaceIoRegToIob" : true,
|
||||
"PlaceOutRegToIob" : true,
|
||||
"Place_Option" : "0",
|
||||
"Process_Configuration_Verion" : "1.0",
|
||||
"Promote_Physical_Constraint_Warning_to_Error" : true,
|
||||
"READY" : false,
|
||||
"RECONFIG_N" : false,
|
||||
"Ram_RW_Check" : false,
|
||||
"Replicate_Resources" : false,
|
||||
"Report_Auto-Placed_Io_Information" : false,
|
||||
"Route_Maxfan" : 23,
|
||||
"Route_Option" : "0",
|
||||
"Run_Timing_Driven" : true,
|
||||
"SECURE_MODE" : false,
|
||||
"SECURITY_BIT" : true,
|
||||
"SEU_HANDLER" : false,
|
||||
"SEU_HANDLER_CHECKSUM" : false,
|
||||
"SEU_HANDLER_MODE" : "auto",
|
||||
"SSPI" : false,
|
||||
"STOP_SEU_HANDLER" : false,
|
||||
"Show_All_Warnings" : false,
|
||||
"Synthesize_tool" : "GowinSyn",
|
||||
"TclPre" : "",
|
||||
"TopModule" : "",
|
||||
"USERCODE" : "default",
|
||||
"Unused_Pin" : "As_input_tri_stated_with_pull_up",
|
||||
"VCCAUX" : 3.3,
|
||||
"VCCX" : "3.3",
|
||||
"VHDL_Standard" : "VHDL_Std_1993",
|
||||
"Verilog_Standard" : "Vlg_Std_2001",
|
||||
"WAKE_UP" : "0",
|
||||
"show_all_warnings" : false,
|
||||
"turn_off_bg" : false
|
||||
}
|
||||
@ -1,36 +0,0 @@
|
||||
[
|
||||
{
|
||||
"InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/BitM.v",
|
||||
"InstLine" : 1,
|
||||
"InstName" : "BitM",
|
||||
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/BitM.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "BitM"
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/fullAdder.v",
|
||||
"InstLine" : 1,
|
||||
"InstName" : "fullAdder",
|
||||
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/fullAdder.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "fullAdder"
|
||||
},
|
||||
{
|
||||
"InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
|
||||
"InstLine" : 1,
|
||||
"InstName" : "tb",
|
||||
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "tb",
|
||||
"SubInsts" : [
|
||||
{
|
||||
"InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
|
||||
"InstLine" : 6,
|
||||
"InstName" : "uut",
|
||||
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/halfAdder.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "halfAdder"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
@ -1,29 +0,0 @@
|
||||
{
|
||||
"Device" : "GW2A-18C",
|
||||
"Files" : [
|
||||
{
|
||||
"Path" : "C:/cygwin64/home/koray/verilog/lab2/src/BitM.v",
|
||||
"Type" : "verilog"
|
||||
},
|
||||
{
|
||||
"Path" : "C:/cygwin64/home/koray/verilog/lab2/src/fullAdder.v",
|
||||
"Type" : "verilog"
|
||||
},
|
||||
{
|
||||
"Path" : "C:/cygwin64/home/koray/verilog/lab2/src/halfAdder.v",
|
||||
"Type" : "verilog"
|
||||
},
|
||||
{
|
||||
"Path" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
|
||||
"Type" : "verilog"
|
||||
}
|
||||
],
|
||||
"IncludePath" : [
|
||||
|
||||
],
|
||||
"LoopLimit" : 2000,
|
||||
"ResultFile" : "C:/cygwin64/home/koray/verilog/lab2/impl/temp/rtl_parser.result",
|
||||
"Top" : "",
|
||||
"VerilogStd" : "verilog_2001",
|
||||
"VhdlStd" : "vhdl_93"
|
||||
}
|
||||
@ -1,13 +0,0 @@
|
||||
<?xml version="1" encoding="UTF-8"?>
|
||||
<!DOCTYPE gowin-fpga-project>
|
||||
<Project>
|
||||
<Template>FPGA</Template>
|
||||
<Version>5</Version>
|
||||
<Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device>
|
||||
<FileList>
|
||||
<File path="src/BitM.v" type="file.verilog" enable="1"/>
|
||||
<File path="src/fullAdder.v" type="file.verilog" enable="1"/>
|
||||
<File path="src/halfAdder.v" type="file.verilog" enable="1"/>
|
||||
<File path="src/tb.v" type="file.verilog" enable="1"/>
|
||||
</FileList>
|
||||
</Project>
|
||||
@ -1,17 +0,0 @@
|
||||
<?xml version="1" encoding="UTF-8"?>
|
||||
<!DOCTYPE ProjectUserData>
|
||||
<UserConfig>
|
||||
<Version>1.0</Version>
|
||||
<FlowState>
|
||||
<Process ID="Synthesis" State="4"/>
|
||||
<Process ID="Pnr" State="0"/>
|
||||
<Process ID="Gao" State="0"/>
|
||||
<Process ID="Rtl_Gao" State="2"/>
|
||||
</FlowState>
|
||||
<ResultFileList>
|
||||
<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/lab2.vg"/>
|
||||
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/lab2_syn.rpt.html"/>
|
||||
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/lab2_syn_rsc.xml"/>
|
||||
</ResultFileList>
|
||||
<Ui>000000ff00000001fd00000002000000000000010000000130fc0200000001fc00000063000001300000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000000000030000050000000121fc0100000001fc00000000000005000000009b00fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000005100fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff0000009b00ffffff000003f80000013000000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e0045006400690074010000009bffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000157ffffffff0000000000000000</Ui>
|
||||
</UserConfig>
|
||||
@ -1,19 +0,0 @@
|
||||
module BitM(
|
||||
input A,
|
||||
input B,
|
||||
output AlB,
|
||||
output AeB,
|
||||
output AgB
|
||||
);
|
||||
|
||||
wire An, Bn;
|
||||
|
||||
not n1 (An, A);
|
||||
not n2 (Bn, B);
|
||||
|
||||
and a1 (AlB, An, B);
|
||||
and a2 (AgB, Bn, A);
|
||||
|
||||
nor nor1 (AeB, AlB, AgB);
|
||||
|
||||
endmodule
|
||||
@ -1,26 +0,0 @@
|
||||
module BitM_tb();
|
||||
|
||||
reg r1, r2;
|
||||
wire w1, w2, w3;
|
||||
|
||||
BitM uut(
|
||||
.A(r1),
|
||||
.B(r2),
|
||||
.AlB(w1),
|
||||
.AeB(w2),
|
||||
.AgB(w3)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("bdmp.vcd");
|
||||
$dumpvars;
|
||||
r1 = 0; r2 = 0; #10
|
||||
r1 = 0; r2 = 1; #10
|
||||
r1 = 1; r2 = 0; #10
|
||||
r1 = 1; r2 = 1; #10
|
||||
$display(w1);
|
||||
$display(w2);
|
||||
$display(w3);
|
||||
end
|
||||
|
||||
endmodule
|
||||
@ -1,58 +0,0 @@
|
||||
$date
|
||||
Thu Apr 11 07:50:26 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module BitM_tb $end
|
||||
$var wire 1 ! w3 $end
|
||||
$var wire 1 " w2 $end
|
||||
$var wire 1 # w1 $end
|
||||
$var reg 1 $ r1 $end
|
||||
$var reg 1 % r2 $end
|
||||
$scope module uut $end
|
||||
$var wire 1 $ A $end
|
||||
$var wire 1 " AeB $end
|
||||
$var wire 1 ! AgB $end
|
||||
$var wire 1 # AlB $end
|
||||
$var wire 1 & An $end
|
||||
$var wire 1 % B $end
|
||||
$var wire 1 ' Bn $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$comment Show the parameter values. $end
|
||||
$dumpall
|
||||
$end
|
||||
#0
|
||||
$dumpvars
|
||||
1'
|
||||
1&
|
||||
0%
|
||||
0$
|
||||
0#
|
||||
1"
|
||||
0!
|
||||
$end
|
||||
#10
|
||||
0"
|
||||
0'
|
||||
1#
|
||||
1%
|
||||
#20
|
||||
1!
|
||||
0"
|
||||
1'
|
||||
0#
|
||||
0&
|
||||
0%
|
||||
1$
|
||||
#30
|
||||
1"
|
||||
0!
|
||||
0'
|
||||
1%
|
||||
#40
|
||||
@ -1,70 +0,0 @@
|
||||
#! /c/Source/iverilog-install/bin/vvp
|
||||
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
|
||||
S_000002114102cad0 .scope module, "BitM_tb" "BitM_tb" 2 1;
|
||||
.timescale 0 0;
|
||||
v0000021140f146e0_0 .var "r1", 0 0;
|
||||
v0000021140f14780_0 .var "r2", 0 0;
|
||||
v0000021140f14820_0 .net "w1", 0 0, L_0000021140ee32f0; 1 drivers
|
||||
v0000021140f148c0_0 .net "w2", 0 0, L_0000021140f14f60; 1 drivers
|
||||
v0000021140f14960_0 .net "w3", 0 0, L_0000021140f14de0; 1 drivers
|
||||
S_000002114102cc60 .scope module, "uut" "BitM" 2 6, 3 1 0, S_000002114102cad0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "AlB";
|
||||
.port_info 3 /OUTPUT 1 "AeB";
|
||||
.port_info 4 /OUTPUT 1 "AgB";
|
||||
L_000002114102af60 .functor NOT 1, v0000021140f146e0_0, C4<0>, C4<0>, C4<0>;
|
||||
L_0000021140ee3190 .functor NOT 1, v0000021140f14780_0, C4<0>, C4<0>, C4<0>;
|
||||
L_0000021140ee32f0 .functor AND 1, L_000002114102af60, v0000021140f14780_0, C4<1>, C4<1>;
|
||||
L_0000021140f14de0 .functor AND 1, L_0000021140ee3190, v0000021140f146e0_0, C4<1>, C4<1>;
|
||||
L_0000021140f14f60 .functor NOR 1, L_0000021140ee32f0, L_0000021140f14de0, C4<0>, C4<0>;
|
||||
v0000021141028fc0_0 .net "A", 0 0, v0000021140f146e0_0; 1 drivers
|
||||
v0000021140ee2ee0_0 .net "AeB", 0 0, L_0000021140f14f60; alias, 1 drivers
|
||||
v000002114102aec0_0 .net "AgB", 0 0, L_0000021140f14de0; alias, 1 drivers
|
||||
v000002114102cdf0_0 .net "AlB", 0 0, L_0000021140ee32f0; alias, 1 drivers
|
||||
v000002114102ce90_0 .net "An", 0 0, L_000002114102af60; 1 drivers
|
||||
v0000021140f145a0_0 .net "B", 0 0, v0000021140f14780_0; 1 drivers
|
||||
v0000021140f14640_0 .net "Bn", 0 0, L_0000021140ee3190; 1 drivers
|
||||
.scope S_000002114102cad0;
|
||||
T_0 ;
|
||||
%vpi_call 2 15 "$dumpfile", "bdmp.vcd" {0 0 0};
|
||||
%vpi_call 2 16 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0000021140f146e0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0000021140f14780_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0000021140f146e0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0000021140f14780_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0000021140f146e0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0000021140f14780_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0000021140f146e0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0000021140f14780_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%vpi_call 2 21 "$display", v0000021140f14820_0 {0 0 0};
|
||||
%vpi_call 2 22 "$display", v0000021140f148c0_0 {0 0 0};
|
||||
%vpi_call 2 23 "$display", v0000021140f14960_0 {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"BitM_tb.v";
|
||||
"BitM.v";
|
||||
@ -1,43 +0,0 @@
|
||||
$date
|
||||
Thu Apr 11 06:36:34 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module tb $end
|
||||
$var wire 1 ! w2 $end
|
||||
$var wire 1 " w1 $end
|
||||
$var reg 1 # r1 $end
|
||||
$var reg 1 $ r2 $end
|
||||
$scope module uut $end
|
||||
$var wire 1 # A $end
|
||||
$var wire 1 $ B $end
|
||||
$var wire 1 ! C $end
|
||||
$var wire 1 " S $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$comment Show the parameter values. $end
|
||||
$dumpall
|
||||
$end
|
||||
#0
|
||||
$dumpvars
|
||||
0$
|
||||
0#
|
||||
0"
|
||||
0!
|
||||
$end
|
||||
#20
|
||||
1"
|
||||
1#
|
||||
#40
|
||||
1$
|
||||
0#
|
||||
#60
|
||||
0"
|
||||
1!
|
||||
1#
|
||||
#80
|
||||
@ -1,75 +0,0 @@
|
||||
$date
|
||||
Thu Apr 11 07:39:27 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module ftb $end
|
||||
$var wire 1 ! w2 $end
|
||||
$var wire 1 " w1 $end
|
||||
$var reg 1 # r1 $end
|
||||
$var reg 1 $ r2 $end
|
||||
$var reg 1 % r3 $end
|
||||
$scope module uut $end
|
||||
$var wire 1 # A $end
|
||||
$var wire 1 & AB $end
|
||||
$var wire 1 ' ABCin $end
|
||||
$var wire 1 ( AaB $end
|
||||
$var wire 1 $ B $end
|
||||
$var wire 1 % Cin $end
|
||||
$var wire 1 ! Cout $end
|
||||
$var wire 1 " S $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$comment Show the parameter values. $end
|
||||
$dumpall
|
||||
$end
|
||||
#0
|
||||
$dumpvars
|
||||
0(
|
||||
0'
|
||||
0&
|
||||
0%
|
||||
0$
|
||||
0#
|
||||
0"
|
||||
0!
|
||||
$end
|
||||
#10
|
||||
1"
|
||||
1%
|
||||
#20
|
||||
1&
|
||||
0%
|
||||
1$
|
||||
#30
|
||||
1!
|
||||
0"
|
||||
1'
|
||||
1%
|
||||
#40
|
||||
0!
|
||||
1"
|
||||
0'
|
||||
0%
|
||||
0$
|
||||
1#
|
||||
#50
|
||||
1!
|
||||
0"
|
||||
1'
|
||||
1%
|
||||
#60
|
||||
0'
|
||||
0&
|
||||
1(
|
||||
0%
|
||||
1$
|
||||
#70
|
||||
1"
|
||||
1%
|
||||
#80
|
||||
@ -1,106 +0,0 @@
|
||||
#! /c/Source/iverilog-install/bin/vvp
|
||||
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
|
||||
S_000001da0354ad70 .scope module, "ftb" "ftb" 2 1;
|
||||
.timescale 0 0;
|
||||
v000001da035dc840_0 .var "r1", 0 0;
|
||||
v000001da035dc8e0_0 .var "r2", 0 0;
|
||||
v000001da035dc980_0 .var "r3", 0 0;
|
||||
v000001da035dca20_0 .net "w1", 0 0, L_000001da03594080; 1 drivers
|
||||
v000001da035935f0_0 .net "w2", 0 0, L_000001da03594470; 1 drivers
|
||||
S_000001da0354e9e0 .scope module, "uut" "fullAdder" 2 6, 3 1 0, S_000001da0354ad70;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "Cin";
|
||||
.port_info 3 /OUTPUT 1 "S";
|
||||
.port_info 4 /OUTPUT 1 "Cout";
|
||||
L_000001da03594010 .functor XOR 1, v000001da035dc840_0, v000001da035dc8e0_0, C4<0>, C4<0>;
|
||||
L_000001da03594080 .functor XOR 1, L_000001da03594010, v000001da035dc980_0, C4<0>, C4<0>;
|
||||
L_000001da03593e50 .functor AND 1, L_000001da03594010, v000001da035dc980_0, C4<1>, C4<1>;
|
||||
L_000001da035940f0 .functor AND 1, v000001da035dc840_0, v000001da035dc8e0_0, C4<1>, C4<1>;
|
||||
L_000001da03594470 .functor OR 1, L_000001da03593e50, L_000001da035940f0, C4<0>, C4<0>;
|
||||
v000001da03563310_0 .net "A", 0 0, v000001da035dc840_0; 1 drivers
|
||||
v000001da03562ee0_0 .net "AB", 0 0, L_000001da03594010; 1 drivers
|
||||
v000001da0354af00_0 .net "ABCin", 0 0, L_000001da03593e50; 1 drivers
|
||||
v000001da03549850_0 .net "AaB", 0 0, L_000001da035940f0; 1 drivers
|
||||
v000001da0354eb70_0 .net "B", 0 0, v000001da035dc8e0_0; 1 drivers
|
||||
v000001da0354ec10_0 .net "Cin", 0 0, v000001da035dc980_0; 1 drivers
|
||||
v000001da0354ecb0_0 .net "Cout", 0 0, L_000001da03594470; alias, 1 drivers
|
||||
v000001da0354ed50_0 .net "S", 0 0, L_000001da03594080; alias, 1 drivers
|
||||
.scope S_000001da0354ad70;
|
||||
T_0 ;
|
||||
%vpi_call 2 15 "$dumpfile", "fdmp.vcd" {0 0 0};
|
||||
%vpi_call 2 16 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc840_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc8e0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc980_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc840_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc8e0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc980_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc840_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc8e0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc980_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc840_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc8e0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc980_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc840_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc8e0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc980_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc840_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc8e0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc980_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc840_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc8e0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001da035dc980_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc840_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc8e0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001da035dc980_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%vpi_call 2 25 "$display", v000001da035dca20_0 {0 0 0};
|
||||
%vpi_call 2 26 "$display", v000001da035935f0_0 {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"ftb.v";
|
||||
"fullAdder.v";
|
||||
@ -1,29 +0,0 @@
|
||||
module ftb ();
|
||||
|
||||
reg r1, r2, r3;
|
||||
wire w1, w2;
|
||||
|
||||
fullAdder uut(
|
||||
.A(r1),
|
||||
.B(r2),
|
||||
.Cin(r3),
|
||||
.S(w1),
|
||||
.Cout(w2)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("fdmp.vcd");
|
||||
$dumpvars;
|
||||
r1 = 0; r2 = 0; r3 = 0; #10
|
||||
r1 = 0; r2 = 0; r3 = 1; #10
|
||||
r1 = 0; r2 = 1; r3 = 0; #10
|
||||
r1 = 0; r2 = 1; r3 = 1; #10
|
||||
r1 = 1; r2 = 0; r3 = 0; #10
|
||||
r1 = 1; r2 = 0; r3 = 1; #10
|
||||
r1 = 1; r2 = 1; r3 = 0; #10
|
||||
r1 = 1; r2 = 1; r3 = 1; #10
|
||||
$display(w1);
|
||||
$display(w2);
|
||||
end
|
||||
|
||||
endmodule
|
||||
@ -1,20 +0,0 @@
|
||||
module fullAdder(
|
||||
input A,
|
||||
input B,
|
||||
input Cin,
|
||||
output S,
|
||||
output Cout
|
||||
);
|
||||
|
||||
wire AB;
|
||||
wire ABCin, AaB;
|
||||
|
||||
xor (AB, A, B);
|
||||
xor (S, AB, Cin);
|
||||
|
||||
and (ABCin, AB, Cin);
|
||||
and (AaB, A, B);
|
||||
|
||||
or (Cout, ABCin, AaB);
|
||||
|
||||
endmodule
|
||||
@ -1,11 +0,0 @@
|
||||
module halfAdder(
|
||||
input A,
|
||||
input B,
|
||||
output S,
|
||||
output C
|
||||
);
|
||||
|
||||
xor (S, A, B);
|
||||
and (C, A, B);
|
||||
|
||||
endmodule
|
||||
@ -1,61 +0,0 @@
|
||||
#! /c/Source/iverilog-install/bin/vvp
|
||||
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
|
||||
S_000001b4458eec80 .scope module, "tb" "tb" 2 1;
|
||||
.timescale 0 0;
|
||||
v000001b4458ec1d0_0 .var "r1", 0 0;
|
||||
v000001b4458ec270_0 .var "r2", 0 0;
|
||||
v000001b4458ec310_0 .net "w1", 0 0, L_000001b445783190; 1 drivers
|
||||
v000001b4458ec3b0_0 .net "w2", 0 0, L_000001b4457832f0; 1 drivers
|
||||
S_000001b4458eee10 .scope module, "uut" "halfAdder" 2 6, 3 1 0, S_000001b4458eec80;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "S";
|
||||
.port_info 3 /OUTPUT 1 "C";
|
||||
L_000001b445783190 .functor XOR 1, v000001b4458ec1d0_0, v000001b4458ec270_0, C4<0>, C4<0>;
|
||||
L_000001b4457832f0 .functor AND 1, v000001b4458ec1d0_0, v000001b4458ec270_0, C4<1>, C4<1>;
|
||||
v000001b4458ebff0_0 .net "A", 0 0, v000001b4458ec1d0_0; 1 drivers
|
||||
v000001b445782ee0_0 .net "B", 0 0, v000001b4458ec270_0; 1 drivers
|
||||
v000001b4458ec090_0 .net "C", 0 0, L_000001b4457832f0; alias, 1 drivers
|
||||
v000001b4458ec130_0 .net "S", 0 0, L_000001b445783190; alias, 1 drivers
|
||||
.scope S_000001b4458eec80;
|
||||
T_0 ;
|
||||
%vpi_call 2 14 "$dumpfile", "dmp.vcd" {0 0 0};
|
||||
%vpi_call 2 15 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001b4458ec1d0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001b4458ec270_0, 0, 1;
|
||||
%delay 20, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001b4458ec1d0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001b4458ec270_0, 0, 1;
|
||||
%delay 20, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001b4458ec1d0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001b4458ec270_0, 0, 1;
|
||||
%delay 20, 0;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001b4458ec1d0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001b4458ec270_0, 0, 1;
|
||||
%delay 20, 0;
|
||||
%vpi_call 2 20 "$display", v000001b4458ec310_0 {0 0 0};
|
||||
%vpi_call 2 21 "$display", v000001b4458ec3b0_0 {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"tb.v";
|
||||
"halfAdder.v";
|
||||
@ -1,24 +0,0 @@
|
||||
module tb();
|
||||
|
||||
reg r1, r2;
|
||||
wire w1, w2;
|
||||
|
||||
halfAdder uut(
|
||||
.A(r1),
|
||||
.B(r2),
|
||||
.S(w1),
|
||||
.C(w2)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("dmp.vcd");
|
||||
$dumpvars;
|
||||
r1 = 0; r2 = 0; #20
|
||||
r1 = 1; r2 = 0; #20
|
||||
r1 = 0; r2 = 1; #20
|
||||
r1 = 1; r2 = 1; #20
|
||||
$display(w1);
|
||||
$display(w2);
|
||||
end
|
||||
|
||||
endmodule
|
||||
@ -1,40 +0,0 @@
|
||||
GowinSynthesis start
|
||||
Running parser ...
|
||||
Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab2\src\lab2.v'
|
||||
Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab2\src\tb.v'
|
||||
Compiling module 'tb'("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":1)
|
||||
WARN (EX3858) : System task 'dumpfile' is ignored for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":17)
|
||||
WARN (EX3858) : System task 'dumpvars' is ignored for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":18)
|
||||
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":19)
|
||||
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":20)
|
||||
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":21)
|
||||
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":22)
|
||||
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":23)
|
||||
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":24)
|
||||
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":25)
|
||||
WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":26)
|
||||
WARN (EX3858) : System task 'display' is ignored for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":27)
|
||||
WARN (EX3780) : Using initial value of 'r1' since it is never assigned("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":28)
|
||||
Compiling module 'lab2'("C:\cygwin64\home\koray\verilog\lab2\src\lab2.v":1)
|
||||
NOTE (EX0101) : Current top module is "tb"
|
||||
WARN (EX0203) : Top module "tb" has no ports("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":1)
|
||||
[5%] Running netlist conversion ...
|
||||
Running device independent optimization ...
|
||||
[10%] Optimizing Phase 0 completed
|
||||
[15%] Optimizing Phase 1 completed
|
||||
[25%] Optimizing Phase 2 completed
|
||||
Running inference ...
|
||||
[30%] Inferring Phase 0 completed
|
||||
[40%] Inferring Phase 1 completed
|
||||
[50%] Inferring Phase 2 completed
|
||||
[55%] Inferring Phase 3 completed
|
||||
Running technical mapping ...
|
||||
[60%] Tech-Mapping Phase 0 completed
|
||||
[65%] Tech-Mapping Phase 1 completed
|
||||
[75%] Tech-Mapping Phase 2 completed
|
||||
[80%] Tech-Mapping Phase 3 completed
|
||||
[90%] Tech-Mapping Phase 4 completed
|
||||
WARN (NL0002) : The module "lab2" instantiated to "uut" is swept in optimizing("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":12)
|
||||
[95%] Generate netlist file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2.vg" completed
|
||||
[100%] Generate report file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2_syn.rpt.html" completed
|
||||
GowinSynthesis finish
|
||||
@ -1,20 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE gowin-synthesis-project>
|
||||
<Project>
|
||||
<Version>beta</Version>
|
||||
<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
|
||||
<FileList>
|
||||
<File path="C:\cygwin64\home\koray\verilog\lab2\src\lab2.v" type="verilog"/>
|
||||
<File path="C:\cygwin64\home\koray\verilog\lab2\src\tb.v" type="verilog"/>
|
||||
</FileList>
|
||||
<OptionList>
|
||||
<Option type="disable_insert_pad" value="0"/>
|
||||
<Option type="global_freq" value="100.000"/>
|
||||
<Option type="looplimit" value="2000"/>
|
||||
<Option type="output_file" value="C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2.vg"/>
|
||||
<Option type="print_all_synthesis_warning" value="0"/>
|
||||
<Option type="ram_rw_check" value="0"/>
|
||||
<Option type="verilog_language" value="verilog-2001"/>
|
||||
<Option type="vhdl_language" value="vhdl-1993"/>
|
||||
</OptionList>
|
||||
</Project>
|
||||
@ -1,25 +0,0 @@
|
||||
//
|
||||
//Written by GowinSynthesis
|
||||
//Tool Version "V1.9.9.02"
|
||||
//Thu Apr 11 06:15:18 2024
|
||||
|
||||
//Source file index table:
|
||||
//file0 "\C:/cygwin64/home/koray/verilog/lab2/src/lab2.v"
|
||||
//file1 "\C:/cygwin64/home/koray/verilog/lab2/src/tb.v"
|
||||
`timescale 100 ps/100 ps
|
||||
module tb (
|
||||
|
||||
)
|
||||
;
|
||||
wire VCC;
|
||||
wire GND;
|
||||
VCC VCC_cZ (
|
||||
.V(VCC)
|
||||
);
|
||||
GND GND_cZ (
|
||||
.G(GND)
|
||||
);
|
||||
GSR GSR (
|
||||
.GSRI(VCC)
|
||||
);
|
||||
endmodule /* tb */
|
||||
@ -1,144 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>synthesis Report</title>
|
||||
<style type="text/css">
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
|
||||
div#main_wrapper{ width: 100%; }
|
||||
div#content { margin-left: 350px; margin-right: 30px; }
|
||||
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
|
||||
div#catalog ul { list-style-type: none; }
|
||||
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
|
||||
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
|
||||
div#catalog a:visited { color: #0084ff; }
|
||||
div#catalog a:hover { color: #fff; background: #0084ff; }
|
||||
hr { margin-top: 30px; margin-bottom: 30px; }
|
||||
h1, h3 { text-align: center; }
|
||||
h1 {margin-top: 50px; }
|
||||
table, th, td { border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { padding: 5px 5px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
|
||||
table.detail_table td.label { min-width: 100px; width: 8%;}
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="main_wrapper">
|
||||
<div id="catalog_wrapper">
|
||||
<div id="catalog">
|
||||
<ul>
|
||||
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
|
||||
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
|
||||
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
|
||||
<ul>
|
||||
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
|
||||
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
|
||||
</ul>
|
||||
</li>
|
||||
</ul>
|
||||
</div><!-- catalog -->
|
||||
</div><!-- catalog_wrapper -->
|
||||
<div id="content">
|
||||
<h1><a name="about">Synthesis Messages</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Report Title</td>
|
||||
<td>GowinSynthesis Report</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Design File</td>
|
||||
<td>C:\cygwin64\home\koray\verilog\lab2\src\lab2.v<br>
|
||||
C:\cygwin64\home\koray\verilog\lab2\src\tb.v<br>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">GowinSynthesis Constraints File</td>
|
||||
<td>---</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Tool Version</td>
|
||||
<td>V1.9.9.02</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Part Number</td>
|
||||
<td>GW2A-LV18PG256C8/I7</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device</td>
|
||||
<td>GW2A-18</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device Version</td>
|
||||
<td>C</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Created Time</td>
|
||||
<td>Thu Apr 11 06:15:18 2024
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Legal Announcement</td>
|
||||
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="summary">Synthesis Details</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Top Level Module</td>
|
||||
<td>tb</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Synthesis Process</td>
|
||||
<td>Running parser:<br/> CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.148s, Peak memory usage = 184.680MB<br/>Running netlist conversion:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/> Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>Running inference:<br/> Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>Running technical mapping:<br/> Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Tech-Mapping Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 184.680MB<br/> Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>Generate output files:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 184.680MB<br/></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Total Time and Memory Usage</td>
|
||||
<td>CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.208s, Peak memory usage = 184.680MB</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="resource">Resource</a></h1>
|
||||
<h2><a name="usage">Resource Usage Summary</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label"><b>Resource</b></td>
|
||||
<td><b>Usage</b></td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="utilization">Resource Utilization Summary</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label"><b>Resource</b></td>
|
||||
<td><b>Usage</b></td>
|
||||
<td><b>Utilization</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Logic</td>
|
||||
<td>0(0 LUT, 0 ALU) / 20736</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Register</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">  --Register as Latch</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">  --Register as FF</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">BSRAM</td>
|
||||
<td>0 / 46</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
||||
@ -1,46 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>Hierarchy Module Resource</title>
|
||||
<style type="text/css">
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
|
||||
div#main_wrapper{ width: 100%; }
|
||||
h1 {text-align: center; }
|
||||
h1 {margin-top: 36px; }
|
||||
table, th, td { border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { align = "center"; padding: 5px 2px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="main_wrapper">
|
||||
<div id="content">
|
||||
<h1>Hierarchy Module Resource</h1>
|
||||
<table>
|
||||
<tr>
|
||||
<th class="label">MODULE NAME</th>
|
||||
<th class="label">REG NUMBER</th>
|
||||
<th class="label">ALU NUMBER</th>
|
||||
<th class="label">LUT NUMBER</th>
|
||||
<th class="label">DSP NUMBER</th>
|
||||
<th class="label">BSRAM NUMBER</th>
|
||||
<th class="label">SSRAM NUMBER</th>
|
||||
<th class="label">ROM16 NUMBER</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">tb (C:/cygwin64/home/koray/verilog/lab2/src/tb.v)</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
||||
@ -1,2 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Module name="tb"/>
|
||||
@ -1,88 +0,0 @@
|
||||
{
|
||||
"BACKGROUND_PROGRAMMING" : "off",
|
||||
"COMPRESS" : false,
|
||||
"CPU" : false,
|
||||
"CRC_CHECK" : true,
|
||||
"Clock_Route_Order" : 0,
|
||||
"Correct_Hold_Violation" : true,
|
||||
"DONE" : false,
|
||||
"DOWNLOAD_SPEED" : "default",
|
||||
"Disable_Insert_Pad" : false,
|
||||
"ENABLE_CTP" : false,
|
||||
"ENABLE_MERGE_MODE" : false,
|
||||
"ENCRYPTION_KEY" : false,
|
||||
"ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
|
||||
"ERROR_DECTION_AND_CORRECTION" : false,
|
||||
"ERROR_DECTION_ONLY" : false,
|
||||
"ERROR_INJECTION" : false,
|
||||
"EXTERNAL_MASTER_CONFIG_CLOCK" : false,
|
||||
"Enable_DSRM" : false,
|
||||
"FORMAT" : "binary",
|
||||
"FREQUENCY_DIVIDER" : "",
|
||||
"Generate_Constraint_File_of_Ports" : false,
|
||||
"Generate_IBIS_File" : false,
|
||||
"Generate_Plain_Text_Timing_Report" : false,
|
||||
"Generate_Post_PNR_Simulation_Model_File" : false,
|
||||
"Generate_Post_Place_File" : false,
|
||||
"Generate_SDF_File" : false,
|
||||
"Generate_VHDL_Post_PNR_Simulation_Model_File" : false,
|
||||
"Global_Freq" : "default",
|
||||
"GwSyn_Loop_Limit" : 2000,
|
||||
"HOTBOOT" : false,
|
||||
"I2C" : false,
|
||||
"I2C_SLAVE_ADDR" : "00",
|
||||
"IncludePath" : [
|
||||
|
||||
],
|
||||
"Incremental_Compile" : "",
|
||||
"Initialize_Primitives" : false,
|
||||
"JTAG" : false,
|
||||
"MODE_IO" : false,
|
||||
"MSPI" : false,
|
||||
"MSPI_JUMP" : false,
|
||||
"MULTIBOOT_ADDRESS_WIDTH" : "24",
|
||||
"MULTIBOOT_MODE" : "Normal",
|
||||
"MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000",
|
||||
"MULTIJUMP_ADDRESS_WIDTH" : "24",
|
||||
"MULTIJUMP_MODE" : "Normal",
|
||||
"MULTIJUMP_SPI_FLASH_ADDRESS" : "000000",
|
||||
"Multi_Boot" : true,
|
||||
"OUTPUT_BASE_NAME" : "lab2",
|
||||
"POWER_ON_RESET_MONITOR" : true,
|
||||
"PRINT_BSRAM_VALUE" : true,
|
||||
"PROGRAM_DONE_BYPASS" : false,
|
||||
"PlaceInRegToIob" : true,
|
||||
"PlaceIoRegToIob" : true,
|
||||
"PlaceOutRegToIob" : true,
|
||||
"Place_Option" : "0",
|
||||
"Process_Configuration_Verion" : "1.0",
|
||||
"Promote_Physical_Constraint_Warning_to_Error" : true,
|
||||
"READY" : false,
|
||||
"RECONFIG_N" : false,
|
||||
"Ram_RW_Check" : false,
|
||||
"Replicate_Resources" : false,
|
||||
"Report_Auto-Placed_Io_Information" : false,
|
||||
"Route_Maxfan" : 23,
|
||||
"Route_Option" : "0",
|
||||
"Run_Timing_Driven" : true,
|
||||
"SECURE_MODE" : false,
|
||||
"SECURITY_BIT" : true,
|
||||
"SEU_HANDLER" : false,
|
||||
"SEU_HANDLER_CHECKSUM" : false,
|
||||
"SEU_HANDLER_MODE" : "auto",
|
||||
"SSPI" : false,
|
||||
"STOP_SEU_HANDLER" : false,
|
||||
"Show_All_Warnings" : false,
|
||||
"Synthesize_tool" : "GowinSyn",
|
||||
"TclPre" : "",
|
||||
"TopModule" : "",
|
||||
"USERCODE" : "default",
|
||||
"Unused_Pin" : "As_input_tri_stated_with_pull_up",
|
||||
"VCCAUX" : 3.3,
|
||||
"VCCX" : "3.3",
|
||||
"VHDL_Standard" : "VHDL_Std_1993",
|
||||
"Verilog_Standard" : "Vlg_Std_2001",
|
||||
"WAKE_UP" : "0",
|
||||
"show_all_warnings" : false,
|
||||
"turn_off_bg" : false
|
||||
}
|
||||
@ -1,20 +0,0 @@
|
||||
[
|
||||
{
|
||||
"InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
|
||||
"InstLine" : 1,
|
||||
"InstName" : "tb",
|
||||
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "tb",
|
||||
"SubInsts" : [
|
||||
{
|
||||
"InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
|
||||
"InstLine" : 6,
|
||||
"InstName" : "uut",
|
||||
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/lab2.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "lab2"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
@ -1,21 +0,0 @@
|
||||
{
|
||||
"Device" : "GW2A-18C",
|
||||
"Files" : [
|
||||
{
|
||||
"Path" : "C:/cygwin64/home/koray/verilog/lab2/src/lab2.v",
|
||||
"Type" : "verilog"
|
||||
},
|
||||
{
|
||||
"Path" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
|
||||
"Type" : "verilog"
|
||||
}
|
||||
],
|
||||
"IncludePath" : [
|
||||
|
||||
],
|
||||
"LoopLimit" : 2000,
|
||||
"ResultFile" : "C:/cygwin64/home/koray/verilog/lab2/impl/temp/rtl_parser.result",
|
||||
"Top" : "",
|
||||
"VerilogStd" : "verilog_2001",
|
||||
"VhdlStd" : "vhdl_93"
|
||||
}
|
||||
@ -1,12 +0,0 @@
|
||||
<?xml version="1" encoding="UTF-8"?>
|
||||
<!DOCTYPE gowin-fpga-project>
|
||||
<Project>
|
||||
<Template>FPGA</Template>
|
||||
<Version>5</Version>
|
||||
<Device name="GW2A-18C" pn="GW2A-LV18PG256C8/I7">gw2a18c-011</Device>
|
||||
<FileList>
|
||||
<File path="src/lab2.v" type="file.verilog" enable="1"/>
|
||||
<File path="src/tb.v" type="file.verilog" enable="1"/>
|
||||
<File path="src/labwave" type="file.other" enable="1"/>
|
||||
</FileList>
|
||||
</Project>
|
||||
@ -1,17 +0,0 @@
|
||||
<?xml version="1" encoding="UTF-8"?>
|
||||
<!DOCTYPE ProjectUserData>
|
||||
<UserConfig>
|
||||
<Version>1.0</Version>
|
||||
<FlowState>
|
||||
<Process ID="Synthesis" State="2"/>
|
||||
<Process ID="Pnr" State="0"/>
|
||||
<Process ID="Gao" State="0"/>
|
||||
<Process ID="Rtl_Gao" State="2"/>
|
||||
</FlowState>
|
||||
<ResultFileList>
|
||||
<ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/lab2.vg"/>
|
||||
<ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/lab2_syn.rpt.html"/>
|
||||
<ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/lab2_syn_rsc.xml"/>
|
||||
</ResultFileList>
|
||||
<Ui>000000ff00000001fd0000000200000000000001700000013dfc0200000001fc000000630000013d0000000000fffffffaffffffff0200000003fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000000000000000fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f00630065007300730100000000ffffffff0000000000000000fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000000000000000000000030000050000000114fc0100000001fc0000000000000500000000a100fffffffa000000000100000002fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000007800fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000a100ffffff000003880000013d00000004000000040000000800000008fc000000010000000200000003000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e0045006400690074010000009bffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000157ffffffff0000000000000000</Ui>
|
||||
</UserConfig>
|
||||
@ -1,77 +0,0 @@
|
||||
$date
|
||||
Thu Apr 11 06:20:47 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module tb $end
|
||||
$var wire 1 ! w1 $end
|
||||
$var reg 1 " r1 $end
|
||||
$var reg 1 # r2 $end
|
||||
$var reg 1 $ r3 $end
|
||||
$var reg 1 % r4 $end
|
||||
$scope module uut $end
|
||||
$var wire 1 " A $end
|
||||
$var wire 1 & AD $end
|
||||
$var wire 1 ' An $end
|
||||
$var wire 1 ( AnBC $end
|
||||
$var wire 1 # B $end
|
||||
$var wire 1 ) Bn $end
|
||||
$var wire 1 $ C $end
|
||||
$var wire 1 * Cn $end
|
||||
$var wire 1 + CnD $end
|
||||
$var wire 1 % D $end
|
||||
$var wire 1 ! F $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
$comment Show the parameter values. $end
|
||||
$dumpall
|
||||
$end
|
||||
#0
|
||||
$dumpvars
|
||||
0+
|
||||
1*
|
||||
1)
|
||||
0(
|
||||
1'
|
||||
0&
|
||||
0%
|
||||
0$
|
||||
0#
|
||||
0"
|
||||
1!
|
||||
$end
|
||||
#50
|
||||
1+
|
||||
1%
|
||||
#100
|
||||
0+
|
||||
0*
|
||||
0%
|
||||
1$
|
||||
#150
|
||||
1%
|
||||
#200
|
||||
0!
|
||||
1*
|
||||
0)
|
||||
0%
|
||||
0$
|
||||
1#
|
||||
#250
|
||||
1!
|
||||
1+
|
||||
1%
|
||||
#300
|
||||
0+
|
||||
1(
|
||||
0*
|
||||
0%
|
||||
1$
|
||||
#350
|
||||
1%
|
||||
#400
|
||||
@ -1,126 +0,0 @@
|
||||
#! /c/Source/iverilog-install/bin/vvp
|
||||
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
|
||||
S_000001e2946aad20 .scope module, "tb" "tb" 2 1;
|
||||
.timescale 0 0;
|
||||
v000001e29475e7f0_0 .var "r1", 0 0;
|
||||
v000001e29475e6b0_0 .var "r2", 0 0;
|
||||
v000001e29475ec50_0 .var "r3", 0 0;
|
||||
v000001e29475e430_0 .var "r4", 0 0;
|
||||
v000001e29475ecf0_0 .net "w1", 0 0, L_000001e29475f0f0; 1 drivers
|
||||
S_000001e294717fc0 .scope module, "uut" "lab2" 2 6, 3 1 0, S_000001e2946aad20;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "C";
|
||||
.port_info 3 /INPUT 1 "D";
|
||||
.port_info 4 /OUTPUT 1 "F";
|
||||
L_000001e2947183d0 .functor NOT 1, v000001e29475e7f0_0, C4<0>, C4<0>, C4<0>;
|
||||
L_000001e2946e2bc0 .functor AND 1, L_000001e2947183d0, v000001e29475e6b0_0, v000001e29475ec50_0, C4<1>;
|
||||
L_000001e2946e2d20 .functor NOT 1, v000001e29475e6b0_0, C4<0>, C4<0>, C4<0>;
|
||||
L_000001e29475f390 .functor AND 1, v000001e29475e7f0_0, v000001e29475e430_0, C4<1>, C4<1>;
|
||||
L_000001e29475f4e0 .functor NOT 1, v000001e29475ec50_0, C4<0>, C4<0>, C4<0>;
|
||||
L_000001e29475f780 .functor AND 1, L_000001e29475f4e0, v000001e29475e430_0, C4<1>, C4<1>;
|
||||
L_000001e29475f0f0 .functor OR 1, L_000001e2946e2bc0, L_000001e2946e2d20, L_000001e29475f390, L_000001e29475f780;
|
||||
v000001e2946e2a40_0 .net "A", 0 0, v000001e29475e7f0_0; 1 drivers
|
||||
v000001e2946e28d0_0 .net "AD", 0 0, L_000001e29475f390; 1 drivers
|
||||
v000001e2946a9e10_0 .net "An", 0 0, L_000001e2947183d0; 1 drivers
|
||||
v000001e2946aaeb0_0 .net "AnBC", 0 0, L_000001e2946e2bc0; 1 drivers
|
||||
v000001e294718150_0 .net "B", 0 0, v000001e29475e6b0_0; 1 drivers
|
||||
v000001e2947181f0_0 .net "Bn", 0 0, L_000001e2946e2d20; 1 drivers
|
||||
v000001e294718290_0 .net "C", 0 0, v000001e29475ec50_0; 1 drivers
|
||||
v000001e294718330_0 .net "Cn", 0 0, L_000001e29475f4e0; 1 drivers
|
||||
v000001e294714e50_0 .net "CnD", 0 0, L_000001e29475f780; 1 drivers
|
||||
v000001e294714ef0_0 .net "D", 0 0, v000001e29475e430_0; 1 drivers
|
||||
v000001e29475e390_0 .net "F", 0 0, L_000001e29475f0f0; alias, 1 drivers
|
||||
.scope S_000001e2946aad20;
|
||||
T_0 ;
|
||||
%vpi_call 2 17 "$dumpfile", "dmp.vcd" {0 0 0};
|
||||
%vpi_call 2 18 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e7f0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e6b0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475ec50_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e430_0, 0, 1;
|
||||
%delay 50, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e7f0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e6b0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475ec50_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475e430_0, 0, 1;
|
||||
%delay 50, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e7f0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e6b0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475ec50_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e430_0, 0, 1;
|
||||
%delay 50, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e7f0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e6b0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475ec50_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475e430_0, 0, 1;
|
||||
%delay 50, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e7f0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475e6b0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475ec50_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e430_0, 0, 1;
|
||||
%delay 50, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e7f0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475e6b0_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475ec50_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475e430_0, 0, 1;
|
||||
%delay 50, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e7f0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475e6b0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475ec50_0, 0, 1;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e430_0, 0, 1;
|
||||
%delay 50, 0;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v000001e29475e7f0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475e6b0_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475ec50_0, 0, 1;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v000001e29475e430_0, 0, 1;
|
||||
%delay 50, 0;
|
||||
%vpi_call 2 27 "$display", v000001e29475ecf0_0 {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"tb.v";
|
||||
"lab2.v";
|
||||
@ -1,43 +0,0 @@
|
||||
#! /c/Source/iverilog-install/bin/vvp
|
||||
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
|
||||
S_0000016d6fd625e0 .scope module, "lab2" "lab2" 2 1;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "C";
|
||||
.port_info 3 /INPUT 1 "D";
|
||||
.port_info 4 /OUTPUT 1 "F";
|
||||
o0000016d6fd96f98 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
L_0000016d6fd62f70 .functor NOT 1, o0000016d6fd96f98, C4<0>, C4<0>, C4<0>;
|
||||
o0000016d6fd97058 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
o0000016d6fd970b8 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
L_0000016d6fedb7d0 .functor AND 1, L_0000016d6fd62f70, o0000016d6fd97058, o0000016d6fd970b8, C4<1>;
|
||||
L_0000016d6fedb840 .functor NOT 1, o0000016d6fd97058, C4<0>, C4<0>, C4<0>;
|
||||
o0000016d6fd97148 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
L_0000016d6fedb8b0 .functor AND 1, o0000016d6fd96f98, o0000016d6fd97148, C4<1>, C4<1>;
|
||||
L_0000016d6fedb920 .functor NOT 1, o0000016d6fd970b8, C4<0>, C4<0>, C4<0>;
|
||||
L_0000016d6fedb990 .functor AND 1, L_0000016d6fedb920, o0000016d6fd97148, C4<1>, C4<1>;
|
||||
L_0000016d6fedba00 .functor OR 1, L_0000016d6fedb7d0, L_0000016d6fedb840, L_0000016d6fedb8b0, L_0000016d6fedb990;
|
||||
v0000016d6fd62b30_0 .net "A", 0 0, o0000016d6fd96f98; 0 drivers
|
||||
v0000016d6fd62d50_0 .net "AD", 0 0, L_0000016d6fedb8b0; 1 drivers
|
||||
v0000016d6fd62770_0 .net "An", 0 0, L_0000016d6fd62f70; 1 drivers
|
||||
v0000016d6fd62810_0 .net "AnBC", 0 0, L_0000016d6fedb7d0; 1 drivers
|
||||
v0000016d6fd628b0_0 .net "B", 0 0, o0000016d6fd97058; 0 drivers
|
||||
v0000016d6fededb0_0 .net "Bn", 0 0, L_0000016d6fedb840; 1 drivers
|
||||
v0000016d6fedee50_0 .net "C", 0 0, o0000016d6fd970b8; 0 drivers
|
||||
v0000016d6fedeef0_0 .net "Cn", 0 0, L_0000016d6fedb920; 1 drivers
|
||||
v0000016d6fedb600_0 .net "CnD", 0 0, L_0000016d6fedb990; 1 drivers
|
||||
v0000016d6fedb730_0 .net "D", 0 0, o0000016d6fd97148; 0 drivers
|
||||
v0000016d6fd90c30_0 .net "F", 0 0, L_0000016d6fedba00; 1 drivers
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 3;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"lab2.v";
|
||||
@ -1,24 +0,0 @@
|
||||
module lab2(
|
||||
input A,
|
||||
input B,
|
||||
input C,
|
||||
input D,
|
||||
output F
|
||||
);
|
||||
|
||||
wire An, Bn, Cn;
|
||||
wire AnBC, AD, CnD;
|
||||
|
||||
not n1 (An, A);
|
||||
and (AnBC, An, B, C);
|
||||
|
||||
not (Bn, B);
|
||||
and (AD, A, D);
|
||||
|
||||
not (Cn, C);
|
||||
and (CnD, Cn, D);
|
||||
|
||||
or (F, AnBC, Bn, AD, CnD);
|
||||
|
||||
|
||||
endmodule
|
||||
@ -1,43 +0,0 @@
|
||||
#! /c/Source/iverilog-install/bin/vvp
|
||||
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
|
||||
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
|
||||
S_000001e0df4625e0 .scope module, "f_lab2" "f_lab2" 2 1;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "C";
|
||||
.port_info 3 /INPUT 1 "D";
|
||||
.port_info 4 /OUTPUT 1 "F";
|
||||
o000001e0df496fd8 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
L_000001e0df462f70 .functor NOT 1, o000001e0df496fd8, C4<0>, C4<0>, C4<0>;
|
||||
o000001e0df497098 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
o000001e0df4970f8 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
L_000001e0df64aa10 .functor AND 1, L_000001e0df462f70, o000001e0df497098, o000001e0df4970f8, C4<1>;
|
||||
L_000001e0df64aa80 .functor NOT 1, o000001e0df497098, C4<0>, C4<0>, C4<0>;
|
||||
o000001e0df497188 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
L_000001e0df64aaf0 .functor AND 1, o000001e0df496fd8, o000001e0df497188, C4<1>, C4<1>;
|
||||
L_000001e0df64ab60 .functor NOT 1, o000001e0df4970f8, C4<0>, C4<0>, C4<0>;
|
||||
L_000001e0df64abd0 .functor AND 1, L_000001e0df64ab60, o000001e0df497188, C4<1>, C4<1>;
|
||||
L_000001e0df64ac40 .functor OR 1, L_000001e0df64aa10, L_000001e0df64aa80, L_000001e0df64aaf0, L_000001e0df64abd0;
|
||||
v000001e0df462b30_0 .net "A", 0 0, o000001e0df496fd8; 0 drivers
|
||||
v000001e0df462d50_0 .net "AD", 0 0, L_000001e0df64aaf0; 1 drivers
|
||||
v000001e0df462770_0 .net "An", 0 0, L_000001e0df462f70; 1 drivers
|
||||
v000001e0df462810_0 .net "AnBC", 0 0, L_000001e0df64aa10; 1 drivers
|
||||
v000001e0df4628b0_0 .net "B", 0 0, o000001e0df497098; 0 drivers
|
||||
v000001e0df64ed90_0 .net "Bn", 0 0, L_000001e0df64aa80; 1 drivers
|
||||
v000001e0df64ee30_0 .net "C", 0 0, o000001e0df4970f8; 0 drivers
|
||||
v000001e0df64eed0_0 .net "Cn", 0 0, L_000001e0df64ab60; 1 drivers
|
||||
v000001e0df64a840_0 .net "CnD", 0 0, L_000001e0df64abd0; 1 drivers
|
||||
v000001e0df64a970_0 .net "D", 0 0, o000001e0df497188; 0 drivers
|
||||
v000001e0df492660_0 .net "F", 0 0, L_000001e0df64ac40; 1 drivers
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 3;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
".\f_lab2.v";
|
||||
@ -1,32 +0,0 @@
|
||||
module tb();
|
||||
|
||||
reg r1, r2, r3, r4;
|
||||
wire w1;
|
||||
|
||||
lab2 uut(
|
||||
.A(r1),
|
||||
.B(r2),
|
||||
.C(r3),
|
||||
.D(r4),
|
||||
.F(w1)
|
||||
);
|
||||
|
||||
// test uut(r1, r2, w1, w2, w3);
|
||||
|
||||
initial begin
|
||||
$dumpfile("dmp.vcd");
|
||||
$dumpvars;
|
||||
r1 = 1'b0; r2 = 1'b0; r3 = 1'b0; r4 = 1'b0; #50;
|
||||
r1 = 1'b0; r2 = 1'b0; r3 = 1'b0; r4 = 1'b1; #50;
|
||||
r1 = 1'b0; r2 = 1'b0; r3 = 1'b1; r4 = 1'b0; #50;
|
||||
r1 = 1'b0; r2 = 1'b0; r3 = 1'b1; r4 = 1'b1; #50;
|
||||
r1 = 1'b0; r2 = 1'b1; r3 = 1'b0; r4 = 1'b0; #50;
|
||||
r1 = 1'b0; r2 = 1'b1; r3 = 1'b0; r4 = 1'b1; #50;
|
||||
r1 = 1'b0; r2 = 1'b1; r3 = 1'b1; r4 = 1'b0; #50;
|
||||
r1 = 1'b0; r2 = 1'b1; r3 = 1'b1; r4 = 1'b1; #50;
|
||||
$display(w1);
|
||||
end
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
@ -1,27 +0,0 @@
|
||||
GowinSynthesis start
|
||||
Running parser ...
|
||||
Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\fullAdder.v'
|
||||
Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\halfAdder.v'
|
||||
Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\mult2bit.v'
|
||||
Compiling module 'mult2bit'("C:\cygwin64\home\koray\verilog\lab3\src\mult2bit.v":1)
|
||||
Compiling module 'halfAdder'("C:\cygwin64\home\koray\verilog\lab3\src\halfAdder.v":1)
|
||||
NOTE (EX0101) : Current top module is "mult2bit"
|
||||
[5%] Running netlist conversion ...
|
||||
Running device independent optimization ...
|
||||
[10%] Optimizing Phase 0 completed
|
||||
[15%] Optimizing Phase 1 completed
|
||||
[25%] Optimizing Phase 2 completed
|
||||
Running inference ...
|
||||
[30%] Inferring Phase 0 completed
|
||||
[40%] Inferring Phase 1 completed
|
||||
[50%] Inferring Phase 2 completed
|
||||
[55%] Inferring Phase 3 completed
|
||||
Running technical mapping ...
|
||||
[60%] Tech-Mapping Phase 0 completed
|
||||
[65%] Tech-Mapping Phase 1 completed
|
||||
[75%] Tech-Mapping Phase 2 completed
|
||||
[80%] Tech-Mapping Phase 3 completed
|
||||
[90%] Tech-Mapping Phase 4 completed
|
||||
[95%] Generate netlist file "C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg" completed
|
||||
[100%] Generate report file "C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3_syn.rpt.html" completed
|
||||
GowinSynthesis finish
|
||||
@ -1,21 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE gowin-synthesis-project>
|
||||
<Project>
|
||||
<Version>beta</Version>
|
||||
<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
|
||||
<FileList>
|
||||
<File path="C:\cygwin64\home\koray\verilog\lab3\src\fullAdder.v" type="verilog"/>
|
||||
<File path="C:\cygwin64\home\koray\verilog\lab3\src\halfAdder.v" type="verilog"/>
|
||||
<File path="C:\cygwin64\home\koray\verilog\lab3\src\mult2bit.v" type="verilog"/>
|
||||
</FileList>
|
||||
<OptionList>
|
||||
<Option type="disable_insert_pad" value="0"/>
|
||||
<Option type="global_freq" value="100.000"/>
|
||||
<Option type="looplimit" value="2000"/>
|
||||
<Option type="output_file" value="C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg"/>
|
||||
<Option type="print_all_synthesis_warning" value="0"/>
|
||||
<Option type="ram_rw_check" value="0"/>
|
||||
<Option type="verilog_language" value="verilog-2001"/>
|
||||
<Option type="vhdl_language" value="vhdl-1993"/>
|
||||
</OptionList>
|
||||
</Project>
|
||||
@ -1,144 +0,0 @@
|
||||
//
|
||||
//Written by GowinSynthesis
|
||||
//Tool Version "V1.9.9.02"
|
||||
//Sat May 4 01:07:38 2024
|
||||
|
||||
//Source file index table:
|
||||
//file0 "\C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v"
|
||||
//file1 "\C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v"
|
||||
//file2 "\C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v"
|
||||
`timescale 100 ps/100 ps
|
||||
module halfAdder (
|
||||
A_d,
|
||||
B_d,
|
||||
C_d
|
||||
)
|
||||
;
|
||||
input [1:0] A_d;
|
||||
input [1:0] B_d;
|
||||
output [1:1] C_d;
|
||||
wire VCC;
|
||||
wire GND;
|
||||
LUT4 C_d_1_s (
|
||||
.F(C_d[1]),
|
||||
.I0(A_d[1]),
|
||||
.I1(B_d[0]),
|
||||
.I2(A_d[0]),
|
||||
.I3(B_d[1])
|
||||
);
|
||||
defparam C_d_1_s.INIT=16'h7888;
|
||||
VCC VCC_cZ (
|
||||
.V(VCC)
|
||||
);
|
||||
GND GND_cZ (
|
||||
.G(GND)
|
||||
);
|
||||
endmodule /* halfAdder */
|
||||
module halfAdder_0 (
|
||||
A_d,
|
||||
B_d,
|
||||
C_d
|
||||
)
|
||||
;
|
||||
input [1:0] A_d;
|
||||
input [1:0] B_d;
|
||||
output [3:2] C_d;
|
||||
wire VCC;
|
||||
wire GND;
|
||||
LUT4 C_d_3_s (
|
||||
.F(C_d[3]),
|
||||
.I0(A_d[0]),
|
||||
.I1(B_d[0]),
|
||||
.I2(A_d[1]),
|
||||
.I3(B_d[1])
|
||||
);
|
||||
defparam C_d_3_s.INIT=16'h7000;
|
||||
LUT4 C_d_2_s (
|
||||
.F(C_d[2]),
|
||||
.I0(A_d[1]),
|
||||
.I1(B_d[0]),
|
||||
.I2(A_d[0]),
|
||||
.I3(B_d[1])
|
||||
);
|
||||
defparam C_d_2_s.INIT=16'h8000;
|
||||
VCC VCC_cZ (
|
||||
.V(VCC)
|
||||
);
|
||||
GND GND_cZ (
|
||||
.G(GND)
|
||||
);
|
||||
endmodule /* halfAdder_0 */
|
||||
module mult2bit (
|
||||
A,
|
||||
B,
|
||||
C
|
||||
)
|
||||
;
|
||||
input [1:0] A;
|
||||
input [1:0] B;
|
||||
output [3:0] C;
|
||||
wire [1:0] A_d;
|
||||
wire [1:0] B_d;
|
||||
wire [0:0] C_d;
|
||||
wire [1:1] C_d_0;
|
||||
wire [3:2] C_d_1;
|
||||
wire VCC;
|
||||
wire GND;
|
||||
IBUF A_0_ibuf (
|
||||
.O(A_d[0]),
|
||||
.I(A[0])
|
||||
);
|
||||
IBUF A_1_ibuf (
|
||||
.O(A_d[1]),
|
||||
.I(A[1])
|
||||
);
|
||||
IBUF B_0_ibuf (
|
||||
.O(B_d[0]),
|
||||
.I(B[0])
|
||||
);
|
||||
IBUF B_1_ibuf (
|
||||
.O(B_d[1]),
|
||||
.I(B[1])
|
||||
);
|
||||
OBUF C_0_obuf (
|
||||
.O(C[0]),
|
||||
.I(C_d[0])
|
||||
);
|
||||
OBUF C_1_obuf (
|
||||
.O(C[1]),
|
||||
.I(C_d_0[1])
|
||||
);
|
||||
OBUF C_2_obuf (
|
||||
.O(C[2]),
|
||||
.I(C_d_1[2])
|
||||
);
|
||||
OBUF C_3_obuf (
|
||||
.O(C[3]),
|
||||
.I(C_d_1[3])
|
||||
);
|
||||
LUT2 C_d_0_s (
|
||||
.F(C_d[0]),
|
||||
.I0(B_d[0]),
|
||||
.I1(A_d[0])
|
||||
);
|
||||
defparam C_d_0_s.INIT=4'h8;
|
||||
halfAdder h0 (
|
||||
.A_d(A_d[1:0]),
|
||||
.B_d(B_d[1:0]),
|
||||
.C_d(C_d_0[1])
|
||||
);
|
||||
halfAdder_0 h1 (
|
||||
.A_d(A_d[1:0]),
|
||||
.B_d(B_d[1:0]),
|
||||
.C_d(C_d_1[3:2])
|
||||
);
|
||||
VCC VCC_cZ (
|
||||
.V(VCC)
|
||||
);
|
||||
GND GND_cZ (
|
||||
.G(GND)
|
||||
);
|
||||
GSR GSR (
|
||||
.GSRI(VCC)
|
||||
);
|
||||
endmodule /* mult2bit */
|
||||
@ -1,173 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>synthesis Report</title>
|
||||
<style type="text/css">
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
|
||||
div#main_wrapper{ width: 100%; }
|
||||
div#content { margin-left: 350px; margin-right: 30px; }
|
||||
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
|
||||
div#catalog ul { list-style-type: none; }
|
||||
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
|
||||
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
|
||||
div#catalog a:visited { color: #0084ff; }
|
||||
div#catalog a:hover { color: #fff; background: #0084ff; }
|
||||
hr { margin-top: 30px; margin-bottom: 30px; }
|
||||
h1, h3 { text-align: center; }
|
||||
h1 {margin-top: 50px; }
|
||||
table, th, td { border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { padding: 5px 5px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
|
||||
table.detail_table td.label { min-width: 100px; width: 8%;}
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="main_wrapper">
|
||||
<div id="catalog_wrapper">
|
||||
<div id="catalog">
|
||||
<ul>
|
||||
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
|
||||
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
|
||||
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
|
||||
<ul>
|
||||
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
|
||||
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
|
||||
</ul>
|
||||
</li>
|
||||
</ul>
|
||||
</div><!-- catalog -->
|
||||
</div><!-- catalog_wrapper -->
|
||||
<div id="content">
|
||||
<h1><a name="about">Synthesis Messages</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Report Title</td>
|
||||
<td>GowinSynthesis Report</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Design File</td>
|
||||
<td>C:\cygwin64\home\koray\verilog\lab3\src\fullAdder.v<br>
|
||||
C:\cygwin64\home\koray\verilog\lab3\src\halfAdder.v<br>
|
||||
C:\cygwin64\home\koray\verilog\lab3\src\mult2bit.v<br>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">GowinSynthesis Constraints File</td>
|
||||
<td>---</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Tool Version</td>
|
||||
<td>V1.9.9.02</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Part Number</td>
|
||||
<td>GW2A-LV18PG256C8/I7</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device</td>
|
||||
<td>GW2A-18</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device Version</td>
|
||||
<td>C</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Created Time</td>
|
||||
<td>Sat May 4 01:07:38 2024
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Legal Announcement</td>
|
||||
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="summary">Synthesis Details</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Top Level Module</td>
|
||||
<td>mult2bit</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Synthesis Process</td>
|
||||
<td>Running parser:<br/> CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.134s, Peak memory usage = 417.762MB<br/>Running netlist conversion:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/> Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/>Running inference:<br/> Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/>Running technical mapping:<br/> Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Tech-Mapping Phase 3: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.308s, Peak memory usage = 417.762MB<br/> Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/>Generate output files:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 417.762MB<br/></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Total Time and Memory Usage</td>
|
||||
<td>CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.447s, Peak memory usage = 417.762MB</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="resource">Resource</a></h1>
|
||||
<h2><a name="usage">Resource Usage Summary</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label"><b>Resource</b></td>
|
||||
<td><b>Usage</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>I/O Port </b></td>
|
||||
<td>8</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>I/O Buf </b></td>
|
||||
<td>8</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    IBUF</td>
|
||||
<td>4</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    OBUF</td>
|
||||
<td>4</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>LUT </b></td>
|
||||
<td>4</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    LUT2</td>
|
||||
<td>1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    LUT4</td>
|
||||
<td>3</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="utilization">Resource Utilization Summary</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label"><b>Resource</b></td>
|
||||
<td><b>Usage</b></td>
|
||||
<td><b>Utilization</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Logic</td>
|
||||
<td>4(4 LUT, 0 ALU) / 20736</td>
|
||||
<td><1%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Register</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">  --Register as Latch</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">  --Register as FF</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">BSRAM</td>
|
||||
<td>0 / 46</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
||||
@ -1,66 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>Hierarchy Module Resource</title>
|
||||
<style type="text/css">
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
|
||||
div#main_wrapper{ width: 100%; }
|
||||
h1 {text-align: center; }
|
||||
h1 {margin-top: 36px; }
|
||||
table, th, td { border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { align = "center"; padding: 5px 2px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="main_wrapper">
|
||||
<div id="content">
|
||||
<h1>Hierarchy Module Resource</h1>
|
||||
<table>
|
||||
<tr>
|
||||
<th class="label">MODULE NAME</th>
|
||||
<th class="label">REG NUMBER</th>
|
||||
<th class="label">ALU NUMBER</th>
|
||||
<th class="label">LUT NUMBER</th>
|
||||
<th class="label">DSP NUMBER</th>
|
||||
<th class="label">BSRAM NUMBER</th>
|
||||
<th class="label">SSRAM NUMBER</th>
|
||||
<th class="label">ROM16 NUMBER</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">mult2bit (C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v)</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">1</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
</tr>
|
||||
<td class="label">    |--h0
|
||||
(C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v)</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">1</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
</tr>
|
||||
<td class="label">    |--h1
|
||||
(C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v)</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">2</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
||||
@ -1,5 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Module name="mult2bit" Lut="1" T_Lut="4(1)">
|
||||
<SubModule name="h0" Lut="1" T_Lut="1(1)"/>
|
||||
<SubModule name="h1" Lut="2" T_Lut="2(2)"/>
|
||||
</Module>
|
||||
@ -1,88 +0,0 @@
|
||||
{
|
||||
"BACKGROUND_PROGRAMMING" : "off",
|
||||
"COMPRESS" : false,
|
||||
"CPU" : false,
|
||||
"CRC_CHECK" : true,
|
||||
"Clock_Route_Order" : 0,
|
||||
"Correct_Hold_Violation" : true,
|
||||
"DONE" : false,
|
||||
"DOWNLOAD_SPEED" : "default",
|
||||
"Disable_Insert_Pad" : false,
|
||||
"ENABLE_CTP" : false,
|
||||
"ENABLE_MERGE_MODE" : false,
|
||||
"ENCRYPTION_KEY" : false,
|
||||
"ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
|
||||
"ERROR_DECTION_AND_CORRECTION" : false,
|
||||
"ERROR_DECTION_ONLY" : false,
|
||||
"ERROR_INJECTION" : false,
|
||||
"EXTERNAL_MASTER_CONFIG_CLOCK" : false,
|
||||
"Enable_DSRM" : false,
|
||||
"FORMAT" : "binary",
|
||||
"FREQUENCY_DIVIDER" : "",
|
||||
"Generate_Constraint_File_of_Ports" : false,
|
||||
"Generate_IBIS_File" : false,
|
||||
"Generate_Plain_Text_Timing_Report" : false,
|
||||
"Generate_Post_PNR_Simulation_Model_File" : false,
|
||||
"Generate_Post_Place_File" : false,
|
||||
"Generate_SDF_File" : false,
|
||||
"Generate_VHDL_Post_PNR_Simulation_Model_File" : false,
|
||||
"Global_Freq" : "default",
|
||||
"GwSyn_Loop_Limit" : 2000,
|
||||
"HOTBOOT" : false,
|
||||
"I2C" : false,
|
||||
"I2C_SLAVE_ADDR" : "00",
|
||||
"IncludePath" : [
|
||||
|
||||
],
|
||||
"Incremental_Compile" : "",
|
||||
"Initialize_Primitives" : false,
|
||||
"JTAG" : false,
|
||||
"MODE_IO" : false,
|
||||
"MSPI" : false,
|
||||
"MSPI_JUMP" : false,
|
||||
"MULTIBOOT_ADDRESS_WIDTH" : "24",
|
||||
"MULTIBOOT_MODE" : "Normal",
|
||||
"MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000",
|
||||
"MULTIJUMP_ADDRESS_WIDTH" : "24",
|
||||
"MULTIJUMP_MODE" : "Normal",
|
||||
"MULTIJUMP_SPI_FLASH_ADDRESS" : "000000",
|
||||
"Multi_Boot" : true,
|
||||
"OUTPUT_BASE_NAME" : "lab3",
|
||||
"POWER_ON_RESET_MONITOR" : true,
|
||||
"PRINT_BSRAM_VALUE" : true,
|
||||
"PROGRAM_DONE_BYPASS" : false,
|
||||
"PlaceInRegToIob" : true,
|
||||
"PlaceIoRegToIob" : true,
|
||||
"PlaceOutRegToIob" : true,
|
||||
"Place_Option" : "0",
|
||||
"Process_Configuration_Verion" : "1.0",
|
||||
"Promote_Physical_Constraint_Warning_to_Error" : true,
|
||||
"READY" : false,
|
||||
"RECONFIG_N" : false,
|
||||
"Ram_RW_Check" : false,
|
||||
"Replicate_Resources" : false,
|
||||
"Report_Auto-Placed_Io_Information" : false,
|
||||
"Route_Maxfan" : 23,
|
||||
"Route_Option" : "0",
|
||||
"Run_Timing_Driven" : true,
|
||||
"SECURE_MODE" : false,
|
||||
"SECURITY_BIT" : true,
|
||||
"SEU_HANDLER" : false,
|
||||
"SEU_HANDLER_CHECKSUM" : false,
|
||||
"SEU_HANDLER_MODE" : "auto",
|
||||
"SSPI" : false,
|
||||
"STOP_SEU_HANDLER" : false,
|
||||
"Show_All_Warnings" : false,
|
||||
"Synthesize_tool" : "GowinSyn",
|
||||
"TclPre" : "",
|
||||
"TopModule" : "",
|
||||
"USERCODE" : "default",
|
||||
"Unused_Pin" : "As_input_tri_stated_with_pull_up",
|
||||
"VCCAUX" : 3.3,
|
||||
"VCCX" : "3.3",
|
||||
"VHDL_Standard" : "VHDL_Std_1993",
|
||||
"Verilog_Standard" : "Vlg_Std_2001",
|
||||
"WAKE_UP" : "0",
|
||||
"show_all_warnings" : false,
|
||||
"turn_off_bg" : false
|
||||
}
|
||||
@ -1,12 +0,0 @@
|
||||
-d C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg
|
||||
-p GW2A-18C-PBGA256-8
|
||||
-pn GW2A-LV18PG256C8/I7
|
||||
-cfg C:\cygwin64\home\koray\verilog\lab3\impl\pnr\device.cfg
|
||||
-bit
|
||||
-tr
|
||||
-ph
|
||||
-timing
|
||||
-cst_error
|
||||
-correct_hold 1
|
||||
-route_maxfan 23
|
||||
-global_freq 100.000
|
||||
@ -1,21 +0,0 @@
|
||||
set JTAG regular_io = false
|
||||
set SSPI regular_io = false
|
||||
set MSPI regular_io = false
|
||||
set READY regular_io = false
|
||||
set DONE regular_io = false
|
||||
set I2C regular_io = false
|
||||
set RECONFIG_N regular_io = false
|
||||
set CRC_check = true
|
||||
set compress = false
|
||||
set encryption = false
|
||||
set security_bit_enable = true
|
||||
set bsram_init_fuse_print = true
|
||||
set background_programming = off
|
||||
set secure_mode = false
|
||||
set program_done_bypass = false
|
||||
set wake_up = 0
|
||||
set format = binary
|
||||
set power_on_reset_monitor = true
|
||||
set multiboot_spi_flash_address = 0x00000000
|
||||
set vccx = 3.3
|
||||
set unused_pin = default
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
File diff suppressed because it is too large
Load Diff
@ -1,27 +0,0 @@
|
||||
Reading netlist file: "C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg"
|
||||
Parsing netlist file "C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg" completed
|
||||
Processing netlist completed
|
||||
Running placement......
|
||||
[10%] Placement Phase 0 completed
|
||||
[20%] Placement Phase 1 completed
|
||||
[30%] Placement Phase 2 completed
|
||||
[50%] Placement Phase 3 completed
|
||||
Running routing......
|
||||
[60%] Routing Phase 0 completed
|
||||
[70%] Routing Phase 1 completed
|
||||
[80%] Routing Phase 2 completed
|
||||
[90%] Routing Phase 3 completed
|
||||
Running timing analysis......
|
||||
[95%] Timing analysis completed
|
||||
Placement and routing completed
|
||||
Bitstream generation in progress......
|
||||
Bitstream generation completed
|
||||
Running power analysis......
|
||||
[100%] Power analysis completed
|
||||
Generate file "C:\cygwin64\home\koray\verilog\lab3\impl\pnr\lab3.power.html" completed
|
||||
Generate file "C:\cygwin64\home\koray\verilog\lab3\impl\pnr\lab3.pin.html" completed
|
||||
Generate file "C:\cygwin64\home\koray\verilog\lab3\impl\pnr\lab3.rpt.html" completed
|
||||
Generate file "C:\cygwin64\home\koray\verilog\lab3\impl\pnr\lab3.rpt.txt" completed
|
||||
Generate file "C:\cygwin64\home\koray\verilog\lab3\impl\pnr\lab3.tr.html" completed
|
||||
Sat May 4 01:07:45 2024
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,266 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//ENhttp://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>Power Analysis Report</title>
|
||||
<style type="text/css">
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
|
||||
div#main_wrapper { width: 100%; }
|
||||
div#content { margin-left: 350px; margin-right: 30px; }
|
||||
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
|
||||
div#catalog ul { list-style-type: none; }
|
||||
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
|
||||
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
|
||||
div#catalog a:visited { color: #0084ff; }
|
||||
div#catalog a:hover { color: #fff; background: #0084ff; }
|
||||
hr { margin-top: 30px; margin-bottom: 30px; }
|
||||
h1, h3 { text-align: center; }
|
||||
h1 {margin-top: 50px; }
|
||||
table, th, td {white-space:pre; border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { padding: 5px 5px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
|
||||
table.thermal_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
|
||||
table.Configure_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
|
||||
table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="main_wrapper">
|
||||
<div id="catalog_wrapper">
|
||||
<div id="catalog">
|
||||
<ul>
|
||||
<li><a href="#Message" style=" font-size: 16px;">Power Messages</a>
|
||||
</li>
|
||||
<li><a href="#Summary" style=" font-size: 16px;">Power Summary</a>
|
||||
<ul>
|
||||
<li><a href="#Power_Info" style=" font-size: 14px;">Power Information</a></li>
|
||||
<li><a href="#Thermal_Info" style=" font-size: 14px;">Thermal Information</a></li>
|
||||
<li><a href="#Configure_Info" style=" font-size: 14px;">Configure Information</a></li>
|
||||
<li><a href="#Supply_Summary" style=" font-size: 14px;">Supply Information</a></li>
|
||||
</ul>
|
||||
</li>
|
||||
<li><a href="#Detail" style=" font-size: 16px;">Power Details</a>
|
||||
<ul>
|
||||
<li><a href="#By_Block_Type" style=" font-size: 14px;">Power By Block Type</a></li>
|
||||
<li><a href="#By_Hierarchy" style=" font-size: 14px;">Power By Hierarchy</a></li>
|
||||
<li><a href="#By_Clock_Domain" style=" font-size: 14px;">Power By Clock Domain</a></li>
|
||||
</ul>
|
||||
</li>
|
||||
</ul>
|
||||
</div><!-- catalog -->
|
||||
</div><!-- catalog_wrapper -->
|
||||
<div id="content">
|
||||
<h1><a name="Message">Power Messages</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Report Title</td>
|
||||
<td>Power Analysis Report</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Design File</td>
|
||||
<td>C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Physical Constraints File</td>
|
||||
<td>---</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Timing Constraints File</td>
|
||||
<td>---</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Tool Version</td>
|
||||
<td>V1.9.9.02</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Part Number</td>
|
||||
<td>GW2A-LV18PG256C8/I7</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device</td>
|
||||
<td>GW2A-18</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device Version</td>
|
||||
<td>C</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Created Time</td>
|
||||
<td>Sat May 4 01:07:45 2024
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Legal Announcement</td>
|
||||
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="Summary">Power Summary</a></h1>
|
||||
<h2><a name="Power_Info">Power Information:</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Total Power (mW)</td>
|
||||
<td>92.439</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Quiescent Power (mW)</td>
|
||||
<td>91.608</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Dynamic Power (mW)</td>
|
||||
<td>0.832</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="Thermal_Info">Thermal Information:</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Junction Temperature</td>
|
||||
<td>27.960</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Theta JA</td>
|
||||
<td>32.020</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Max Allowed Ambient Temperature</td>
|
||||
<td>82.040</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="Configure_Info">Configure Information:</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Default IO Toggle Rate</td>
|
||||
<td>0.125</td>
|
||||
</tr>
|
||||
<td class="label">Default Remain Toggle Rate</td>
|
||||
<td>0.125</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Use Vectorless Estimation</td>
|
||||
<td>false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Filter Glitches</td>
|
||||
<td>false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Related Vcd File</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Related Saif File</td>
|
||||
<td></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Use Custom Theta JA</td>
|
||||
<td>false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Air Flow</td>
|
||||
<td>LFM_0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Heat Sink</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Use Custom Theta SA</td>
|
||||
<td>false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Board Thermal Model</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Use Custom Theta JB</td>
|
||||
<td>false</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Ambient Temperature</td>
|
||||
<td>25.000
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="Supply_Summary">Supply Information:</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<th class="label">Voltage Source</th>
|
||||
<th class="label">Voltage</th>
|
||||
<th class="label">Dynamic Current(mA)</th>
|
||||
<th class="label">Quiescent Current(mA)</th>
|
||||
<th class="label">Power(mW)</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>VCC</td>
|
||||
<td>1.000</td>
|
||||
<td>0.158</td>
|
||||
<td>61.510</td>
|
||||
<td>61.668</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>VCCX</td>
|
||||
<td>2.500</td>
|
||||
<td>0.158</td>
|
||||
<td>11.364</td>
|
||||
<td>28.803</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>VCCIO18</td>
|
||||
<td>1.800</td>
|
||||
<td>0.155</td>
|
||||
<td>0.938</td>
|
||||
<td>1.968</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="Detail">Power Details</a></h1>
|
||||
<h2><a name="By_Block_Type">Power By Block Type:</a></h2>
|
||||
<table class="detail_table">
|
||||
<tr>
|
||||
<th class="label">Block Type</th>
|
||||
<th class="label">Total Power(mW)</th>
|
||||
<th class="label">Static Power(mW)</th>
|
||||
<th class="label">Average Toggle Rate(millions of transitions/sec)</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>IO</td>
|
||||
<td>3.335
|
||||
<td>2.503
|
||||
<td>6.250
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="By_Hierarchy">Power By Hierarchy:</a></h2>
|
||||
<table class="detail_table">
|
||||
<tr>
|
||||
<th class="label">Hierarchy Entity</th>
|
||||
<th class="label">Total Power(mW)</th>
|
||||
<th class="label">Block Dynamic Power(mW)</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>mult2bit</td>
|
||||
<td>0.000</td>
|
||||
<td>0.000(0.000)</td>
|
||||
<tr>
|
||||
<td>mult2bit/h0/</td>
|
||||
<td>0.000</td>
|
||||
<td>0.000(0.000)</td>
|
||||
<tr>
|
||||
<td>mult2bit/h1/</td>
|
||||
<td>0.000</td>
|
||||
<td>0.000(0.000)</td>
|
||||
</table>
|
||||
<h2><a name="By_Clock_Domain">Power By Clock Domain:</a></h2>
|
||||
<table class="detail_table">
|
||||
<tr>
|
||||
<th class="label">Clock Domain</th>
|
||||
<th class="label">Clock Frequency(Mhz)</th>
|
||||
<th class="label">Total Dynamic Power(mW)</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>NO CLOCK DOMAIN</td>
|
||||
<td>0.000</td>
|
||||
<td>0.000</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,346 +0,0 @@
|
||||
//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
|
||||
//All rights reserved.
|
||||
|
||||
|
||||
1. PnR Messages
|
||||
|
||||
<Report Title>: PnR Report
|
||||
<Design File>: C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg
|
||||
<Physical Constraints File>: ---
|
||||
<Timing Constraints File>: ---
|
||||
<Tool Version>: V1.9.9.02
|
||||
<Part Number>: GW2A-LV18PG256C8/I7
|
||||
<Device>: GW2A-18
|
||||
<Device Version>: C
|
||||
<Created Time>:Sat May 4 01:07:45 2024
|
||||
|
||||
|
||||
2. PnR Details
|
||||
|
||||
Running placement:
|
||||
Placement Phase 0: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s
|
||||
Placement Phase 1: CPU time = 0h 0m 0.546s, Elapsed time = 0h 0m 0.545s
|
||||
Placement Phase 2: CPU time = 0h 0m 0.005s, Elapsed time = 0h 0m 0.005s
|
||||
Placement Phase 3: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
|
||||
Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
|
||||
Running routing:
|
||||
Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
|
||||
Routing Phase 1: CPU time = 0h 0m 0.314s, Elapsed time = 0h 0m 0.314s
|
||||
Routing Phase 2: CPU time = 0h 0m 0.152s, Elapsed time = 0h 0m 0.152s
|
||||
Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
|
||||
Total Routing: CPU time = 0h 0m 0.466s, Elapsed time = 0h 0m 0.466s
|
||||
Generate output files:
|
||||
CPU time = 0h 0m 3s, Elapsed time = 0h 0m 3s
|
||||
|
||||
Total Time and Memory Usage: CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 420MB
|
||||
|
||||
|
||||
3. Resource Usage Summary
|
||||
|
||||
----------------------------------------------------------
|
||||
Resources | Usage
|
||||
----------------------------------------------------------
|
||||
Logic | 4/20736 <1%
|
||||
--LUT,ALU,ROM16 | 4(4 LUT, 0 ALU, 0 ROM16)
|
||||
--SSRAM(RAM16) | 0
|
||||
Register | 0/16173 0%
|
||||
--Logic Register as Latch | 0/15552 0%
|
||||
--Logic Register as FF | 0/15552 0%
|
||||
--I/O Register as Latch | 0/621 0%
|
||||
--I/O Register as FF | 0/621 0%
|
||||
CLS | 3/10368 <1%
|
||||
I/O Port | 8
|
||||
I/O Buf | 8
|
||||
--Input Buf | 4
|
||||
--Output Buf | 4
|
||||
--Inout Buf | 0
|
||||
IOLOGIC | 0%
|
||||
BSRAM | 0%
|
||||
DSP | 0%
|
||||
PLL | 0/4 0%
|
||||
DCS | 0/8 0%
|
||||
DQCE | 0/24 0%
|
||||
OSC | 0/1 0%
|
||||
CLKDIV | 0/8 0%
|
||||
DLLDLY | 0/8 0%
|
||||
DQS | 0/9 0%
|
||||
DHCEN | 0/16 0%
|
||||
==========================================================
|
||||
|
||||
|
||||
|
||||
4. I/O Bank Usage Summary
|
||||
|
||||
-----------------------
|
||||
I/O Bank | Usage
|
||||
-----------------------
|
||||
bank 0 | 4/29(13%)
|
||||
bank 1 | 0/20(0%)
|
||||
bank 2 | 0/20(0%)
|
||||
bank 3 | 0/32(0%)
|
||||
bank 4 | 0/36(0%)
|
||||
bank 5 | 0/36(0%)
|
||||
bank 6 | 0/18(0%)
|
||||
bank 7 | 4/16(25%)
|
||||
=======================
|
||||
|
||||
|
||||
5. Global Clock Usage Summary
|
||||
|
||||
-------------------------------
|
||||
Global Clock | Usage
|
||||
-------------------------------
|
||||
PRIMARY | 0/8(0%)
|
||||
LW | 0/8(0%)
|
||||
GCLK_PIN | 0/8(0%)
|
||||
PLL | 0/4(0%)
|
||||
CLKDIV | 0/8(0%)
|
||||
DLLDLY | 0/8(0%)
|
||||
===============================
|
||||
|
||||
|
||||
6. Global Clock Signals
|
||||
|
||||
-------------------------------------------
|
||||
Signal | Global Clock | Location
|
||||
-------------------------------------------
|
||||
===========================================
|
||||
|
||||
|
||||
7. Pinout by Port Name
|
||||
|
||||
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
Port Name | Diff Pair | Loc./Bank | Constraint | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | BankVccio
|
||||
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
A[0] | | A15/7 | N | in | IOL2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
A[1] | | L15/0 | N | in | IOT2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B[0] | | D16/0 | N | in | IOT4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B[1] | | B12/7 | N | in | IOL7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
C[0] | | E14/0 | N | out | IOT4[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
|
||||
C[1] | | B14/7 | N | out | IOL2[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 1.8
|
||||
C[2] | | C12/7 | N | out | IOL7[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 1.8
|
||||
C[3] | | C16/0 | N | out | IOT5[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
|
||||
==================================================================================================================================================================================================================
|
||||
|
||||
|
||||
|
||||
|
||||
8. All Package Pins
|
||||
|
||||
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
Loc./Bank| Signal | Dir. | Site | IO Type | Drive | Pull Mode | PCI Clamp | Hysteresis | Open Drain | Vref | Single Resistor | Diff Resistor | Bank Vccio
|
||||
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
L15/0 | A[1] | in | IOT2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D16/0 | B[0] | in | IOT4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E14/0 | C[0] | out | IOT4[B] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
|
||||
C16/0 | C[3] | out | IOT5[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
|
||||
D15/0 | - | in | IOT5[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E16/0 | - | in | IOT6[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F15/0 | - | in | IOT6[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F13/0 | - | in | IOT8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G12/0 | - | in | IOT8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F14/0 | - | in | IOT9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F16/0 | - | in | IOT9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F12/0 | - | in | IOT12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G13/0 | - | in | IOT12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G15/0 | - | in | IOT13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G14/0 | - | in | IOT13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G11/0 | - | in | IOT14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H12/0 | - | in | IOT14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G16/0 | - | in | IOT16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H15/0 | - | in | IOT16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H13/0 | - | in | IOT18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J12/0 | - | in | IOT18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H14/0 | - | in | IOT20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H16/0 | - | in | IOT20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J16/0 | - | in | IOT22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J14/0 | - | in | IOT22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J15/0 | - | in | IOT24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K16/0 | - | in | IOT24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H11/0 | - | in | IOT27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J13/0 | - | in | IOT27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K14/1 | - | in | IOT30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K15/1 | - | in | IOT30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J11/1 | - | in | IOT32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L12/1 | - | in | IOT32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L16/1 | - | in | IOT34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L14/1 | - | in | IOT34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K13/1 | - | in | IOT36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K12/1 | - | in | IOT36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K11/1 | - | in | IOT38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L13/1 | - | in | IOT38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M14/1 | - | in | IOT40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M15/1 | - | in | IOT40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D14/1 | - | in | IOT44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E15/1 | - | in | IOT44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N15/1 | - | in | IOT48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P16/1 | - | in | IOT48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N16/1 | - | in | IOT52[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N14/1 | - | in | IOT52[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P15/1 | - | in | IOT54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R16/1 | - | in | IOT54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
A4/5 | - | in | IOB2[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C5/5 | - | in | IOB2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D6/5 | - | in | IOB3[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E7/5 | - | in | IOB3[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A3/5 | - | in | IOB4[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B4/5 | - | in | IOB4[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A5/5 | - | in | IOB7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B6/5 | - | in | IOB7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B1/5 | - | in | IOB8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C2/5 | - | in | IOB8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D3/5 | - | in | IOB9[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D1/5 | - | in | IOB9[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E2/5 | - | in | IOB12[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E3/5 | - | in | IOB12[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B3/5 | - | in | IOB13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A2/5 | - | in | IOB13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C1/5 | - | in | IOB14[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D2/5 | - | in | IOB14[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E1/5 | - | in | IOB16[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F2/5 | - | in | IOB16[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F4/5 | - | in | IOB18[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G6/5 | - | in | IOB18[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F3/5 | - | in | IOB19[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F1/5 | - | in | IOB19[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G5/5 | - | in | IOB20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G4/5 | - | in | IOB20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G2/5 | - | in | IOB21[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G3/5 | - | in | IOB21[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F5/5 | - | in | IOB22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H6/5 | - | in | IOB22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
G1/5 | - | in | IOB24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H2/5 | - | in | IOB24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H4/5 | - | in | IOB26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J6/5 | - | in | IOB26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J1/5 | - | in | IOB27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J3/5 | - | in | IOB27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L2/4 | - | in | IOB30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M1/4 | - | in | IOB30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H3/4 | - | in | IOB32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H1/4 | - | in | IOB32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J2/4 | - | in | IOB34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K1/4 | - | in | IOB34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
H5/4 | - | in | IOB35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J4/4 | - | in | IOB35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K3/4 | - | in | IOB36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K2/4 | - | in | IOB36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
J5/4 | - | in | IOB37[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K6/4 | - | in | IOB37[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L1/4 | - | in | IOB38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L3/4 | - | in | IOB38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K4/4 | - | in | IOB39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L5/4 | - | in | IOB39[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
K5/4 | - | in | IOB40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L4/4 | - | in | IOB40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N2/4 | - | in | IOB41[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P1/4 | - | in | IOB41[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M3/4 | - | in | IOB42[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N1/4 | - | in | IOB42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M2/4 | - | in | IOB43[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N3/4 | - | in | IOB43[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R1/4 | - | in | IOB44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P2/4 | - | in | IOB44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P4/4 | - | in | IOB45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T4/4 | - | in | IOB45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R3/4 | - | in | IOB48[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T2/4 | - | in | IOB48[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P5/4 | - | in | IOB50[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R5/4 | - | in | IOB50[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R4/4 | - | in | IOB52[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T3/4 | - | in | IOB52[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R6/4 | - | in | IOB54[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T5/4 | - | in | IOB54[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
B14/7 | C[1] | out | IOL2[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 1.8
|
||||
A15/7 | A[0] | in | IOL2[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
C12/7 | C[2] | out | IOL7[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | OFF | NA | 1.8
|
||||
B12/7 | B[1] | in | IOL7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | OFF | NA | 1.8
|
||||
B13/7 | - | in | IOL8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A14/7 | - | in | IOL8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F10/7 | - | in | IOL11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B11/7 | - | in | IOL13[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A12/7 | - | in | IOL13[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A11/7 | - | in | IOL15[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C11/7 | - | in | IOL15[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D10/7 | - | in | IOL17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E10/7 | - | in | IOL17[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D11/7 | - | in | IOL22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A9/7 | - | in | IOL27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C9/7 | - | in | IOL27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C8/6 | - | in | IOL29[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A8/6 | - | in | IOL29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F9/6 | - | in | IOL31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E11/6 | - | in | IOL31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B9/6 | - | in | IOL33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A10/6 | - | in | IOL33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F8/6 | - | in | IOL35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D9/6 | - | in | IOL35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D8/6 | - | in | IOL38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E9/6 | - | in | IOL38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B7/6 | - | in | IOL40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C7/6 | - | in | IOL40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
F7/6 | - | in | IOL45[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E8/6 | - | in | IOL45[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C4/6 | - | in | IOL47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B5/6 | - | in | IOL47[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
E6/6 | - | in | IOL53[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
D7/6 | - | in | IOL53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
T15/2 | - | in | IOR7[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R14/2 | - | in | IOR7[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P12/2 | - | in | IOR8[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T13/2 | - | in | IOR8[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R12/2 | - | in | IOR11[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P13/2 | - | in | IOR11[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R11/2 | - | in | IOR17[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T12/2 | - | in | IOR17[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R13/2 | - | in | IOR20[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T14/2 | - | in | IOR20[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M10/2 | - | in | IOR22[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N11/2 | - | in | IOR22[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T11/2 | - | in | IOR24[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P11/2 | - | in | IOR24[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C6/2 | - | out | IOR25[A] | LVCMOS18 | 8 | UP | NA | NA | OFF | NA | NA | NA | 1.8
|
||||
B8/2 | - | in | IOR25[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A7/2 | - | in | IOR26[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A6/2 | - | in | IOR26[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N10/2 | - | in | IOR27[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M11/2 | - | in | IOR27[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T7/3 | - | in | IOR29[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R8/3 | - | in | IOR29[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M16/3 | - | in | IOR30[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B16/3 | - | in | IOR30[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C15/3 | - | in | IOR31[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
B10/3 | - | in | IOR31[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
A13/3 | - | in | IOR32[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C13/3 | - | in | IOR32[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P10/3 | - | in | IOR33[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R10/3 | - | in | IOR33[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M9/3 | - | in | IOR34[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L10/3 | - | in | IOR34[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R9/3 | - | in | IOR35[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T10/3 | - | in | IOR35[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M8/3 | - | in | IOR36[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N9/3 | - | in | IOR36[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T9/3 | - | in | IOR38[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P9/3 | - | in | IOR38[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
C10/3 | - | in | IOR39[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N8/3 | - | in | IOR40[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L9/3 | - | in | IOR40[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P8/3 | - | in | IOR42[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T8/3 | - | in | IOR42[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M6/3 | - | in | IOR44[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
L8/3 | - | in | IOR44[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
M7/3 | - | in | IOR47[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N7/3 | - | in | IOR47[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
R7/3 | - | in | IOR49[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P7/3 | - | in | IOR49[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
N6/3 | - | in | IOR51[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
P6/3 | - | in | IOR53[A] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
T6/3 | - | in | IOR53[B] | LVCMOS18 | NA | UP | ON | NONE | NA | NA | NA | NA | 1.8
|
||||
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
|
||||
====================================================================================================================================================================================
|
||||
|
||||
|
||||
@ -1,10 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>Timing Analysis Report</title>
|
||||
</head>
|
||||
<frameset cols="20%, 80%">
|
||||
<frame src="lab3_tr_cata.html" name="cataFrame" />
|
||||
<frame src="lab3_tr_content.html" name="mainFrame"/>
|
||||
</frameset>
|
||||
</html>
|
||||
@ -1,132 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>Timing Report Navigation</title>
|
||||
<style type="text/css">
|
||||
@import url(../temp/style.css);
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
|
||||
div#catalog_wrapper { width: 100%; }
|
||||
div#catalog ul { list-style: none; margin-left: -15px; }
|
||||
div#catalog ul li { margin: 3px 0 3px 0; text-align: left; color: #0084ff; white-space: nowrap; word-break: keep-all; }
|
||||
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 4px; margin: 0 0 0 0; }
|
||||
div#catalog a:visited { color: #0084ff; }
|
||||
div#catalog a:hover { color: #fff; background: #0084ff; }
|
||||
div.triangle_fake, div.triangle { display: inline-block; cursor: pointer; width: 8px; height: 0; border-top: 5px solid transparent; border-bottom: 5px solid transparent; }
|
||||
div.triangle_fake { border-left: 5px solid transparent; }
|
||||
div.triangle { border-left: 5px solid #0084ff; }
|
||||
div.triangle:hover { border-left-color: #000; }
|
||||
</style>
|
||||
<script>
|
||||
function onClick(obj){var childs=obj.parentNode.childNodes;for(var i=0;i<childs.length;i++){if(childs[i].tagName=="UL"){if(childs[i].style.display=="none"){childs[i].style.display="block"}else{childs[i].style.display="none"}}}};
|
||||
</script>
|
||||
</head>
|
||||
<body>
|
||||
<div id="catalog_wrapper">
|
||||
<div id="catalog">
|
||||
<ul>
|
||||
<!-- messages begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Message" target="mainFrame" style=" font-size: 16px;">Timing Messages</a></li>
|
||||
<!-- messages end-->
|
||||
<!-- summaries begin-->
|
||||
<li><div class="triangle" onclick="onClick(this)"></div><a href="lab3_tr_content.html#Summary" style=" font-size: 16px;" target="mainFrame">Timing Summaries</a>
|
||||
<ul>
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#STA_Tool_Run_Summary" style=" font-size: 14px;" target="mainFrame">STA Tool Run Summary</a></li>
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Clock_Report" style=" font-size: 14px;" target="mainFrame">Clock Summary</a></li>
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Max_Frequency_Report" style=" font-size: 14px;" target="mainFrame">Max Frequency Summary</a></li>
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Total_Negative_Slack_Report" style=" font-size: 14px;" target="mainFrame">Total Negative Slack Summary</a></li>
|
||||
</ul>
|
||||
</li>
|
||||
<!-- summaries end-->
|
||||
<!-- details begin-->
|
||||
<li><div class="triangle" onclick="onClick(this)"></div><a href="lab3_tr_content.html#Detail" style=" font-size: 16px;" target="mainFrame">Timing Details</a>
|
||||
<ul>
|
||||
<!--All_Path_Slack_Table begin-->
|
||||
<li><div class="triangle" onclick="onClick(this)"></div><a href="lab3_tr_content.html#All_Path_Slack_Table" style=" font-size: 14px;" target="mainFrame">Path Slacks Table</a>
|
||||
<ul>
|
||||
<!--Setup_Slack_Table begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Setup_Slack_Table" style=" font-size: 13px;" target="mainFrame">Setup Paths Table</a>
|
||||
</li>
|
||||
<!--Setup_Slack_Table end-->
|
||||
<!--Hold_Slack_Table begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Hold_Slack_Table" style=" font-size: 13px;" target="mainFrame">Hold Paths Table</a>
|
||||
</li>
|
||||
<!--Hold_Slack_Table end-->
|
||||
<!--Recovery_Slack_Table begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Recovery_Slack_Table" style=" font-size: 13px;" target="mainFrame">Recovery Paths Table</a>
|
||||
</li>
|
||||
<!--Recovery_Slack_Table end-->
|
||||
<!--Removal_Slack_Table begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Removal_Slack_Table" style=" font-size: 13px;" target="mainFrame">Removal Paths Table</a>
|
||||
</li>
|
||||
<!--Removal_Slack_Table end-->
|
||||
</ul>
|
||||
</li><!--All_Path_Slack_Table end-->
|
||||
<!--MIN_PULSE_WIDTH_TABLE begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#MIN_PULSE_WIDTH_TABLE" style=" font-size: 14px;" target="mainFrame">Minimum Pulse Width Table</a>
|
||||
</li>
|
||||
<!--MIN_PULSE_WIDTH_TABLE end-->
|
||||
<!--Timing_Report_by_Analysis_Type begin-->
|
||||
<li><div class="triangle" onclick="onClick(this)"></div><a href="lab3_tr_content.html#Timing_Report_by_Analysis_Type" style=" font-size: 14px;" target="mainFrame">Timing Report By Analysis Type</a>
|
||||
<ul>
|
||||
<!--Setup_Analysis begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Setup_Analysis" style=" font-size: 13px;" target="mainFrame">Setup Analysis Report</a>
|
||||
</li>
|
||||
<!--Setup_Analysis end-->
|
||||
<!--Hold_Analysis begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Hold_Analysis" style=" font-size: 13px;" target="mainFrame">Hold Analysis Report</a>
|
||||
</li>
|
||||
<!--Hold_Analysis end-->
|
||||
<!--Recovery_Analysis begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Recovery_Analysis" style=" font-size: 13px;" target="mainFrame">Recovery Analysis Report</a>
|
||||
</li>
|
||||
<!--Recovery_Analysis end-->
|
||||
<!--Removal_Analysis begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Removal_Analysis" style=" font-size: 13px;" target="mainFrame">Removal Analysis Report</a>
|
||||
</li>
|
||||
<!--Removal_Analysis end-->
|
||||
</ul>
|
||||
</li>
|
||||
<!--Timing_Report_by_Analysis_Type end-->
|
||||
<!--Minimum_Pulse_Width_Report begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Minimum_Pulse_Width_Report" style=" font-size: 14px;" target="mainFrame">Minimum Pulse Width Report</a>
|
||||
</li>
|
||||
<!--Minimum_Pulse_Width_Report end-->
|
||||
<!--High_Fanout_Nets_Report begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#High_Fanout_Nets_Report" style=" font-size: 14px;" target="mainFrame">High Fanout Nets Report</a></li>
|
||||
<!--High_Fanout_Nets_Report end-->
|
||||
<!--Route_Congestions_Report begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Route_Congestions_Report" style=" font-size: 14px;" target="mainFrame">Route Congestions Report</a></li>
|
||||
<!--Route_Congestions_Report end-->
|
||||
<!--Timing_Exceptions_Report begin-->
|
||||
<li><div class="triangle" onclick="onClick(this)"></div><a href="lab3_tr_content.html#Timing_Exceptions_Report" style=" font-size: 14px;" target="mainFrame">Timing Exceptions Report</a>
|
||||
<ul>
|
||||
<!--Setup_Analysis_Exceptions begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Setup_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Setup Analysis Report</a>
|
||||
</li>
|
||||
<!--Setup_Analysis_Exceptions end-->
|
||||
<!--Hold_Analysis_Exceptions begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Hold_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Hold Analysis Report</a>
|
||||
</li>
|
||||
<!--Hold_Analysis_Exceptions end-->
|
||||
<!--Recovery_Analysis_Exceptions begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#Recovery_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Recovery Analysis Report</a>
|
||||
</li>
|
||||
<!--Recovery_Analysis_Exceptions end-->
|
||||
<!--Removal_Analysis_Exceptions begin-->
|
||||
<li><div class="triangle_fake" onclick="onClick(this)"></div><a href="lab3_tr_content.html#Removal_Analysis_Exceptions" style=" font-size: 13px;" target="mainFrame">Removal Analysis Report</a>
|
||||
</li>
|
||||
<!--Removal_Analysis_Exceptions end-->
|
||||
</ul>
|
||||
</li>
|
||||
<!--Timing_Exceptions_Report end-->
|
||||
<!--SDC_Report begin-->
|
||||
<li><div class="triangle_fake"></div><a href="lab3_tr_content.html#SDC_Report" style=" font-size: 14px;" target="mainFrame">Timing Constraints Report</a></li>
|
||||
<!--SDC_Report end-->
|
||||
</ul>
|
||||
</li>
|
||||
<!-- details end-->
|
||||
</ul>
|
||||
</div><!-- catalog -->
|
||||
</div><!-- catalog_wrapper -->
|
||||
</body>
|
||||
</html>
|
||||
@ -1,249 +0,0 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>Timing Analysis Report</title>
|
||||
<style type="text/css">
|
||||
@import url(../temp/style.css);
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
|
||||
div#content { width: 100%; margin: }
|
||||
hr { margin-top: 30px; margin-bottom: 30px; }
|
||||
h1, h3 { text-align: center; }
|
||||
h1 {margin-top: 50px; }
|
||||
table, th, td {white-space:pre; border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { padding: 5px 5px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
|
||||
table.detail_table th.label { min-width: 8%; width: 8%; }
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="content">
|
||||
<h1><a name="Message">Timing Messages</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Report Title</td>
|
||||
<td>Timing Analysis Report</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Design File</td>
|
||||
<td>C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Physical Constraints File</td>
|
||||
<td>---</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Timing Constraint File</td>
|
||||
<td>---</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Tool Version</td>
|
||||
<td>V1.9.9.02</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Part Number</td>
|
||||
<td>GW2A-LV18PG256C8/I7</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device</td>
|
||||
<td>GW2A-18</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device Version</td>
|
||||
<td>C</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Created Time</td>
|
||||
<td>Sat May 4 01:07:45 2024
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Legal Announcement</td>
|
||||
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="Summary">Timing Summaries</a></h1>
|
||||
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Setup Delay Model</td>
|
||||
<td>Slow 0.95V 85C C8/I7</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Hold Delay Model</td>
|
||||
<td>Fast 1.05V 0C C8/I7</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Numbers of Paths Analyzed</td>
|
||||
<td>14</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Numbers of Endpoints Analyzed</td>
|
||||
<td>4</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Numbers of Falling Endpoints</td>
|
||||
<td>0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Numbers of Setup Violated Endpoints</td>
|
||||
<td>0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Numbers of Hold Violated Endpoints</td>
|
||||
<td>0</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="Clock_Report">Clock Summary:</a></h2>
|
||||
<table class="detail_table">
|
||||
<tr>
|
||||
<th class="label">Clock Name</th>
|
||||
<th class="label">Type</th>
|
||||
<th class="label">Period</th>
|
||||
<th class="label">Frequency(MHz)</th>
|
||||
<th class="label">Rise</th>
|
||||
<th class="label">Fall</th>
|
||||
<th class="label">Source</th>
|
||||
<th class="label">Master</th>
|
||||
<th class="label">Objects</th>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
|
||||
<table>
|
||||
<tr>
|
||||
<th>NO.</th>
|
||||
<th>Clock Name</th>
|
||||
<th>Constraint</th>
|
||||
<th>Actual Fmax</th>
|
||||
<th>Logic Level</th>
|
||||
<th>Entity</th>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
|
||||
<table class="detail_table">
|
||||
<tr>
|
||||
<th class="label">Clock Name</th>
|
||||
<th class="label">Analysis Type</th>
|
||||
<th class="label">Endpoints TNS</th>
|
||||
<th class="label">Number of Endpoints</th>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="Detail">Timing Details</a></h1>
|
||||
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
|
||||
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
|
||||
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
|
||||
<h4>Nothing to report!</h4>
|
||||
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
|
||||
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
|
||||
<h4>Nothing to report!</h4>
|
||||
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
|
||||
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
|
||||
<h4>Nothing to report!</h4>
|
||||
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
|
||||
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
|
||||
<h4>Nothing to report!</h4>
|
||||
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
|
||||
<table class="detail_table">
|
||||
<tr>
|
||||
<th class="label">Number</th>
|
||||
<th class="label">Slack</th>
|
||||
<th class="label">Actual Width</th>
|
||||
<th class="label">Required Width</th>
|
||||
<th class="label">Type</th>
|
||||
<th class="label">Clock</th>
|
||||
<th class="label">Objects</th>
|
||||
</tr>
|
||||
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
|
||||
<h4>Nothing to report!</h4>
|
||||
</table>
|
||||
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
|
||||
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
|
||||
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
|
||||
<h4>No setup paths to report!</h4>
|
||||
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
|
||||
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
|
||||
<h4>No hold paths to report!</h4>
|
||||
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
|
||||
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
|
||||
<h4>No recovery paths to report!</h4>
|
||||
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
|
||||
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
|
||||
<h4>No removal paths to report!</h4>
|
||||
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
|
||||
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
|
||||
<h4>Nothing to report!</h4>
|
||||
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
|
||||
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
|
||||
<table class="detail_table">
|
||||
<tr>
|
||||
<th class="label">FANOUT</th>
|
||||
<th class="label">NET NAME</th>
|
||||
<th class="label">WORST SLACK</th>
|
||||
<th class="label">MAX DELAY</th>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
|
||||
<h4>Report Command:report_route_congestion -max_grids 10</h4>
|
||||
<table class="detail_table">
|
||||
<tr>
|
||||
<th class="label">GRID LOC</th>
|
||||
<th class="label">ROUTE CONGESTIONS</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R2C2</td>
|
||||
<td>8.33%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R2C1</td>
|
||||
<td>5.56%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R1C2</td>
|
||||
<td>2.78%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R2C4</td>
|
||||
<td>2.78%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R7C1</td>
|
||||
<td>2.78%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R1C4</td>
|
||||
<td>2.78%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R28C51</td>
|
||||
<td>1.39%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>R2C3</td>
|
||||
<td>1.39%</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
|
||||
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
|
||||
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
|
||||
<h4>No timing exceptions to report!</h4>
|
||||
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
|
||||
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
|
||||
<h4>No timing exceptions to report!</h4>
|
||||
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
|
||||
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
|
||||
<h4>No timing exceptions to report!</h4>
|
||||
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
|
||||
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
|
||||
<h4>No timing exceptions to report!</h4>
|
||||
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
|
||||
<table class="detail_table">
|
||||
<tr>
|
||||
<th class="label">SDC Command Type</th>
|
||||
<th class="label">State</th>
|
||||
<th class="label">Detail Command</th>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</body>
|
||||
</html>
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user