subtraction & multiplier
This commit is contained in:
1451
project0.2/ALU
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1451
project0.2/ALU
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File diff suppressed because it is too large
Load Diff
57
project0.2/ALU.v
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57
project0.2/ALU.v
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@@ -0,0 +1,57 @@
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module ALU (
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input [3:0] A, B,
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input CarryIN,
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input [2:0] opCodeA,
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output [3:0] Y,
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output CarryOUT, overflow
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);
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// Supports: ADD[0], SUB[1], AND[4], OR[5], XOR[6]
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wire [7:0] opCode8;
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wire [3:0] add_Y, sub_Y;
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wire [3:0] resultA, resultO, resultX, lUOutput1;
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wire [3:0] aUtemp1, aUtemp2, lUOutput2;
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wire [3:0] wireY;
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opCode opCd (.A(opCodeA), .opCode(opCode8));
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arithmeticUnit aU(.opCode(opCode8[1:0]), .A(A), .B(B), .CarryIN(CarryIN), .add_Y(add_Y), .sub_Y(sub_Y), .CarryOUT(CarryOUT), .overflow(overflow));
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logicUnit lU (.opCode(opCode8[6:4]), .A(A), .B(B), .resultA(resultA), .resultO(resultO), .resultX(resultX));
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or o01 (lUOutput1[0], resultA[0], resultO[0]);
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or o02 (lUOutput1[1], resultA[1], resultO[1]);
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or o03 (lUOutput1[2], resultA[2], resultO[2]);
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or o04 (lUOutput1[3], resultA[3], resultO[3]);
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or o11 (lUOutput2[0], lUOutput1[0], resultX[0]);
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or o12 (lUOutput2[1], lUOutput1[1], resultX[1]);
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or o13 (lUOutput2[2], lUOutput1[2], resultX[2]);
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or o14 (lUOutput2[3], lUOutput1[3], resultX[3]);
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and a01 (aUtemp1[0], opCode8[0], add_Y[0]);
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and a02 (aUtemp1[1], opCode8[0], add_Y[1]);
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and a03 (aUtemp1[2], opCode8[0], add_Y[2]);
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and a04 (aUtemp1[3], opCode8[0], add_Y[3]);
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and a11 (aUtemp2[0], opCode8[1], sub_Y[0]);
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and a12 (aUtemp2[1], opCode8[1], sub_Y[1]);
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and a13 (aUtemp2[2], opCode8[1], sub_Y[2]);
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and a14 (aUtemp2[3], opCode8[1], sub_Y[3]);
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or o21 (wireY[0], aUtemp1[0], aUtemp2[0]);
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or o22 (wireY[1], aUtemp1[1], aUtemp2[1]);
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or o23 (wireY[2], aUtemp1[2], aUtemp2[2]);
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or o24 (wireY[3], aUtemp1[3], aUtemp2[3]);
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or o1 (Y[0], lUOutput2[0], wireY[0]);
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or o2 (Y[1], lUOutput2[1], wireY[1]);
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or o3 (Y[2], lUOutput2[2], wireY[2]);
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or o4 (Y[3], lUOutput2[3], wireY[3]);
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endmodule
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1656
project0.2/ALU.vcd
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1656
project0.2/ALU.vcd
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File diff suppressed because it is too large
Load Diff
36
project0.2/ALUTB.v
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36
project0.2/ALUTB.v
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@@ -0,0 +1,36 @@
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module ALUTB ();
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reg [3:0] A, B;
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reg CarryIN;
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reg [2:0] opCodeA;
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wire [3:0] Y;
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wire CarryOUT, overflow;
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ALU uut(
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.A(A),
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.B(B),
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.CarryIN(CarryIN),
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.opCodeA(opCodeA),
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.Y(Y),
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.CarryOUT(CarryOUT),
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.overflow(overflow)
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);
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initial begin
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$dumpfile("ALU.vcd"); // GTKWAVE SIMULTAIN DATA WAVEFORM
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$dumpvars; // ICARUS VERILOG ADD ALL VARIABLES
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A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b000; #5;
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A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 3'b000; #5;
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A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b000; #5;
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A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b000; #5;
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A = 4'b0111; B = 4'b0111; CarryIN = 1'b1; opCodeA = 3'b000; #5;
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A = 4'b0000; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b001; #5;
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A = 4'b0000; B = 4'b1111; CarryIN = 1'b0; opCodeA = 3'b001; #5;
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A = 4'b1111; B = 4'b0000; CarryIN = 1'b0; opCodeA = 3'b001; #5;
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A = 4'b1111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b001; #5;
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A = 4'b0111; B = 4'b1111; CarryIN = 1'b1; opCodeA = 3'b001; #5;
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$finish; //NOT CONTAIN CLK, BUT STILL STOPS CODE
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end
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endmodule
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20
project0.2/addition.v
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20
project0.2/addition.v
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@@ -0,0 +1,20 @@
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module addition (
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input [3:0] A, B,
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input CarryIN,
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output [3:0] Y,
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output CarryOUT,
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output overflow
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);
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wire [2:0] Carry4;
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fulladder f0(.A(A[0]), .B(B[0]), .Carry(CarryIN), .Sum(Y[0]), .CarryO(Carry4[0]));
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fulladder f1(.A(A[1]), .B(B[1]), .Carry(Carry4[0]), .Sum(Y[1]), .CarryO(Carry4[1]));
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fulladder f2(.A(A[2]), .B(B[2]), .Carry(Carry4[1]), .Sum(Y[2]), .CarryO(Carry4[2]));
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fulladder f3(.A(A[3]), .B(B[3]), .Carry(Carry4[2]), .Sum(Y[3]), .CarryO(CarryOUT));
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overflowDetect od1 (.opCode(2'b01), .A(A), .B(B), .Y(Y), .CarryOUT(CarryOUT), .overflowDetect(overflow));
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endmodule
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29
project0.2/arithmeticUnit.v
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29
project0.2/arithmeticUnit.v
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@@ -0,0 +1,29 @@
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module arithmeticUnit (
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input [1:0] opCode,
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input [3:0] A, B,
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input CarryIN,
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output [3:0] add_Y, sub_Y,
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output CarryOUT,
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output overflow
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);
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wire [3:0] addY, subY;
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wire overflowSUB, overflowADD, CarryOUTADD, CarryOUTSUB;
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addition a1(.A(A), .B(B), .CarryIN(CarryIN), .Y(addY), .CarryOUT(CarryOUTADD), .overflow(overflowADD));
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subtraction s1(.A(A), .B(B), .CarryIN(CarryIN), .Y(subY), .CarryOUT(CarryOUTSUB), .overflow(overflowSUB));
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and add1 (add_Y[0], opCode[0], addY[0]);
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and add2 (add_Y[1], opCode[0], addY[1]);
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and add3 (add_Y[2], opCode[0], addY[2]);
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and add4 (add_Y[3], opCode[0], addY[3]);
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and sub1 (sub_Y[0], opCode[1], subY[0]);
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and sub2 (sub_Y[1], opCode[1], subY[1]);
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and sub3 (sub_Y[2], opCode[1], subY[2]);
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and sub4 (sub_Y[3], opCode[1], subY[3]);
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or or1 (CarryOUT, CarryOUTADD, CarryOUTSUB);
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or or2 (overflow, overflowADD, overflowSUB);
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endmodule
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12
project0.2/fulladder.v
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12
project0.2/fulladder.v
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@@ -0,0 +1,12 @@
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module fulladder (
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input A, B, Carry,
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output Sum, CarryO
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);
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wire xor1, and1, and2;
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halfadder h1(.A(A), .B(B), .Sum(xor1), .Carry(and1));
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halfadder h2 (.A(xor1), .B(Carry), .Sum(Sum), .Carry(and2));
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or o1 (CarryO, and1, and2);
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endmodule
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12
project0.2/fullsubtraction.v
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12
project0.2/fullsubtraction.v
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@@ -0,0 +1,12 @@
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module fullsubtraction (
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input A, B, BorrowIN,
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output Difference, BorrowOut
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);
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wire tempD, tempB1, tempB2;
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halfsubtraction hf1(.A(A), .B(B), .Difference(tempD), .Borrow(tempB1));
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halfsubtraction hf2(.A(tempD), .B(BorrowIN), .Difference(Difference), .Borrow(tempB2));
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or o1 (BorrowOut, tempB1, tempB2);
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endmodule
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9
project0.2/halfadder.v
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9
project0.2/halfadder.v
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@@ -0,0 +1,9 @@
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module halfadder (
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input A, B,
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output Sum, Carry
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);
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and a1 (Carry, A, B);
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xor xo1 (Sum, A, B);
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endmodule
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12
project0.2/halfsubtraction.v
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12
project0.2/halfsubtraction.v
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@@ -0,0 +1,12 @@
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module halfsubtraction (
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input A, B,
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output Difference, Borrow
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);
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wire notA;
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xor xo1 (Difference, A, B);
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not a1 (notA, A);
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and an1 (Borrow, notA, B);
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endmodule
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288
project0.2/logicUnit
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288
project0.2/logicUnit
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@@ -0,0 +1,288 @@
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#! /usr/bin/vvp
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:ivl_version "11.0 (stable)";
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:ivl_delay_selection "TYPICAL";
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:vpi_time_precision + 0;
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
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S_0x56004b80baa0 .scope module, "logicUnitTB" "logicUnitTB" 2 1;
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.timescale 0 0;
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v0x56004b83a150_0 .var "A", 3 0;
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v0x56004b83a230_0 .var "B", 3 0;
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v0x56004b83a300_0 .var "opCode", 2 0;
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v0x56004b83a400_0 .net "resultA", 3 0, L_0x56004b83d920; 1 drivers
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v0x56004b83a4d0_0 .net "resultO", 3 0, L_0x56004b83ec00; 1 drivers
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v0x56004b83a570_0 .net "resultX", 3 0, L_0x56004b83fe60; 1 drivers
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S_0x56004b80bc30 .scope module, "uut" "logicUnit" 2 7, 3 1 0, S_0x56004b80baa0;
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.timescale 0 0;
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.port_info 0 /INPUT 3 "opCode";
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.port_info 1 /INPUT 4 "A";
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.port_info 2 /INPUT 4 "B";
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.port_info 3 /OUTPUT 4 "resultA";
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.port_info 4 /OUTPUT 4 "resultO";
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.port_info 5 /OUTPUT 4 "resultX";
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L_0x56004b83a640 .functor AND 1, L_0x56004b83a740, L_0x56004b83a880, C4<1>, C4<1>;
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L_0x56004b83a9c0 .functor AND 1, L_0x56004b83aa30, L_0x56004b83ab20, C4<1>, C4<1>;
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L_0x56004b83ac40 .functor AND 1, L_0x56004b83acb0, L_0x56004b83ada0, C4<1>, C4<1>;
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L_0x56004b83afc0 .functor AND 1, L_0x56004b83b0b0, L_0x56004b83b1f0, C4<1>, C4<1>;
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L_0x56004b83b2e0 .functor OR 1, L_0x56004b83b350, L_0x56004b83b4a0, C4<0>, C4<0>;
|
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L_0x56004b83b540 .functor OR 1, L_0x56004b83b5f0, L_0x56004b83b750, C4<0>, C4<0>;
|
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L_0x56004b83b840 .functor OR 1, L_0x56004b83b8b0, L_0x56004b83ba20, C4<0>, C4<0>;
|
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L_0x56004b83b6e0 .functor OR 1, L_0x56004b83bdd0, L_0x56004b83bec0, C4<0>, C4<0>;
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L_0x56004b83c050 .functor XOR 1, L_0x56004b83c0c0, L_0x56004b83c1b0, C4<0>, C4<0>;
|
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L_0x56004b83c350 .functor XOR 1, L_0x56004b83bfb0, L_0x56004b83c450, C4<0>, C4<0>;
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L_0x56004b83c600 .functor XOR 1, L_0x56004b83c6a0, L_0x56004b83c790, C4<0>, C4<0>;
|
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L_0x56004b83cae0 .functor XOR 1, L_0x56004b83cc10, L_0x56004b83cde0, C4<0>, C4<0>;
|
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L_0x56004b83ced0 .functor AND 1, L_0x56004b83cf40, L_0x56004b83d170, C4<1>, C4<1>;
|
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L_0x56004b83d2b0 .functor AND 1, L_0x56004b83d3a0, L_0x56004b83d590, C4<1>, C4<1>;
|
||||
L_0x56004b83cba0 .functor AND 1, L_0x56004b83d680, L_0x56004b83d880, C4<1>, C4<1>;
|
||||
L_0x56004b83dbd0 .functor AND 1, L_0x56004b83dd20, L_0x56004b83de10, C4<1>, C4<1>;
|
||||
L_0x56004b83e030 .functor AND 1, L_0x56004b83e0a0, L_0x56004b83e190, C4<1>, C4<1>;
|
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L_0x56004b83e410 .functor AND 1, L_0x56004b83e520, L_0x56004b83e610, C4<1>, C4<1>;
|
||||
L_0x56004b83e850 .functor AND 1, L_0x56004b83e8c0, L_0x56004b83e9b0, C4<1>, C4<1>;
|
||||
L_0x56004b83ed90 .functor AND 1, L_0x56004b83e480, L_0x56004b83f0c0, C4<1>, C4<1>;
|
||||
L_0x56004b83f1b0 .functor AND 1, L_0x56004b83f220, L_0x56004b83f490, C4<1>, C4<1>;
|
||||
L_0x56004b83f5d0 .functor AND 1, L_0x56004b83f700, L_0x56004b83f980, C4<1>, C4<1>;
|
||||
L_0x56004b83fa70 .functor AND 1, L_0x56004b83fae0, L_0x56004b83fd70, C4<1>, C4<1>;
|
||||
L_0x56004b8401a0 .functor AND 1, L_0x56004b840330, L_0x56004b840420, C4<1>, C4<1>;
|
||||
v0x56004b7c9cf0_0 .net "A", 3 0, v0x56004b83a150_0; 1 drivers
|
||||
v0x56004b835650_0 .net "B", 3 0, v0x56004b83a230_0; 1 drivers
|
||||
v0x56004b835730_0 .net *"_ivl_0", 0 0, L_0x56004b83a640; 1 drivers
|
||||
v0x56004b8357f0_0 .net *"_ivl_100", 0 0, L_0x56004b83e030; 1 drivers
|
||||
v0x56004b8358d0_0 .net *"_ivl_103", 0 0, L_0x56004b83e0a0; 1 drivers
|
||||
v0x56004b835a00_0 .net *"_ivl_105", 0 0, L_0x56004b83e190; 1 drivers
|
||||
v0x56004b835ae0_0 .net *"_ivl_106", 0 0, L_0x56004b83e410; 1 drivers
|
||||
v0x56004b835bc0_0 .net *"_ivl_109", 0 0, L_0x56004b83e520; 1 drivers
|
||||
v0x56004b835ca0_0 .net *"_ivl_11", 0 0, L_0x56004b83ab20; 1 drivers
|
||||
v0x56004b835d80_0 .net *"_ivl_111", 0 0, L_0x56004b83e610; 1 drivers
|
||||
v0x56004b835e60_0 .net *"_ivl_112", 0 0, L_0x56004b83e850; 1 drivers
|
||||
v0x56004b835f40_0 .net *"_ivl_115", 0 0, L_0x56004b83e8c0; 1 drivers
|
||||
v0x56004b836020_0 .net *"_ivl_117", 0 0, L_0x56004b83e9b0; 1 drivers
|
||||
v0x56004b836100_0 .net *"_ivl_118", 0 0, L_0x56004b83ed90; 1 drivers
|
||||
v0x56004b8361e0_0 .net *"_ivl_12", 0 0, L_0x56004b83ac40; 1 drivers
|
||||
v0x56004b8362c0_0 .net *"_ivl_122", 0 0, L_0x56004b83e480; 1 drivers
|
||||
v0x56004b8363a0_0 .net *"_ivl_124", 0 0, L_0x56004b83f0c0; 1 drivers
|
||||
v0x56004b836480_0 .net *"_ivl_125", 0 0, L_0x56004b83f1b0; 1 drivers
|
||||
v0x56004b836560_0 .net *"_ivl_128", 0 0, L_0x56004b83f220; 1 drivers
|
||||
v0x56004b836640_0 .net *"_ivl_130", 0 0, L_0x56004b83f490; 1 drivers
|
||||
v0x56004b836720_0 .net *"_ivl_131", 0 0, L_0x56004b83f5d0; 1 drivers
|
||||
v0x56004b836800_0 .net *"_ivl_134", 0 0, L_0x56004b83f700; 1 drivers
|
||||
v0x56004b8368e0_0 .net *"_ivl_136", 0 0, L_0x56004b83f980; 1 drivers
|
||||
v0x56004b8369c0_0 .net *"_ivl_137", 0 0, L_0x56004b83fa70; 1 drivers
|
||||
v0x56004b836aa0_0 .net *"_ivl_140", 0 0, L_0x56004b83fae0; 1 drivers
|
||||
v0x56004b836b80_0 .net *"_ivl_142", 0 0, L_0x56004b83fd70; 1 drivers
|
||||
v0x56004b836c60_0 .net *"_ivl_143", 0 0, L_0x56004b8401a0; 1 drivers
|
||||
v0x56004b836d40_0 .net *"_ivl_147", 0 0, L_0x56004b840330; 1 drivers
|
||||
v0x56004b836e20_0 .net *"_ivl_149", 0 0, L_0x56004b840420; 1 drivers
|
||||
v0x56004b836f00_0 .net *"_ivl_15", 0 0, L_0x56004b83acb0; 1 drivers
|
||||
v0x56004b836fe0_0 .net *"_ivl_17", 0 0, L_0x56004b83ada0; 1 drivers
|
||||
v0x56004b8370c0_0 .net *"_ivl_18", 0 0, L_0x56004b83afc0; 1 drivers
|
||||
v0x56004b8371a0_0 .net *"_ivl_22", 0 0, L_0x56004b83b0b0; 1 drivers
|
||||
v0x56004b837280_0 .net *"_ivl_24", 0 0, L_0x56004b83b1f0; 1 drivers
|
||||
v0x56004b837360_0 .net *"_ivl_25", 0 0, L_0x56004b83b2e0; 1 drivers
|
||||
v0x56004b837440_0 .net *"_ivl_28", 0 0, L_0x56004b83b350; 1 drivers
|
||||
v0x56004b837520_0 .net *"_ivl_3", 0 0, L_0x56004b83a740; 1 drivers
|
||||
v0x56004b837600_0 .net *"_ivl_30", 0 0, L_0x56004b83b4a0; 1 drivers
|
||||
v0x56004b8376e0_0 .net *"_ivl_31", 0 0, L_0x56004b83b540; 1 drivers
|
||||
v0x56004b8377c0_0 .net *"_ivl_34", 0 0, L_0x56004b83b5f0; 1 drivers
|
||||
v0x56004b8378a0_0 .net *"_ivl_36", 0 0, L_0x56004b83b750; 1 drivers
|
||||
v0x56004b837980_0 .net *"_ivl_37", 0 0, L_0x56004b83b840; 1 drivers
|
||||
v0x56004b837a60_0 .net *"_ivl_40", 0 0, L_0x56004b83b8b0; 1 drivers
|
||||
v0x56004b837b40_0 .net *"_ivl_42", 0 0, L_0x56004b83ba20; 1 drivers
|
||||
v0x56004b837c20_0 .net *"_ivl_43", 0 0, L_0x56004b83b6e0; 1 drivers
|
||||
v0x56004b837d00_0 .net *"_ivl_47", 0 0, L_0x56004b83bdd0; 1 drivers
|
||||
v0x56004b837de0_0 .net *"_ivl_49", 0 0, L_0x56004b83bec0; 1 drivers
|
||||
v0x56004b837ec0_0 .net *"_ivl_5", 0 0, L_0x56004b83a880; 1 drivers
|
||||
v0x56004b837fa0_0 .net *"_ivl_50", 0 0, L_0x56004b83c050; 1 drivers
|
||||
v0x56004b838080_0 .net *"_ivl_53", 0 0, L_0x56004b83c0c0; 1 drivers
|
||||
v0x56004b838160_0 .net *"_ivl_55", 0 0, L_0x56004b83c1b0; 1 drivers
|
||||
v0x56004b838240_0 .net *"_ivl_56", 0 0, L_0x56004b83c350; 1 drivers
|
||||
v0x56004b838320_0 .net *"_ivl_59", 0 0, L_0x56004b83bfb0; 1 drivers
|
||||
v0x56004b838400_0 .net *"_ivl_6", 0 0, L_0x56004b83a9c0; 1 drivers
|
||||
v0x56004b8384e0_0 .net *"_ivl_61", 0 0, L_0x56004b83c450; 1 drivers
|
||||
v0x56004b8385c0_0 .net *"_ivl_62", 0 0, L_0x56004b83c600; 1 drivers
|
||||
v0x56004b8386a0_0 .net *"_ivl_65", 0 0, L_0x56004b83c6a0; 1 drivers
|
||||
v0x56004b838780_0 .net *"_ivl_67", 0 0, L_0x56004b83c790; 1 drivers
|
||||
v0x56004b838860_0 .net *"_ivl_68", 0 0, L_0x56004b83cae0; 1 drivers
|
||||
v0x56004b838940_0 .net *"_ivl_72", 0 0, L_0x56004b83cc10; 1 drivers
|
||||
v0x56004b838a20_0 .net *"_ivl_74", 0 0, L_0x56004b83cde0; 1 drivers
|
||||
v0x56004b838b00_0 .net *"_ivl_75", 0 0, L_0x56004b83ced0; 1 drivers
|
||||
v0x56004b838be0_0 .net *"_ivl_78", 0 0, L_0x56004b83cf40; 1 drivers
|
||||
v0x56004b838cc0_0 .net *"_ivl_80", 0 0, L_0x56004b83d170; 1 drivers
|
||||
v0x56004b838da0_0 .net *"_ivl_81", 0 0, L_0x56004b83d2b0; 1 drivers
|
||||
v0x56004b839290_0 .net *"_ivl_84", 0 0, L_0x56004b83d3a0; 1 drivers
|
||||
v0x56004b839370_0 .net *"_ivl_86", 0 0, L_0x56004b83d590; 1 drivers
|
||||
v0x56004b839450_0 .net *"_ivl_87", 0 0, L_0x56004b83cba0; 1 drivers
|
||||
v0x56004b839530_0 .net *"_ivl_9", 0 0, L_0x56004b83aa30; 1 drivers
|
||||
v0x56004b839610_0 .net *"_ivl_90", 0 0, L_0x56004b83d680; 1 drivers
|
||||
v0x56004b8396f0_0 .net *"_ivl_92", 0 0, L_0x56004b83d880; 1 drivers
|
||||
v0x56004b8397d0_0 .net *"_ivl_93", 0 0, L_0x56004b83dbd0; 1 drivers
|
||||
v0x56004b8398b0_0 .net *"_ivl_97", 0 0, L_0x56004b83dd20; 1 drivers
|
||||
v0x56004b839990_0 .net *"_ivl_99", 0 0, L_0x56004b83de10; 1 drivers
|
||||
v0x56004b839a70_0 .net "and1", 3 0, L_0x56004b83ae80; 1 drivers
|
||||
v0x56004b839b50_0 .net "opCode", 2 0, v0x56004b83a300_0; 1 drivers
|
||||
v0x56004b839c30_0 .net "or1", 3 0, L_0x56004b83bb10; 1 drivers
|
||||
v0x56004b839d10_0 .net "resultA", 3 0, L_0x56004b83d920; alias, 1 drivers
|
||||
v0x56004b839df0_0 .net "resultO", 3 0, L_0x56004b83ec00; alias, 1 drivers
|
||||
v0x56004b839ed0_0 .net "resultX", 3 0, L_0x56004b83fe60; alias, 1 drivers
|
||||
v0x56004b839fb0_0 .net "xor1", 3 0, L_0x56004b83c950; 1 drivers
|
||||
L_0x56004b83a740 .part v0x56004b83a150_0, 0, 1;
|
||||
L_0x56004b83a880 .part v0x56004b83a230_0, 0, 1;
|
||||
L_0x56004b83aa30 .part v0x56004b83a150_0, 1, 1;
|
||||
L_0x56004b83ab20 .part v0x56004b83a230_0, 1, 1;
|
||||
L_0x56004b83acb0 .part v0x56004b83a150_0, 2, 1;
|
||||
L_0x56004b83ada0 .part v0x56004b83a230_0, 2, 1;
|
||||
L_0x56004b83ae80 .concat8 [ 1 1 1 1], L_0x56004b83a640, L_0x56004b83a9c0, L_0x56004b83ac40, L_0x56004b83afc0;
|
||||
L_0x56004b83b0b0 .part v0x56004b83a150_0, 3, 1;
|
||||
L_0x56004b83b1f0 .part v0x56004b83a230_0, 3, 1;
|
||||
L_0x56004b83b350 .part v0x56004b83a150_0, 0, 1;
|
||||
L_0x56004b83b4a0 .part v0x56004b83a230_0, 0, 1;
|
||||
L_0x56004b83b5f0 .part v0x56004b83a150_0, 1, 1;
|
||||
L_0x56004b83b750 .part v0x56004b83a230_0, 1, 1;
|
||||
L_0x56004b83b8b0 .part v0x56004b83a150_0, 2, 1;
|
||||
L_0x56004b83ba20 .part v0x56004b83a230_0, 2, 1;
|
||||
L_0x56004b83bb10 .concat8 [ 1 1 1 1], L_0x56004b83b2e0, L_0x56004b83b540, L_0x56004b83b840, L_0x56004b83b6e0;
|
||||
L_0x56004b83bdd0 .part v0x56004b83a150_0, 3, 1;
|
||||
L_0x56004b83bec0 .part v0x56004b83a230_0, 3, 1;
|
||||
L_0x56004b83c0c0 .part v0x56004b83a150_0, 0, 1;
|
||||
L_0x56004b83c1b0 .part v0x56004b83a230_0, 0, 1;
|
||||
L_0x56004b83bfb0 .part v0x56004b83a150_0, 1, 1;
|
||||
L_0x56004b83c450 .part v0x56004b83a230_0, 1, 1;
|
||||
L_0x56004b83c6a0 .part v0x56004b83a150_0, 2, 1;
|
||||
L_0x56004b83c790 .part v0x56004b83a230_0, 2, 1;
|
||||
L_0x56004b83c950 .concat8 [ 1 1 1 1], L_0x56004b83c050, L_0x56004b83c350, L_0x56004b83c600, L_0x56004b83cae0;
|
||||
L_0x56004b83cc10 .part v0x56004b83a150_0, 3, 1;
|
||||
L_0x56004b83cde0 .part v0x56004b83a230_0, 3, 1;
|
||||
L_0x56004b83cf40 .part v0x56004b83a300_0, 0, 1;
|
||||
L_0x56004b83d170 .part L_0x56004b83ae80, 0, 1;
|
||||
L_0x56004b83d3a0 .part v0x56004b83a300_0, 0, 1;
|
||||
L_0x56004b83d590 .part L_0x56004b83ae80, 1, 1;
|
||||
L_0x56004b83d680 .part v0x56004b83a300_0, 0, 1;
|
||||
L_0x56004b83d880 .part L_0x56004b83ae80, 2, 1;
|
||||
L_0x56004b83d920 .concat8 [ 1 1 1 1], L_0x56004b83ced0, L_0x56004b83d2b0, L_0x56004b83cba0, L_0x56004b83dbd0;
|
||||
L_0x56004b83dd20 .part v0x56004b83a300_0, 0, 1;
|
||||
L_0x56004b83de10 .part L_0x56004b83ae80, 3, 1;
|
||||
L_0x56004b83e0a0 .part v0x56004b83a300_0, 1, 1;
|
||||
L_0x56004b83e190 .part L_0x56004b83bb10, 0, 1;
|
||||
L_0x56004b83e520 .part v0x56004b83a300_0, 1, 1;
|
||||
L_0x56004b83e610 .part L_0x56004b83bb10, 1, 1;
|
||||
L_0x56004b83e8c0 .part v0x56004b83a300_0, 1, 1;
|
||||
L_0x56004b83e9b0 .part L_0x56004b83bb10, 2, 1;
|
||||
L_0x56004b83ec00 .concat8 [ 1 1 1 1], L_0x56004b83e030, L_0x56004b83e410, L_0x56004b83e850, L_0x56004b83ed90;
|
||||
L_0x56004b83e480 .part v0x56004b83a300_0, 1, 1;
|
||||
L_0x56004b83f0c0 .part L_0x56004b83bb10, 3, 1;
|
||||
L_0x56004b83f220 .part v0x56004b83a300_0, 2, 1;
|
||||
L_0x56004b83f490 .part L_0x56004b83c950, 0, 1;
|
||||
L_0x56004b83f700 .part v0x56004b83a300_0, 2, 1;
|
||||
L_0x56004b83f980 .part L_0x56004b83c950, 1, 1;
|
||||
L_0x56004b83fae0 .part v0x56004b83a300_0, 2, 1;
|
||||
L_0x56004b83fd70 .part L_0x56004b83c950, 2, 1;
|
||||
L_0x56004b83fe60 .concat8 [ 1 1 1 1], L_0x56004b83f1b0, L_0x56004b83f5d0, L_0x56004b83fa70, L_0x56004b8401a0;
|
||||
L_0x56004b840330 .part v0x56004b83a300_0, 2, 1;
|
||||
L_0x56004b840420 .part L_0x56004b83c950, 3, 1;
|
||||
.scope S_0x56004b80baa0;
|
||||
T_0 ;
|
||||
%vpi_call 2 17 "$dumpfile", "logicUnit.vcd" {0 0 0};
|
||||
%vpi_call 2 18 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%store/vec4 v0x56004b83a300_0, 0, 3;
|
||||
%pushi/vec4 1, 0, 4;
|
||||
%store/vec4 v0x56004b83a150_0, 0, 4;
|
||||
%pushi/vec4 1, 0, 4;
|
||||
%store/vec4 v0x56004b83a230_0, 0, 4;
|
||||
%delay 2, 0;
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%store/vec4 v0x56004b83a300_0, 0, 3;
|
||||
%pushi/vec4 3, 0, 4;
|
||||
%store/vec4 v0x56004b83a150_0, 0, 4;
|
||||
%pushi/vec4 1, 0, 4;
|
||||
%store/vec4 v0x56004b83a230_0, 0, 4;
|
||||
%delay 2, 0;
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%store/vec4 v0x56004b83a300_0, 0, 3;
|
||||
%pushi/vec4 9, 0, 4;
|
||||
%store/vec4 v0x56004b83a150_0, 0, 4;
|
||||
%pushi/vec4 9, 0, 4;
|
||||
%store/vec4 v0x56004b83a230_0, 0, 4;
|
||||
%delay 2, 0;
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%store/vec4 v0x56004b83a300_0, 0, 3;
|
||||
%pushi/vec4 15, 0, 4;
|
||||
%store/vec4 v0x56004b83a150_0, 0, 4;
|
||||
%pushi/vec4 15, 0, 4;
|
||||
%store/vec4 v0x56004b83a230_0, 0, 4;
|
||||
%delay 2, 0;
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%store/vec4 v0x56004b83a300_0, 0, 3;
|
||||
%pushi/vec4 0, 0, 4;
|
||||
%store/vec4 v0x56004b83a150_0, 0, 4;
|
||||
%pushi/vec4 0, 0, 4;
|
||||
%store/vec4 v0x56004b83a230_0, 0, 4;
|
||||
%delay 2, 0;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%store/vec4 v0x56004b83a300_0, 0, 3;
|
||||
%pushi/vec4 1, 0, 4;
|
||||
%store/vec4 v0x56004b83a150_0, 0, 4;
|
||||
%pushi/vec4 5, 0, 4;
|
||||
%store/vec4 v0x56004b83a230_0, 0, 4;
|
||||
%delay 2, 0;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%store/vec4 v0x56004b83a300_0, 0, 3;
|
||||
%pushi/vec4 9, 0, 4;
|
||||
%store/vec4 v0x56004b83a150_0, 0, 4;
|
||||
%pushi/vec4 5, 0, 4;
|
||||
%store/vec4 v0x56004b83a230_0, 0, 4;
|
||||
%delay 2, 0;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%store/vec4 v0x56004b83a300_0, 0, 3;
|
||||
%pushi/vec4 1, 0, 4;
|
||||
%store/vec4 v0x56004b83a150_0, 0, 4;
|
||||
%pushi/vec4 15, 0, 4;
|
||||
%store/vec4 v0x56004b83a230_0, 0, 4;
|
||||
%delay 2, 0;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%store/vec4 v0x56004b83a300_0, 0, 3;
|
||||
%pushi/vec4 0, 0, 4;
|
||||
%store/vec4 v0x56004b83a150_0, 0, 4;
|
||||
%pushi/vec4 5, 0, 4;
|
||||
%store/vec4 v0x56004b83a230_0, 0, 4;
|
||||
%delay 2, 0;
|
||||
%pushi/vec4 4, 0, 3;
|
||||
%store/vec4 v0x56004b83a300_0, 0, 3;
|
||||
%pushi/vec4 0, 0, 4;
|
||||
%store/vec4 v0x56004b83a150_0, 0, 4;
|
||||
%pushi/vec4 5, 0, 4;
|
||||
%store/vec4 v0x56004b83a230_0, 0, 4;
|
||||
%delay 2, 0;
|
||||
%pushi/vec4 4, 0, 3;
|
||||
%store/vec4 v0x56004b83a300_0, 0, 3;
|
||||
%pushi/vec4 0, 0, 4;
|
||||
%store/vec4 v0x56004b83a150_0, 0, 4;
|
||||
%pushi/vec4 0, 0, 4;
|
||||
%store/vec4 v0x56004b83a230_0, 0, 4;
|
||||
%delay 2, 0;
|
||||
%pushi/vec4 4, 0, 3;
|
||||
%store/vec4 v0x56004b83a300_0, 0, 3;
|
||||
%pushi/vec4 0, 0, 4;
|
||||
%store/vec4 v0x56004b83a150_0, 0, 4;
|
||||
%pushi/vec4 5, 0, 4;
|
||||
%store/vec4 v0x56004b83a230_0, 0, 4;
|
||||
%delay 2, 0;
|
||||
%pushi/vec4 4, 0, 3;
|
||||
%store/vec4 v0x56004b83a300_0, 0, 3;
|
||||
%pushi/vec4 15, 0, 4;
|
||||
%store/vec4 v0x56004b83a150_0, 0, 4;
|
||||
%pushi/vec4 15, 0, 4;
|
||||
%store/vec4 v0x56004b83a230_0, 0, 4;
|
||||
%delay 2, 0;
|
||||
%vpi_call 2 34 "$finish" {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"logicUnitTB.v";
|
||||
"logicUnit.v";
|
||||
39
project0.2/logicUnit.v
Normal file
39
project0.2/logicUnit.v
Normal file
@@ -0,0 +1,39 @@
|
||||
module logicUnit (
|
||||
input [2:0] opCode,
|
||||
input [3:0] A, B,
|
||||
output [3:0] resultA, resultO, resultX
|
||||
);
|
||||
|
||||
wire [3:0] and1, or1, xor1;
|
||||
|
||||
and a01 (and1[0], A[0], B[0]);
|
||||
and a02 (and1[1], A[1], B[1]);
|
||||
and a03 (and1[2], A[2], B[2]);
|
||||
and a04 (and1[3], A[3], B[3]);
|
||||
|
||||
or o01 (or1[0], A[0], B[0]);
|
||||
or o02 (or1[1], A[1], B[1]);
|
||||
or o03 (or1[2], A[2], B[2]);
|
||||
or o04 (or1[3], A[3], B[3]);
|
||||
|
||||
xor xor01 (xor1[0], A[0], B[0]);
|
||||
xor xor02 (xor1[1], A[1], B[1]);
|
||||
xor xor03 (xor1[2], A[2], B[2]);
|
||||
xor xor04 (xor1[3], A[3], B[3]);
|
||||
|
||||
and a_o1 (resultA[0], opCode[0], and1[0]);
|
||||
and a_o2 (resultA[1], opCode[0], and1[1]);
|
||||
and a_o3 (resultA[2], opCode[0], and1[2]);
|
||||
and a_o4 (resultA[3], opCode[0], and1[3]);
|
||||
|
||||
and o_o1 (resultO[0], opCode[1], or1[0]);
|
||||
and o_o2 (resultO[1], opCode[1], or1[1]);
|
||||
and o_o3 (resultO[2], opCode[1], or1[2]);
|
||||
and o_o4 (resultO[3], opCode[1], or1[3]);
|
||||
|
||||
and x_o1 (resultX[0], opCode[2], xor1[0]);
|
||||
and x_o2 (resultX[1], opCode[2], xor1[1]);
|
||||
and x_o3 (resultX[2], opCode[2], xor1[2]);
|
||||
and x_o4 (resultX[3], opCode[2], xor1[3]);
|
||||
|
||||
endmodule
|
||||
150
project0.2/logicUnit.vcd
Normal file
150
project0.2/logicUnit.vcd
Normal file
@@ -0,0 +1,150 @@
|
||||
$date
|
||||
Sat Dec 14 03:32:40 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module logicUnitTB $end
|
||||
$var wire 4 ! resultX [3:0] $end
|
||||
$var wire 4 " resultO [3:0] $end
|
||||
$var wire 4 # resultA [3:0] $end
|
||||
$var reg 4 $ A [3:0] $end
|
||||
$var reg 4 % B [3:0] $end
|
||||
$var reg 3 & opCode [2:0] $end
|
||||
$scope module uut $end
|
||||
$var wire 4 ' A [3:0] $end
|
||||
$var wire 4 ( B [3:0] $end
|
||||
$var wire 3 ) opCode [2:0] $end
|
||||
$var wire 4 * xor1 [3:0] $end
|
||||
$var wire 4 + resultX [3:0] $end
|
||||
$var wire 4 , resultO [3:0] $end
|
||||
$var wire 4 - resultA [3:0] $end
|
||||
$var wire 4 . or1 [3:0] $end
|
||||
$var wire 4 / and1 [3:0] $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
#0
|
||||
$dumpvars
|
||||
b1 /
|
||||
b1 .
|
||||
b1 -
|
||||
b0 ,
|
||||
b0 +
|
||||
b0 *
|
||||
b1 )
|
||||
b1 (
|
||||
b1 '
|
||||
b1 &
|
||||
b1 %
|
||||
b1 $
|
||||
b1 #
|
||||
b0 "
|
||||
b0 !
|
||||
$end
|
||||
#2
|
||||
b11 .
|
||||
b10 *
|
||||
b11 $
|
||||
b11 '
|
||||
#4
|
||||
b1001 #
|
||||
b1001 -
|
||||
b1001 /
|
||||
b1001 .
|
||||
b0 *
|
||||
b1001 %
|
||||
b1001 (
|
||||
b1001 $
|
||||
b1001 '
|
||||
#6
|
||||
b1111 #
|
||||
b1111 -
|
||||
b1111 /
|
||||
b1111 .
|
||||
b1111 %
|
||||
b1111 (
|
||||
b1111 $
|
||||
b1111 '
|
||||
#8
|
||||
b0 #
|
||||
b0 -
|
||||
b0 /
|
||||
b0 .
|
||||
b0 %
|
||||
b0 (
|
||||
b0 $
|
||||
b0 '
|
||||
#10
|
||||
b101 "
|
||||
b101 ,
|
||||
b100 *
|
||||
b1 /
|
||||
b101 .
|
||||
b101 %
|
||||
b101 (
|
||||
b1 $
|
||||
b1 '
|
||||
b10 &
|
||||
b10 )
|
||||
#12
|
||||
b1101 "
|
||||
b1101 ,
|
||||
b1101 .
|
||||
b1100 *
|
||||
b1001 $
|
||||
b1001 '
|
||||
#14
|
||||
b1111 "
|
||||
b1111 ,
|
||||
b1111 .
|
||||
b1110 *
|
||||
b1111 %
|
||||
b1111 (
|
||||
b1 $
|
||||
b1 '
|
||||
#16
|
||||
b101 "
|
||||
b101 ,
|
||||
b101 .
|
||||
b0 /
|
||||
b101 *
|
||||
b101 %
|
||||
b101 (
|
||||
b0 $
|
||||
b0 '
|
||||
#18
|
||||
b0 "
|
||||
b0 ,
|
||||
b101 !
|
||||
b101 +
|
||||
b100 &
|
||||
b100 )
|
||||
#20
|
||||
b0 !
|
||||
b0 +
|
||||
b0 .
|
||||
b0 *
|
||||
b0 %
|
||||
b0 (
|
||||
#22
|
||||
b101 !
|
||||
b101 +
|
||||
b101 .
|
||||
b101 *
|
||||
b101 %
|
||||
b101 (
|
||||
#24
|
||||
b0 !
|
||||
b0 +
|
||||
b1111 /
|
||||
b1111 .
|
||||
b0 *
|
||||
b1111 %
|
||||
b1111 (
|
||||
b1111 $
|
||||
b1111 '
|
||||
#26
|
||||
37
project0.2/logicUnitTB.v
Normal file
37
project0.2/logicUnitTB.v
Normal file
@@ -0,0 +1,37 @@
|
||||
module logicUnitTB ();
|
||||
|
||||
reg [2:0] opCode;
|
||||
reg [3:0] A, B;
|
||||
wire [3:0] resultA, resultO, resultX;
|
||||
|
||||
logicUnit uut (
|
||||
.opCode(opCode),
|
||||
.A(A),
|
||||
.B(B),
|
||||
.resultA(resultA),
|
||||
.resultO(resultO),
|
||||
.resultX(resultX)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("logicUnit.vcd");
|
||||
$dumpvars;
|
||||
opCode = 3'b001; A = 4'b0001; B = 4'b0001; #2;
|
||||
opCode = 3'b001; A = 4'b0011; B = 4'b0001; #2;
|
||||
opCode = 3'b001; A = 4'b1001; B = 4'b1001; #2;
|
||||
opCode = 3'b001; A = 4'b1111; B = 4'b1111; #2;
|
||||
opCode = 3'b001; A = 4'b0000; B = 4'b0000; #2;
|
||||
|
||||
opCode = 3'b010; A = 4'b0001; B = 4'b0101; #2;
|
||||
opCode = 3'b010; A = 4'b1001; B = 4'b0101; #2;
|
||||
opCode = 3'b010; A = 4'b0001; B = 4'b1111; #2;
|
||||
opCode = 3'b010; A = 4'b0000; B = 4'b0101; #2;
|
||||
|
||||
opCode = 3'b100; A = 4'b0000; B = 4'b0101; #2;
|
||||
opCode = 3'b100; A = 4'b0000; B = 4'b0000; #2;
|
||||
opCode = 3'b100; A = 4'b0000; B = 4'b0101; #2;
|
||||
opCode = 3'b100; A = 4'b1111; B = 4'b1111; #2;
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
957
project0.2/multiplier
Normal file
957
project0.2/multiplier
Normal file
@@ -0,0 +1,957 @@
|
||||
#! /usr/bin/vvp
|
||||
:ivl_version "11.0 (stable)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
|
||||
S_0x55f30e07afd0 .scope module, "multiplierTB" "multiplierTB" 2 1;
|
||||
.timescale 0 0;
|
||||
v0x55f30e0dc920_0 .var "A", 3 0;
|
||||
v0x55f30e0dc9e0_0 .var "B", 3 0;
|
||||
v0x55f30e0dca80_0 .net "Y", 7 0, L_0x55f30e0eaf60; 1 drivers
|
||||
S_0x55f30e070c90 .scope module, "uut" "multiplier" 2 5, 3 1 0, S_0x55f30e07afd0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 4 "A";
|
||||
.port_info 1 /INPUT 4 "B";
|
||||
.port_info 2 /OUTPUT 8 "Y";
|
||||
L_0x55f30e0dcb20 .functor AND 1, L_0x55f30e0dcb90, L_0x55f30e0dccd0, C4<1>, C4<1>;
|
||||
L_0x55f30e0dce10 .functor AND 1, L_0x55f30e0dce80, L_0x55f30e0dcf70, C4<1>, C4<1>;
|
||||
L_0x55f30e0dd060 .functor AND 1, L_0x55f30e0dd0d0, L_0x55f30e0dd1c0, C4<1>, C4<1>;
|
||||
L_0x55f30e0dd330 .functor AND 1, L_0x55f30e0dd3d0, L_0x55f30e0dd470, C4<1>, C4<1>;
|
||||
L_0x7f5d71fc0018 .functor BUFT 1, C4<1>, C4<0>, C4<0>, C4<0>;
|
||||
L_0x55f30e0dd740 .functor NOT 1, L_0x7f5d71fc0018, C4<0>, C4<0>, C4<0>;
|
||||
L_0x55f30e0dd850 .functor AND 1, L_0x55f30e0dd900, L_0x55f30e0dda50, C4<1>, C4<1>;
|
||||
L_0x55f30e0ddaf0 .functor AND 1, L_0x55f30e0ddb60, L_0x55f30e0ddcc0, C4<1>, C4<1>;
|
||||
L_0x55f30e0dddb0 .functor AND 1, L_0x55f30e0dde70, L_0x55f30e0ddfe0, C4<1>, C4<1>;
|
||||
L_0x55f30e0ddc50 .functor AND 1, L_0x55f30e0de450, L_0x55f30e0de540, C4<1>, C4<1>;
|
||||
L_0x55f30e0e1870 .functor AND 1, L_0x55f30e0e1940, L_0x55f30e0de630, C4<1>, C4<1>;
|
||||
L_0x55f30e0e1a90 .functor AND 1, L_0x55f30e0e1b00, L_0x55f30e0e1c60, C4<1>, C4<1>;
|
||||
L_0x55f30e0e1d50 .functor AND 1, L_0x55f30e0e1e30, L_0x55f30e0e1ff0, C4<1>, C4<1>;
|
||||
L_0x55f30e0e2350 .functor AND 1, L_0x55f30e0e2410, L_0x55f30e0e2500, C4<1>, C4<1>;
|
||||
L_0x55f30e0e5c40 .functor AND 1, L_0x55f30e0e5d30, L_0x55f30e0e5dd0, C4<1>, C4<1>;
|
||||
L_0x55f30e0e1dc0 .functor AND 1, L_0x55f30e0e5f80, L_0x55f30e0e6070, C4<1>, C4<1>;
|
||||
L_0x55f30e0e6280 .functor AND 1, L_0x55f30e0e6380, L_0x55f30e0e6470, C4<1>, C4<1>;
|
||||
L_0x55f30e0e6940 .functor AND 1, L_0x55f30e0e6a00, L_0x55f30e0e6c30, C4<1>, C4<1>;
|
||||
L_0x7f5d71fc0210 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||
L_0x55f30e0e9fe0 .functor OR 1, L_0x55f30e0ea0f0, L_0x7f5d71fc0210, C4<0>, C4<0>;
|
||||
L_0x7f5d71fc0258 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||
L_0x55f30e0ea2f0 .functor OR 1, L_0x55f30e0ea360, L_0x7f5d71fc0258, C4<0>, C4<0>;
|
||||
L_0x7f5d71fc02a0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||
L_0x55f30e0ea4a0 .functor OR 1, L_0x55f30e0ea050, L_0x7f5d71fc02a0, C4<0>, C4<0>;
|
||||
L_0x7f5d71fc02e8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||
L_0x55f30e0ea7d0 .functor OR 1, L_0x55f30e0ea840, L_0x7f5d71fc02e8, C4<0>, C4<0>;
|
||||
L_0x7f5d71fc0330 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||
L_0x55f30e0ea980 .functor OR 1, L_0x55f30e0eaab0, L_0x7f5d71fc0330, C4<0>, C4<0>;
|
||||
L_0x7f5d71fc0378 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||
L_0x55f30e0eadb0 .functor OR 1, L_0x55f30e0eae20, L_0x7f5d71fc0378, C4<0>, C4<0>;
|
||||
L_0x7f5d71fc03c0 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||
L_0x55f30e0eb460 .functor OR 1, L_0x55f30e0eb5f0, L_0x7f5d71fc03c0, C4<0>, C4<0>;
|
||||
v0x55f30e0d7700_0 .net "A", 3 0, v0x55f30e0dc920_0; 1 drivers
|
||||
v0x55f30e0d7800_0 .net "B", 3 0, v0x55f30e0dc9e0_0; 1 drivers
|
||||
v0x55f30e0d78e0_0 .net "S0", 4 0, L_0x55f30e0e1740; 1 drivers
|
||||
v0x55f30e0d79a0_0 .net "S1", 4 0, L_0x55f30e0e5a10; 1 drivers
|
||||
v0x55f30e0d7a80_0 .net "S2", 4 0, L_0x55f30e0e9eb0; 1 drivers
|
||||
v0x55f30e0d7bb0_0 .net "Y", 7 0, L_0x55f30e0eaf60; alias, 1 drivers
|
||||
v0x55f30e0d7c90_0 .net *"_ivl_1", 0 0, L_0x55f30e0dcb20; 1 drivers
|
||||
v0x55f30e0d7d70_0 .net *"_ivl_10", 0 0, L_0x55f30e0dce80; 1 drivers
|
||||
v0x55f30e0d7e50_0 .net *"_ivl_101", 0 0, L_0x55f30e0e5dd0; 1 drivers
|
||||
v0x55f30e0d7f30_0 .net *"_ivl_102", 0 0, L_0x55f30e0e1dc0; 1 drivers
|
||||
v0x55f30e0d8010_0 .net *"_ivl_105", 0 0, L_0x55f30e0e5f80; 1 drivers
|
||||
v0x55f30e0d80f0_0 .net *"_ivl_107", 0 0, L_0x55f30e0e6070; 1 drivers
|
||||
v0x55f30e0d81d0_0 .net *"_ivl_108", 0 0, L_0x55f30e0e6280; 1 drivers
|
||||
v0x55f30e0d82b0_0 .net *"_ivl_111", 0 0, L_0x55f30e0e6380; 1 drivers
|
||||
v0x55f30e0d8390_0 .net *"_ivl_113", 0 0, L_0x55f30e0e6470; 1 drivers
|
||||
v0x55f30e0d8470_0 .net *"_ivl_114", 0 0, L_0x55f30e0e6940; 1 drivers
|
||||
v0x55f30e0d8550_0 .net *"_ivl_118", 0 0, L_0x55f30e0e6a00; 1 drivers
|
||||
v0x55f30e0d8740_0 .net *"_ivl_12", 0 0, L_0x55f30e0dcf70; 1 drivers
|
||||
v0x55f30e0d8820_0 .net *"_ivl_120", 0 0, L_0x55f30e0e6c30; 1 drivers
|
||||
v0x55f30e0d8900_0 .net *"_ivl_13", 0 0, L_0x55f30e0dd060; 1 drivers
|
||||
v0x55f30e0d89e0_0 .net *"_ivl_130", 0 0, L_0x55f30e0e9fe0; 1 drivers
|
||||
v0x55f30e0d8ac0_0 .net *"_ivl_133", 0 0, L_0x55f30e0ea0f0; 1 drivers
|
||||
v0x55f30e0d8ba0_0 .net/2u *"_ivl_134", 0 0, L_0x7f5d71fc0210; 1 drivers
|
||||
v0x55f30e0d8c80_0 .net *"_ivl_136", 0 0, L_0x55f30e0ea2f0; 1 drivers
|
||||
v0x55f30e0d8d60_0 .net *"_ivl_139", 0 0, L_0x55f30e0ea360; 1 drivers
|
||||
v0x55f30e0d8e40_0 .net/2u *"_ivl_140", 0 0, L_0x7f5d71fc0258; 1 drivers
|
||||
v0x55f30e0d8f20_0 .net *"_ivl_142", 0 0, L_0x55f30e0ea4a0; 1 drivers
|
||||
v0x55f30e0d9000_0 .net *"_ivl_145", 0 0, L_0x55f30e0ea050; 1 drivers
|
||||
v0x55f30e0d90e0_0 .net/2u *"_ivl_146", 0 0, L_0x7f5d71fc02a0; 1 drivers
|
||||
v0x55f30e0d91c0_0 .net *"_ivl_148", 0 0, L_0x55f30e0ea7d0; 1 drivers
|
||||
v0x55f30e0d92a0_0 .net *"_ivl_151", 0 0, L_0x55f30e0ea840; 1 drivers
|
||||
v0x55f30e0d9380_0 .net/2u *"_ivl_152", 0 0, L_0x7f5d71fc02e8; 1 drivers
|
||||
v0x55f30e0d9460_0 .net *"_ivl_154", 0 0, L_0x55f30e0ea980; 1 drivers
|
||||
v0x55f30e0d9750_0 .net *"_ivl_157", 0 0, L_0x55f30e0eaab0; 1 drivers
|
||||
v0x55f30e0d9830_0 .net/2u *"_ivl_158", 0 0, L_0x7f5d71fc0330; 1 drivers
|
||||
v0x55f30e0d9910_0 .net *"_ivl_16", 0 0, L_0x55f30e0dd0d0; 1 drivers
|
||||
v0x55f30e0d99f0_0 .net *"_ivl_160", 0 0, L_0x55f30e0eadb0; 1 drivers
|
||||
v0x55f30e0d9ad0_0 .net *"_ivl_163", 0 0, L_0x55f30e0eae20; 1 drivers
|
||||
v0x55f30e0d9bb0_0 .net/2u *"_ivl_164", 0 0, L_0x7f5d71fc0378; 1 drivers
|
||||
v0x55f30e0d9c90_0 .net *"_ivl_166", 0 0, L_0x55f30e0eb460; 1 drivers
|
||||
v0x55f30e0d9d70_0 .net *"_ivl_170", 0 0, L_0x55f30e0eb5f0; 1 drivers
|
||||
v0x55f30e0d9e50_0 .net/2u *"_ivl_171", 0 0, L_0x7f5d71fc03c0; 1 drivers
|
||||
v0x55f30e0d9f30_0 .net *"_ivl_18", 0 0, L_0x55f30e0dd1c0; 1 drivers
|
||||
v0x55f30e0da010_0 .net *"_ivl_19", 0 0, L_0x55f30e0dd330; 1 drivers
|
||||
v0x55f30e0da0f0_0 .net *"_ivl_22", 0 0, L_0x55f30e0dd3d0; 1 drivers
|
||||
v0x55f30e0da1d0_0 .net *"_ivl_24", 0 0, L_0x55f30e0dd470; 1 drivers
|
||||
v0x55f30e0da2b0_0 .net *"_ivl_25", 0 0, L_0x55f30e0dd740; 1 drivers
|
||||
v0x55f30e0da390_0 .net/2u *"_ivl_28", 0 0, L_0x7f5d71fc0018; 1 drivers
|
||||
v0x55f30e0da470_0 .net *"_ivl_30", 0 0, L_0x55f30e0dd850; 1 drivers
|
||||
v0x55f30e0da550_0 .net *"_ivl_33", 0 0, L_0x55f30e0dd900; 1 drivers
|
||||
v0x55f30e0da630_0 .net *"_ivl_35", 0 0, L_0x55f30e0dda50; 1 drivers
|
||||
v0x55f30e0da710_0 .net *"_ivl_36", 0 0, L_0x55f30e0ddaf0; 1 drivers
|
||||
v0x55f30e0da7f0_0 .net *"_ivl_39", 0 0, L_0x55f30e0ddb60; 1 drivers
|
||||
v0x55f30e0da8d0_0 .net *"_ivl_4", 0 0, L_0x55f30e0dcb90; 1 drivers
|
||||
v0x55f30e0da9b0_0 .net *"_ivl_41", 0 0, L_0x55f30e0ddcc0; 1 drivers
|
||||
v0x55f30e0daa90_0 .net *"_ivl_42", 0 0, L_0x55f30e0dddb0; 1 drivers
|
||||
v0x55f30e0dab70_0 .net *"_ivl_45", 0 0, L_0x55f30e0dde70; 1 drivers
|
||||
v0x55f30e0dac50_0 .net *"_ivl_47", 0 0, L_0x55f30e0ddfe0; 1 drivers
|
||||
v0x55f30e0dad30_0 .net *"_ivl_48", 0 0, L_0x55f30e0ddc50; 1 drivers
|
||||
v0x55f30e0dae10_0 .net *"_ivl_52", 0 0, L_0x55f30e0de450; 1 drivers
|
||||
v0x55f30e0daef0_0 .net *"_ivl_54", 0 0, L_0x55f30e0de540; 1 drivers
|
||||
v0x55f30e0dafd0_0 .net *"_ivl_6", 0 0, L_0x55f30e0dccd0; 1 drivers
|
||||
v0x55f30e0db0b0_0 .net *"_ivl_62", 0 0, L_0x55f30e0e1870; 1 drivers
|
||||
v0x55f30e0db190_0 .net *"_ivl_65", 0 0, L_0x55f30e0e1940; 1 drivers
|
||||
v0x55f30e0db270_0 .net *"_ivl_67", 0 0, L_0x55f30e0de630; 1 drivers
|
||||
v0x55f30e0db760_0 .net *"_ivl_68", 0 0, L_0x55f30e0e1a90; 1 drivers
|
||||
v0x55f30e0db840_0 .net *"_ivl_7", 0 0, L_0x55f30e0dce10; 1 drivers
|
||||
v0x55f30e0db920_0 .net *"_ivl_71", 0 0, L_0x55f30e0e1b00; 1 drivers
|
||||
v0x55f30e0dba00_0 .net *"_ivl_73", 0 0, L_0x55f30e0e1c60; 1 drivers
|
||||
v0x55f30e0dbae0_0 .net *"_ivl_74", 0 0, L_0x55f30e0e1d50; 1 drivers
|
||||
v0x55f30e0dbbc0_0 .net *"_ivl_77", 0 0, L_0x55f30e0e1e30; 1 drivers
|
||||
v0x55f30e0dbca0_0 .net *"_ivl_79", 0 0, L_0x55f30e0e1ff0; 1 drivers
|
||||
v0x55f30e0dbd80_0 .net *"_ivl_80", 0 0, L_0x55f30e0e2350; 1 drivers
|
||||
v0x55f30e0dbe60_0 .net *"_ivl_84", 0 0, L_0x55f30e0e2410; 1 drivers
|
||||
v0x55f30e0dbf40_0 .net *"_ivl_86", 0 0, L_0x55f30e0e2500; 1 drivers
|
||||
v0x55f30e0dc020_0 .net *"_ivl_96", 0 0, L_0x55f30e0e5c40; 1 drivers
|
||||
v0x55f30e0dc100_0 .net *"_ivl_99", 0 0, L_0x55f30e0e5d30; 1 drivers
|
||||
v0x55f30e0dc1e0_0 .net "a0", 3 0, L_0x55f30e0de1e0; 1 drivers
|
||||
v0x55f30e0dc2a0_0 .net "a1", 3 0, L_0x55f30e0e20e0; 1 drivers
|
||||
v0x55f30e0dc3b0_0 .net "a2", 3 0, L_0x55f30e0e6160; 1 drivers
|
||||
v0x55f30e0dc4c0_0 .net "b0", 3 0, L_0x55f30e0dd5b0; 1 drivers
|
||||
v0x55f30e0dc5d0_0 .net "overflow0", 0 0, L_0x55f30e0e1630; 1 drivers
|
||||
v0x55f30e0dc6c0_0 .net "overflow1", 0 0, L_0x55f30e0e56b0; 1 drivers
|
||||
v0x55f30e0dc7b0_0 .net "overflow2", 0 0, L_0x55f30e0e9b60; 1 drivers
|
||||
L_0x55f30e0dcb90 .part v0x55f30e0dc920_0, 0, 1;
|
||||
L_0x55f30e0dccd0 .part v0x55f30e0dc9e0_0, 0, 1;
|
||||
L_0x55f30e0dce80 .part v0x55f30e0dc920_0, 1, 1;
|
||||
L_0x55f30e0dcf70 .part v0x55f30e0dc9e0_0, 0, 1;
|
||||
L_0x55f30e0dd0d0 .part v0x55f30e0dc920_0, 2, 1;
|
||||
L_0x55f30e0dd1c0 .part v0x55f30e0dc9e0_0, 0, 1;
|
||||
L_0x55f30e0dd3d0 .part v0x55f30e0dc920_0, 3, 1;
|
||||
L_0x55f30e0dd470 .part v0x55f30e0dc9e0_0, 0, 1;
|
||||
L_0x55f30e0dd5b0 .concat8 [ 1 1 1 1], L_0x55f30e0dce10, L_0x55f30e0dd060, L_0x55f30e0dd330, L_0x55f30e0dd740;
|
||||
L_0x55f30e0dd900 .part v0x55f30e0dc920_0, 0, 1;
|
||||
L_0x55f30e0dda50 .part v0x55f30e0dc9e0_0, 1, 1;
|
||||
L_0x55f30e0ddb60 .part v0x55f30e0dc920_0, 1, 1;
|
||||
L_0x55f30e0ddcc0 .part v0x55f30e0dc9e0_0, 1, 1;
|
||||
L_0x55f30e0dde70 .part v0x55f30e0dc920_0, 2, 1;
|
||||
L_0x55f30e0ddfe0 .part v0x55f30e0dc9e0_0, 1, 1;
|
||||
L_0x55f30e0de1e0 .concat8 [ 1 1 1 1], L_0x55f30e0dd850, L_0x55f30e0ddaf0, L_0x55f30e0dddb0, L_0x55f30e0ddc50;
|
||||
L_0x55f30e0de450 .part v0x55f30e0dc920_0, 3, 1;
|
||||
L_0x55f30e0de540 .part v0x55f30e0dc9e0_0, 1, 1;
|
||||
L_0x55f30e0e1740 .concat8 [ 4 1 0 0], L_0x55f30e0e03e0, L_0x55f30e0dff40;
|
||||
L_0x55f30e0e1940 .part v0x55f30e0dc920_0, 0, 1;
|
||||
L_0x55f30e0de630 .part v0x55f30e0dc9e0_0, 2, 1;
|
||||
L_0x55f30e0e1b00 .part v0x55f30e0dc920_0, 1, 1;
|
||||
L_0x55f30e0e1c60 .part v0x55f30e0dc9e0_0, 2, 1;
|
||||
L_0x55f30e0e1e30 .part v0x55f30e0dc920_0, 2, 1;
|
||||
L_0x55f30e0e1ff0 .part v0x55f30e0dc9e0_0, 2, 1;
|
||||
L_0x55f30e0e20e0 .concat8 [ 1 1 1 1], L_0x55f30e0e1870, L_0x55f30e0e1a90, L_0x55f30e0e1d50, L_0x55f30e0e2350;
|
||||
L_0x55f30e0e2410 .part v0x55f30e0dc920_0, 3, 1;
|
||||
L_0x55f30e0e2500 .part v0x55f30e0dc9e0_0, 2, 1;
|
||||
L_0x55f30e0e57c0 .part L_0x55f30e0e1740, 1, 4;
|
||||
L_0x55f30e0e5a10 .concat8 [ 4 1 0 0], L_0x55f30e0e45b0, L_0x55f30e0e4110;
|
||||
L_0x55f30e0e5d30 .part v0x55f30e0dc920_0, 0, 1;
|
||||
L_0x55f30e0e5dd0 .part v0x55f30e0dc9e0_0, 3, 1;
|
||||
L_0x55f30e0e5f80 .part v0x55f30e0dc920_0, 1, 1;
|
||||
L_0x55f30e0e6070 .part v0x55f30e0dc9e0_0, 3, 1;
|
||||
L_0x55f30e0e6380 .part v0x55f30e0dc920_0, 2, 1;
|
||||
L_0x55f30e0e6470 .part v0x55f30e0dc9e0_0, 3, 1;
|
||||
L_0x55f30e0e6160 .concat8 [ 1 1 1 1], L_0x55f30e0e5c40, L_0x55f30e0e1dc0, L_0x55f30e0e6280, L_0x55f30e0e6940;
|
||||
L_0x55f30e0e6a00 .part v0x55f30e0dc920_0, 3, 1;
|
||||
L_0x55f30e0e6c30 .part v0x55f30e0dc9e0_0, 3, 1;
|
||||
L_0x55f30e0e9c70 .part L_0x55f30e0e5a10, 1, 4;
|
||||
L_0x55f30e0e9eb0 .concat8 [ 4 1 0 0], L_0x55f30e0e8bb0, L_0x55f30e0e8710;
|
||||
L_0x55f30e0ea0f0 .part L_0x55f30e0e1740, 0, 1;
|
||||
L_0x55f30e0ea360 .part L_0x55f30e0e5a10, 0, 1;
|
||||
L_0x55f30e0ea050 .part L_0x55f30e0e9eb0, 0, 1;
|
||||
L_0x55f30e0ea840 .part L_0x55f30e0e9eb0, 1, 1;
|
||||
L_0x55f30e0eaab0 .part L_0x55f30e0e9eb0, 2, 1;
|
||||
L_0x55f30e0eae20 .part L_0x55f30e0e9eb0, 3, 1;
|
||||
LS_0x55f30e0eaf60_0_0 .concat8 [ 1 1 1 1], L_0x55f30e0dcb20, L_0x55f30e0e9fe0, L_0x55f30e0ea2f0, L_0x55f30e0ea4a0;
|
||||
LS_0x55f30e0eaf60_0_4 .concat8 [ 1 1 1 1], L_0x55f30e0ea7d0, L_0x55f30e0ea980, L_0x55f30e0eadb0, L_0x55f30e0eb460;
|
||||
L_0x55f30e0eaf60 .concat8 [ 4 4 0 0], LS_0x55f30e0eaf60_0_0, LS_0x55f30e0eaf60_0_4;
|
||||
L_0x55f30e0eb5f0 .part L_0x55f30e0e9eb0, 4, 1;
|
||||
S_0x55f30e094c90 .scope module, "add0" "addition" 3 26, 4 1 0, S_0x55f30e070c90;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 4 "A";
|
||||
.port_info 1 /INPUT 4 "B";
|
||||
.port_info 2 /INPUT 1 "CarryIN";
|
||||
.port_info 3 /OUTPUT 4 "Y";
|
||||
.port_info 4 /OUTPUT 1 "CarryOUT";
|
||||
.port_info 5 /OUTPUT 1 "overflow";
|
||||
v0x55f30e0c81a0_0 .net "A", 3 0, L_0x55f30e0de1e0; alias, 1 drivers
|
||||
v0x55f30e0c8280_0 .net "B", 3 0, L_0x55f30e0dd5b0; alias, 1 drivers
|
||||
v0x55f30e0c8350_0 .net "Carry4", 3 0, L_0x55f30e0eb730; 1 drivers
|
||||
L_0x7f5d71fc00a8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55f30e0c8420_0 .net "CarryIN", 0 0, L_0x7f5d71fc00a8; 1 drivers
|
||||
v0x55f30e0c84c0_0 .net "CarryOUT", 0 0, L_0x55f30e0dff40; 1 drivers
|
||||
v0x55f30e0c8600_0 .net "Y", 3 0, L_0x55f30e0e03e0; 1 drivers
|
||||
o0x7f5d7200a578 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
; Elide local net with no drivers, v0x55f30e0c86c0_0 name=_ivl_41
|
||||
v0x55f30e0c8780_0 .net "overflow", 0 0, L_0x55f30e0e1630; alias, 1 drivers
|
||||
L_0x55f30e0dea40 .part L_0x55f30e0de1e0, 0, 1;
|
||||
L_0x55f30e0deb70 .part L_0x55f30e0dd5b0, 0, 1;
|
||||
L_0x55f30e0deff0 .part L_0x55f30e0de1e0, 1, 1;
|
||||
L_0x55f30e0df120 .part L_0x55f30e0dd5b0, 1, 1;
|
||||
L_0x55f30e0df250 .part L_0x55f30e0eb730, 0, 1;
|
||||
L_0x55f30e0df720 .part L_0x55f30e0de1e0, 2, 1;
|
||||
L_0x55f30e0df890 .part L_0x55f30e0dd5b0, 2, 1;
|
||||
L_0x55f30e0df9c0 .part L_0x55f30e0eb730, 1, 1;
|
||||
L_0x55f30e0dfff0 .part L_0x55f30e0de1e0, 3, 1;
|
||||
L_0x55f30e0e0120 .part L_0x55f30e0dd5b0, 3, 1;
|
||||
L_0x55f30e0e02b0 .part L_0x55f30e0eb730, 2, 1;
|
||||
L_0x55f30e0e03e0 .concat8 [ 1 1 1 1], L_0x55f30e0de960, L_0x55f30e0def10, L_0x55f30e0df5b0, L_0x55f30e0dfe60;
|
||||
L_0x55f30e0eb730 .concat [ 1 1 1 1], L_0x55f30e0de9d0, L_0x55f30e0def80, L_0x55f30e0df690, o0x7f5d7200a578;
|
||||
S_0x55f30e087a30 .scope module, "f0" "fulladder" 4 11, 5 1 0, S_0x55f30e094c90;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "Carry";
|
||||
.port_info 3 /OUTPUT 1 "Sum";
|
||||
.port_info 4 /OUTPUT 1 "CarryO";
|
||||
L_0x55f30e0de9d0 .functor OR 1, L_0x55f30e0de6d0, L_0x55f30e0de8a0, C4<0>, C4<0>;
|
||||
v0x55f30e0c26d0_0 .net "A", 0 0, L_0x55f30e0dea40; 1 drivers
|
||||
v0x55f30e0c2790_0 .net "B", 0 0, L_0x55f30e0deb70; 1 drivers
|
||||
v0x55f30e0c2860_0 .net "Carry", 0 0, L_0x7f5d71fc00a8; alias, 1 drivers
|
||||
v0x55f30e0c2960_0 .net "CarryO", 0 0, L_0x55f30e0de9d0; 1 drivers
|
||||
v0x55f30e0c2a00_0 .net "Sum", 0 0, L_0x55f30e0de960; 1 drivers
|
||||
v0x55f30e0c2aa0_0 .net "and1", 0 0, L_0x55f30e0de6d0; 1 drivers
|
||||
v0x55f30e0c2b70_0 .net "and2", 0 0, L_0x55f30e0de8a0; 1 drivers
|
||||
v0x55f30e0c2c40_0 .net "xor1", 0 0, L_0x55f30e0de830; 1 drivers
|
||||
S_0x55f30e0a2230 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55f30e087a30;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x55f30e0de6d0 .functor AND 1, L_0x55f30e0dea40, L_0x55f30e0deb70, C4<1>, C4<1>;
|
||||
L_0x55f30e0de830 .functor XOR 1, L_0x55f30e0dea40, L_0x55f30e0deb70, C4<0>, C4<0>;
|
||||
v0x55f30e0902b0_0 .net "A", 0 0, L_0x55f30e0dea40; alias, 1 drivers
|
||||
v0x55f30e084b20_0 .net "B", 0 0, L_0x55f30e0deb70; alias, 1 drivers
|
||||
v0x55f30e083050_0 .net "Carry", 0 0, L_0x55f30e0de6d0; alias, 1 drivers
|
||||
v0x55f30e0a7570_0 .net "Sum", 0 0, L_0x55f30e0de830; alias, 1 drivers
|
||||
S_0x55f30e0c22e0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55f30e087a30;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x55f30e0de8a0 .functor AND 1, L_0x55f30e0de830, L_0x7f5d71fc00a8, C4<1>, C4<1>;
|
||||
L_0x55f30e0de960 .functor XOR 1, L_0x55f30e0de830, L_0x7f5d71fc00a8, C4<0>, C4<0>;
|
||||
v0x55f30e0a6830_0 .net "A", 0 0, L_0x55f30e0de830; alias, 1 drivers
|
||||
v0x55f30e0127f0_0 .net "B", 0 0, L_0x7f5d71fc00a8; alias, 1 drivers
|
||||
v0x55f30e0c2490_0 .net "Carry", 0 0, L_0x55f30e0de8a0; alias, 1 drivers
|
||||
v0x55f30e0c2560_0 .net "Sum", 0 0, L_0x55f30e0de960; alias, 1 drivers
|
||||
S_0x55f30e0c2d30 .scope module, "f1" "fulladder" 4 12, 5 1 0, S_0x55f30e094c90;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "Carry";
|
||||
.port_info 3 /OUTPUT 1 "Sum";
|
||||
.port_info 4 /OUTPUT 1 "CarryO";
|
||||
L_0x55f30e0def80 .functor OR 1, L_0x55f30e0ded30, L_0x55f30e0dee10, C4<0>, C4<0>;
|
||||
v0x55f30e0c3ab0_0 .net "A", 0 0, L_0x55f30e0deff0; 1 drivers
|
||||
v0x55f30e0c3b70_0 .net "B", 0 0, L_0x55f30e0df120; 1 drivers
|
||||
v0x55f30e0c3c40_0 .net "Carry", 0 0, L_0x55f30e0df250; 1 drivers
|
||||
v0x55f30e0c3d40_0 .net "CarryO", 0 0, L_0x55f30e0def80; 1 drivers
|
||||
v0x55f30e0c3de0_0 .net "Sum", 0 0, L_0x55f30e0def10; 1 drivers
|
||||
v0x55f30e0c3ed0_0 .net "and1", 0 0, L_0x55f30e0ded30; 1 drivers
|
||||
v0x55f30e0c3fa0_0 .net "and2", 0 0, L_0x55f30e0dee10; 1 drivers
|
||||
v0x55f30e0c4070_0 .net "xor1", 0 0, L_0x55f30e0deda0; 1 drivers
|
||||
S_0x55f30e0c2f10 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55f30e0c2d30;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x55f30e0ded30 .functor AND 1, L_0x55f30e0deff0, L_0x55f30e0df120, C4<1>, C4<1>;
|
||||
L_0x55f30e0deda0 .functor XOR 1, L_0x55f30e0deff0, L_0x55f30e0df120, C4<0>, C4<0>;
|
||||
v0x55f30e0c3120_0 .net "A", 0 0, L_0x55f30e0deff0; alias, 1 drivers
|
||||
v0x55f30e0c3200_0 .net "B", 0 0, L_0x55f30e0df120; alias, 1 drivers
|
||||
v0x55f30e0c32c0_0 .net "Carry", 0 0, L_0x55f30e0ded30; alias, 1 drivers
|
||||
v0x55f30e0c3390_0 .net "Sum", 0 0, L_0x55f30e0deda0; alias, 1 drivers
|
||||
S_0x55f30e0c3500 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55f30e0c2d30;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x55f30e0dee10 .functor AND 1, L_0x55f30e0deda0, L_0x55f30e0df250, C4<1>, C4<1>;
|
||||
L_0x55f30e0def10 .functor XOR 1, L_0x55f30e0deda0, L_0x55f30e0df250, C4<0>, C4<0>;
|
||||
v0x55f30e0c3700_0 .net "A", 0 0, L_0x55f30e0deda0; alias, 1 drivers
|
||||
v0x55f30e0c37d0_0 .net "B", 0 0, L_0x55f30e0df250; alias, 1 drivers
|
||||
v0x55f30e0c3870_0 .net "Carry", 0 0, L_0x55f30e0dee10; alias, 1 drivers
|
||||
v0x55f30e0c3940_0 .net "Sum", 0 0, L_0x55f30e0def10; alias, 1 drivers
|
||||
S_0x55f30e0c4160 .scope module, "f2" "fulladder" 4 13, 5 1 0, S_0x55f30e094c90;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "Carry";
|
||||
.port_info 3 /OUTPUT 1 "Sum";
|
||||
.port_info 4 /OUTPUT 1 "CarryO";
|
||||
L_0x55f30e0df690 .functor OR 1, L_0x55f30e0df380, L_0x55f30e0df460, C4<0>, C4<0>;
|
||||
v0x55f30e0c4ef0_0 .net "A", 0 0, L_0x55f30e0df720; 1 drivers
|
||||
v0x55f30e0c4fb0_0 .net "B", 0 0, L_0x55f30e0df890; 1 drivers
|
||||
v0x55f30e0c5080_0 .net "Carry", 0 0, L_0x55f30e0df9c0; 1 drivers
|
||||
v0x55f30e0c5180_0 .net "CarryO", 0 0, L_0x55f30e0df690; 1 drivers
|
||||
v0x55f30e0c5220_0 .net "Sum", 0 0, L_0x55f30e0df5b0; 1 drivers
|
||||
v0x55f30e0c5310_0 .net "and1", 0 0, L_0x55f30e0df380; 1 drivers
|
||||
v0x55f30e0c53e0_0 .net "and2", 0 0, L_0x55f30e0df460; 1 drivers
|
||||
v0x55f30e0c54b0_0 .net "xor1", 0 0, L_0x55f30e0df3f0; 1 drivers
|
||||
S_0x55f30e0c4370 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55f30e0c4160;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x55f30e0df380 .functor AND 1, L_0x55f30e0df720, L_0x55f30e0df890, C4<1>, C4<1>;
|
||||
L_0x55f30e0df3f0 .functor XOR 1, L_0x55f30e0df720, L_0x55f30e0df890, C4<0>, C4<0>;
|
||||
v0x55f30e0c4580_0 .net "A", 0 0, L_0x55f30e0df720; alias, 1 drivers
|
||||
v0x55f30e0c4640_0 .net "B", 0 0, L_0x55f30e0df890; alias, 1 drivers
|
||||
v0x55f30e0c4700_0 .net "Carry", 0 0, L_0x55f30e0df380; alias, 1 drivers
|
||||
v0x55f30e0c47d0_0 .net "Sum", 0 0, L_0x55f30e0df3f0; alias, 1 drivers
|
||||
S_0x55f30e0c4940 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55f30e0c4160;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x55f30e0df460 .functor AND 1, L_0x55f30e0df3f0, L_0x55f30e0df9c0, C4<1>, C4<1>;
|
||||
L_0x55f30e0df5b0 .functor XOR 1, L_0x55f30e0df3f0, L_0x55f30e0df9c0, C4<0>, C4<0>;
|
||||
v0x55f30e0c4b40_0 .net "A", 0 0, L_0x55f30e0df3f0; alias, 1 drivers
|
||||
v0x55f30e0c4c10_0 .net "B", 0 0, L_0x55f30e0df9c0; alias, 1 drivers
|
||||
v0x55f30e0c4cb0_0 .net "Carry", 0 0, L_0x55f30e0df460; alias, 1 drivers
|
||||
v0x55f30e0c4d80_0 .net "Sum", 0 0, L_0x55f30e0df5b0; alias, 1 drivers
|
||||
S_0x55f30e0c55a0 .scope module, "f3" "fulladder" 4 14, 5 1 0, S_0x55f30e094c90;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "Carry";
|
||||
.port_info 3 /OUTPUT 1 "Sum";
|
||||
.port_info 4 /OUTPUT 1 "CarryO";
|
||||
L_0x55f30e0dff40 .functor OR 1, L_0x55f30e0dfb40, L_0x55f30e0dfcd0, C4<0>, C4<0>;
|
||||
v0x55f30e0c6320_0 .net "A", 0 0, L_0x55f30e0dfff0; 1 drivers
|
||||
v0x55f30e0c63e0_0 .net "B", 0 0, L_0x55f30e0e0120; 1 drivers
|
||||
v0x55f30e0c64b0_0 .net "Carry", 0 0, L_0x55f30e0e02b0; 1 drivers
|
||||
v0x55f30e0c65b0_0 .net "CarryO", 0 0, L_0x55f30e0dff40; alias, 1 drivers
|
||||
v0x55f30e0c6650_0 .net "Sum", 0 0, L_0x55f30e0dfe60; 1 drivers
|
||||
v0x55f30e0c6740_0 .net "and1", 0 0, L_0x55f30e0dfb40; 1 drivers
|
||||
v0x55f30e0c6810_0 .net "and2", 0 0, L_0x55f30e0dfcd0; 1 drivers
|
||||
v0x55f30e0c68e0_0 .net "xor1", 0 0, L_0x55f30e0dfc40; 1 drivers
|
||||
S_0x55f30e0c5780 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55f30e0c55a0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x55f30e0dfb40 .functor AND 1, L_0x55f30e0dfff0, L_0x55f30e0e0120, C4<1>, C4<1>;
|
||||
L_0x55f30e0dfc40 .functor XOR 1, L_0x55f30e0dfff0, L_0x55f30e0e0120, C4<0>, C4<0>;
|
||||
v0x55f30e0c5990_0 .net "A", 0 0, L_0x55f30e0dfff0; alias, 1 drivers
|
||||
v0x55f30e0c5a70_0 .net "B", 0 0, L_0x55f30e0e0120; alias, 1 drivers
|
||||
v0x55f30e0c5b30_0 .net "Carry", 0 0, L_0x55f30e0dfb40; alias, 1 drivers
|
||||
v0x55f30e0c5c00_0 .net "Sum", 0 0, L_0x55f30e0dfc40; alias, 1 drivers
|
||||
S_0x55f30e0c5d70 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55f30e0c55a0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x55f30e0dfcd0 .functor AND 1, L_0x55f30e0dfc40, L_0x55f30e0e02b0, C4<1>, C4<1>;
|
||||
L_0x55f30e0dfe60 .functor XOR 1, L_0x55f30e0dfc40, L_0x55f30e0e02b0, C4<0>, C4<0>;
|
||||
v0x55f30e0c5f70_0 .net "A", 0 0, L_0x55f30e0dfc40; alias, 1 drivers
|
||||
v0x55f30e0c6040_0 .net "B", 0 0, L_0x55f30e0e02b0; alias, 1 drivers
|
||||
v0x55f30e0c60e0_0 .net "Carry", 0 0, L_0x55f30e0dfcd0; alias, 1 drivers
|
||||
v0x55f30e0c61b0_0 .net "Sum", 0 0, L_0x55f30e0dfe60; alias, 1 drivers
|
||||
S_0x55f30e0c69d0 .scope module, "od1" "overflowDetect" 4 17, 7 1 0, S_0x55f30e094c90;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 2 "opCode";
|
||||
.port_info 1 /INPUT 4 "A";
|
||||
.port_info 2 /INPUT 4 "B";
|
||||
.port_info 3 /INPUT 4 "Y";
|
||||
.port_info 4 /INPUT 1 "CarryOUT";
|
||||
.port_info 5 /OUTPUT 1 "overflowDetect";
|
||||
L_0x55f30e0e04f0 .functor OR 1, L_0x55f30e0e0580, L_0x55f30e0e0620, C4<0>, C4<0>;
|
||||
L_0x55f30e0e06c0 .functor XNOR 1, L_0x55f30e0e0730, L_0x55f30e0e0930, C4<0>, C4<0>;
|
||||
L_0x55f30e0e0b30 .functor XOR 1, L_0x55f30e0e0ba0, L_0x55f30e0e0c90, C4<0>, C4<0>;
|
||||
L_0x55f30e0e0dc0 .functor XOR 1, L_0x55f30e0e0e30, L_0x55f30e0e0f20, C4<0>, C4<0>;
|
||||
L_0x55f30e0e1060 .functor AND 1, L_0x55f30e0e06c0, L_0x55f30e0e1120, C4<1>, C4<1>;
|
||||
L_0x55f30e0e1210 .functor AND 1, L_0x55f30e0e0b30, L_0x55f30e0e1310, C4<1>, C4<1>;
|
||||
L_0x55f30e0e1460 .functor OR 1, L_0x55f30e0e1060, L_0x55f30e0e1210, C4<0>, C4<0>;
|
||||
L_0x55f30e0e14d0 .functor AND 1, L_0x55f30e0e1460, L_0x55f30e0e0dc0, C4<1>, C4<1>;
|
||||
L_0x55f30e0e1630 .functor AND 1, L_0x55f30e0e04f0, L_0x55f30e0e14d0, C4<1>, C4<1>;
|
||||
v0x55f30e0c6ca0_0 .net "A", 3 0, L_0x55f30e0de1e0; alias, 1 drivers
|
||||
v0x55f30e0c6d80_0 .net "B", 3 0, L_0x55f30e0dd5b0; alias, 1 drivers
|
||||
v0x55f30e0c6e60_0 .net "CarryOUT", 0 0, L_0x55f30e0dff40; alias, 1 drivers
|
||||
v0x55f30e0c6f00_0 .net "Y", 3 0, L_0x55f30e0e03e0; alias, 1 drivers
|
||||
v0x55f30e0c6fa0_0 .net *"_ivl_1", 0 0, L_0x55f30e0e0580; 1 drivers
|
||||
v0x55f30e0c70d0_0 .net *"_ivl_11", 0 0, L_0x55f30e0e0c90; 1 drivers
|
||||
v0x55f30e0c71b0_0 .net *"_ivl_13", 0 0, L_0x55f30e0e0e30; 1 drivers
|
||||
v0x55f30e0c7290_0 .net *"_ivl_15", 0 0, L_0x55f30e0e0f20; 1 drivers
|
||||
v0x55f30e0c7370_0 .net *"_ivl_17", 0 0, L_0x55f30e0e1120; 1 drivers
|
||||
v0x55f30e0c74e0_0 .net *"_ivl_19", 0 0, L_0x55f30e0e1310; 1 drivers
|
||||
v0x55f30e0c75c0_0 .net *"_ivl_3", 0 0, L_0x55f30e0e0620; 1 drivers
|
||||
v0x55f30e0c76a0_0 .net *"_ivl_5", 0 0, L_0x55f30e0e0730; 1 drivers
|
||||
v0x55f30e0c7780_0 .net *"_ivl_7", 0 0, L_0x55f30e0e0930; 1 drivers
|
||||
v0x55f30e0c7860_0 .net *"_ivl_9", 0 0, L_0x55f30e0e0ba0; 1 drivers
|
||||
v0x55f30e0c7940_0 .net "addOverflow", 0 0, L_0x55f30e0e1060; 1 drivers
|
||||
v0x55f30e0c7a00_0 .net "detect1", 0 0, L_0x55f30e0e1460; 1 drivers
|
||||
v0x55f30e0c7ac0_0 .net "detect2", 0 0, L_0x55f30e0e14d0; 1 drivers
|
||||
v0x55f30e0c7b80_0 .net "opC", 0 0, L_0x55f30e0e04f0; 1 drivers
|
||||
L_0x7f5d71fc0060 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55f30e0c7c40_0 .net "opCode", 1 0, L_0x7f5d71fc0060; 1 drivers
|
||||
v0x55f30e0c7d20_0 .net "overflowDetect", 0 0, L_0x55f30e0e1630; alias, 1 drivers
|
||||
v0x55f30e0c7de0_0 .net "sign1", 0 0, L_0x55f30e0e06c0; 1 drivers
|
||||
v0x55f30e0c7ea0_0 .net "sign2", 0 0, L_0x55f30e0e0dc0; 1 drivers
|
||||
v0x55f30e0c7f60_0 .net "sign3", 0 0, L_0x55f30e0e0b30; 1 drivers
|
||||
v0x55f30e0c8020_0 .net "subOverflow", 0 0, L_0x55f30e0e1210; 1 drivers
|
||||
L_0x55f30e0e0580 .part L_0x7f5d71fc0060, 0, 1;
|
||||
L_0x55f30e0e0620 .part L_0x7f5d71fc0060, 1, 1;
|
||||
L_0x55f30e0e0730 .part L_0x55f30e0de1e0, 3, 1;
|
||||
L_0x55f30e0e0930 .part L_0x55f30e0dd5b0, 3, 1;
|
||||
L_0x55f30e0e0ba0 .part L_0x55f30e0de1e0, 3, 1;
|
||||
L_0x55f30e0e0c90 .part L_0x55f30e0dd5b0, 3, 1;
|
||||
L_0x55f30e0e0e30 .part L_0x55f30e0e03e0, 3, 1;
|
||||
L_0x55f30e0e0f20 .part L_0x55f30e0de1e0, 3, 1;
|
||||
L_0x55f30e0e1120 .part L_0x7f5d71fc0060, 0, 1;
|
||||
L_0x55f30e0e1310 .part L_0x7f5d71fc0060, 1, 1;
|
||||
S_0x55f30e0c88c0 .scope module, "add1" "addition" 3 42, 4 1 0, S_0x55f30e070c90;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 4 "A";
|
||||
.port_info 1 /INPUT 4 "B";
|
||||
.port_info 2 /INPUT 1 "CarryIN";
|
||||
.port_info 3 /OUTPUT 4 "Y";
|
||||
.port_info 4 /OUTPUT 1 "CarryOUT";
|
||||
.port_info 5 /OUTPUT 1 "overflow";
|
||||
v0x55f30e0cf710_0 .net "A", 3 0, L_0x55f30e0e20e0; alias, 1 drivers
|
||||
v0x55f30e0cf7f0_0 .net "B", 3 0, L_0x55f30e0e57c0; 1 drivers
|
||||
v0x55f30e0cf8c0_0 .net "Carry4", 3 0, L_0x55f30e0eb900; 1 drivers
|
||||
L_0x7f5d71fc0138 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55f30e0cf990_0 .net "CarryIN", 0 0, L_0x7f5d71fc0138; 1 drivers
|
||||
v0x55f30e0cfa30_0 .net "CarryOUT", 0 0, L_0x55f30e0e4110; 1 drivers
|
||||
v0x55f30e0cfb70_0 .net "Y", 3 0, L_0x55f30e0e45b0; 1 drivers
|
||||
o0x7f5d7200bc28 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
; Elide local net with no drivers, v0x55f30e0cfc30_0 name=_ivl_41
|
||||
v0x55f30e0cfcf0_0 .net "overflow", 0 0, L_0x55f30e0e56b0; alias, 1 drivers
|
||||
L_0x55f30e0e2b70 .part L_0x55f30e0e20e0, 0, 1;
|
||||
L_0x55f30e0e2d30 .part L_0x55f30e0e57c0, 0, 1;
|
||||
L_0x55f30e0e31c0 .part L_0x55f30e0e20e0, 1, 1;
|
||||
L_0x55f30e0e32f0 .part L_0x55f30e0e57c0, 1, 1;
|
||||
L_0x55f30e0e3420 .part L_0x55f30e0eb900, 0, 1;
|
||||
L_0x55f30e0e38b0 .part L_0x55f30e0e20e0, 2, 1;
|
||||
L_0x55f30e0e3a20 .part L_0x55f30e0e57c0, 2, 1;
|
||||
L_0x55f30e0e3be0 .part L_0x55f30e0eb900, 1, 1;
|
||||
L_0x55f30e0e41c0 .part L_0x55f30e0e20e0, 3, 1;
|
||||
L_0x55f30e0e42f0 .part L_0x55f30e0e57c0, 3, 1;
|
||||
L_0x55f30e0e4480 .part L_0x55f30e0eb900, 2, 1;
|
||||
L_0x55f30e0e45b0 .concat8 [ 1 1 1 1], L_0x55f30e0e2a00, L_0x55f30e0e3090, L_0x55f30e0e3780, L_0x55f30e0e4030;
|
||||
L_0x55f30e0eb900 .concat [ 1 1 1 1], L_0x55f30e0e2b00, L_0x55f30e0e3150, L_0x55f30e0e3840, o0x7f5d7200bc28;
|
||||
S_0x55f30e0c8b60 .scope module, "f0" "fulladder" 4 11, 5 1 0, S_0x55f30e0c88c0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "Carry";
|
||||
.port_info 3 /OUTPUT 1 "Sum";
|
||||
.port_info 4 /OUTPUT 1 "CarryO";
|
||||
L_0x55f30e0e2b00 .functor OR 1, L_0x55f30e0e26e0, L_0x55f30e0e28b0, C4<0>, C4<0>;
|
||||
v0x55f30e0c99e0_0 .net "A", 0 0, L_0x55f30e0e2b70; 1 drivers
|
||||
v0x55f30e0c9aa0_0 .net "B", 0 0, L_0x55f30e0e2d30; 1 drivers
|
||||
v0x55f30e0c9b70_0 .net "Carry", 0 0, L_0x7f5d71fc0138; alias, 1 drivers
|
||||
v0x55f30e0c9c70_0 .net "CarryO", 0 0, L_0x55f30e0e2b00; 1 drivers
|
||||
v0x55f30e0c9d10_0 .net "Sum", 0 0, L_0x55f30e0e2a00; 1 drivers
|
||||
v0x55f30e0c9e00_0 .net "and1", 0 0, L_0x55f30e0e26e0; 1 drivers
|
||||
v0x55f30e0c9ed0_0 .net "and2", 0 0, L_0x55f30e0e28b0; 1 drivers
|
||||
v0x55f30e0c9fa0_0 .net "xor1", 0 0, L_0x55f30e0e2840; 1 drivers
|
||||
S_0x55f30e0c8d40 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55f30e0c8b60;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x55f30e0e26e0 .functor AND 1, L_0x55f30e0e2b70, L_0x55f30e0e2d30, C4<1>, C4<1>;
|
||||
L_0x55f30e0e2840 .functor XOR 1, L_0x55f30e0e2b70, L_0x55f30e0e2d30, C4<0>, C4<0>;
|
||||
v0x55f30e0c8fe0_0 .net "A", 0 0, L_0x55f30e0e2b70; alias, 1 drivers
|
||||
v0x55f30e0c90c0_0 .net "B", 0 0, L_0x55f30e0e2d30; alias, 1 drivers
|
||||
v0x55f30e0c9180_0 .net "Carry", 0 0, L_0x55f30e0e26e0; alias, 1 drivers
|
||||
v0x55f30e0c9250_0 .net "Sum", 0 0, L_0x55f30e0e2840; alias, 1 drivers
|
||||
S_0x55f30e0c93c0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55f30e0c8b60;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x55f30e0e28b0 .functor AND 1, L_0x55f30e0e2840, L_0x7f5d71fc0138, C4<1>, C4<1>;
|
||||
L_0x55f30e0e2a00 .functor XOR 1, L_0x55f30e0e2840, L_0x7f5d71fc0138, C4<0>, C4<0>;
|
||||
v0x55f30e0c9630_0 .net "A", 0 0, L_0x55f30e0e2840; alias, 1 drivers
|
||||
v0x55f30e0c9700_0 .net "B", 0 0, L_0x7f5d71fc0138; alias, 1 drivers
|
||||
v0x55f30e0c97a0_0 .net "Carry", 0 0, L_0x55f30e0e28b0; alias, 1 drivers
|
||||
v0x55f30e0c9870_0 .net "Sum", 0 0, L_0x55f30e0e2a00; alias, 1 drivers
|
||||
S_0x55f30e0ca090 .scope module, "f1" "fulladder" 4 12, 5 1 0, S_0x55f30e0c88c0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "Carry";
|
||||
.port_info 3 /OUTPUT 1 "Sum";
|
||||
.port_info 4 /OUTPUT 1 "CarryO";
|
||||
L_0x55f30e0e3150 .functor OR 1, L_0x55f30e0e2e60, L_0x55f30e0e2f40, C4<0>, C4<0>;
|
||||
v0x55f30e0caef0_0 .net "A", 0 0, L_0x55f30e0e31c0; 1 drivers
|
||||
v0x55f30e0cafb0_0 .net "B", 0 0, L_0x55f30e0e32f0; 1 drivers
|
||||
v0x55f30e0cb080_0 .net "Carry", 0 0, L_0x55f30e0e3420; 1 drivers
|
||||
v0x55f30e0cb180_0 .net "CarryO", 0 0, L_0x55f30e0e3150; 1 drivers
|
||||
v0x55f30e0cb220_0 .net "Sum", 0 0, L_0x55f30e0e3090; 1 drivers
|
||||
v0x55f30e0cb310_0 .net "and1", 0 0, L_0x55f30e0e2e60; 1 drivers
|
||||
v0x55f30e0cb3e0_0 .net "and2", 0 0, L_0x55f30e0e2f40; 1 drivers
|
||||
v0x55f30e0cb4b0_0 .net "xor1", 0 0, L_0x55f30e0e2ed0; 1 drivers
|
||||
S_0x55f30e0ca270 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55f30e0ca090;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x55f30e0e2e60 .functor AND 1, L_0x55f30e0e31c0, L_0x55f30e0e32f0, C4<1>, C4<1>;
|
||||
L_0x55f30e0e2ed0 .functor XOR 1, L_0x55f30e0e31c0, L_0x55f30e0e32f0, C4<0>, C4<0>;
|
||||
v0x55f30e0ca4f0_0 .net "A", 0 0, L_0x55f30e0e31c0; alias, 1 drivers
|
||||
v0x55f30e0ca5d0_0 .net "B", 0 0, L_0x55f30e0e32f0; alias, 1 drivers
|
||||
v0x55f30e0ca690_0 .net "Carry", 0 0, L_0x55f30e0e2e60; alias, 1 drivers
|
||||
v0x55f30e0ca760_0 .net "Sum", 0 0, L_0x55f30e0e2ed0; alias, 1 drivers
|
||||
S_0x55f30e0ca8d0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55f30e0ca090;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x55f30e0e2f40 .functor AND 1, L_0x55f30e0e2ed0, L_0x55f30e0e3420, C4<1>, C4<1>;
|
||||
L_0x55f30e0e3090 .functor XOR 1, L_0x55f30e0e2ed0, L_0x55f30e0e3420, C4<0>, C4<0>;
|
||||
v0x55f30e0cab40_0 .net "A", 0 0, L_0x55f30e0e2ed0; alias, 1 drivers
|
||||
v0x55f30e0cac10_0 .net "B", 0 0, L_0x55f30e0e3420; alias, 1 drivers
|
||||
v0x55f30e0cacb0_0 .net "Carry", 0 0, L_0x55f30e0e2f40; alias, 1 drivers
|
||||
v0x55f30e0cad80_0 .net "Sum", 0 0, L_0x55f30e0e3090; alias, 1 drivers
|
||||
S_0x55f30e0cb5a0 .scope module, "f2" "fulladder" 4 13, 5 1 0, S_0x55f30e0c88c0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "Carry";
|
||||
.port_info 3 /OUTPUT 1 "Sum";
|
||||
.port_info 4 /OUTPUT 1 "CarryO";
|
||||
L_0x55f30e0e3840 .functor OR 1, L_0x55f30e0e3550, L_0x55f30e0e3630, C4<0>, C4<0>;
|
||||
v0x55f30e0cc410_0 .net "A", 0 0, L_0x55f30e0e38b0; 1 drivers
|
||||
v0x55f30e0cc4d0_0 .net "B", 0 0, L_0x55f30e0e3a20; 1 drivers
|
||||
v0x55f30e0cc5a0_0 .net "Carry", 0 0, L_0x55f30e0e3be0; 1 drivers
|
||||
v0x55f30e0cc6a0_0 .net "CarryO", 0 0, L_0x55f30e0e3840; 1 drivers
|
||||
v0x55f30e0cc740_0 .net "Sum", 0 0, L_0x55f30e0e3780; 1 drivers
|
||||
v0x55f30e0cc830_0 .net "and1", 0 0, L_0x55f30e0e3550; 1 drivers
|
||||
v0x55f30e0cc900_0 .net "and2", 0 0, L_0x55f30e0e3630; 1 drivers
|
||||
v0x55f30e0cc9d0_0 .net "xor1", 0 0, L_0x55f30e0e35c0; 1 drivers
|
||||
S_0x55f30e0cb7b0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55f30e0cb5a0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x55f30e0e3550 .functor AND 1, L_0x55f30e0e38b0, L_0x55f30e0e3a20, C4<1>, C4<1>;
|
||||
L_0x55f30e0e35c0 .functor XOR 1, L_0x55f30e0e38b0, L_0x55f30e0e3a20, C4<0>, C4<0>;
|
||||
v0x55f30e0cba30_0 .net "A", 0 0, L_0x55f30e0e38b0; alias, 1 drivers
|
||||
v0x55f30e0cbaf0_0 .net "B", 0 0, L_0x55f30e0e3a20; alias, 1 drivers
|
||||
v0x55f30e0cbbb0_0 .net "Carry", 0 0, L_0x55f30e0e3550; alias, 1 drivers
|
||||
v0x55f30e0cbc80_0 .net "Sum", 0 0, L_0x55f30e0e35c0; alias, 1 drivers
|
||||
S_0x55f30e0cbdf0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55f30e0cb5a0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x55f30e0e3630 .functor AND 1, L_0x55f30e0e35c0, L_0x55f30e0e3be0, C4<1>, C4<1>;
|
||||
L_0x55f30e0e3780 .functor XOR 1, L_0x55f30e0e35c0, L_0x55f30e0e3be0, C4<0>, C4<0>;
|
||||
v0x55f30e0cc060_0 .net "A", 0 0, L_0x55f30e0e35c0; alias, 1 drivers
|
||||
v0x55f30e0cc130_0 .net "B", 0 0, L_0x55f30e0e3be0; alias, 1 drivers
|
||||
v0x55f30e0cc1d0_0 .net "Carry", 0 0, L_0x55f30e0e3630; alias, 1 drivers
|
||||
v0x55f30e0cc2a0_0 .net "Sum", 0 0, L_0x55f30e0e3780; alias, 1 drivers
|
||||
S_0x55f30e0ccac0 .scope module, "f3" "fulladder" 4 14, 5 1 0, S_0x55f30e0c88c0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "Carry";
|
||||
.port_info 3 /OUTPUT 1 "Sum";
|
||||
.port_info 4 /OUTPUT 1 "CarryO";
|
||||
L_0x55f30e0e4110 .functor OR 1, L_0x55f30e0e3d60, L_0x55f30e0e3ea0, C4<0>, C4<0>;
|
||||
v0x55f30e0cd920_0 .net "A", 0 0, L_0x55f30e0e41c0; 1 drivers
|
||||
v0x55f30e0cd9e0_0 .net "B", 0 0, L_0x55f30e0e42f0; 1 drivers
|
||||
v0x55f30e0cdab0_0 .net "Carry", 0 0, L_0x55f30e0e4480; 1 drivers
|
||||
v0x55f30e0cdbb0_0 .net "CarryO", 0 0, L_0x55f30e0e4110; alias, 1 drivers
|
||||
v0x55f30e0cdc50_0 .net "Sum", 0 0, L_0x55f30e0e4030; 1 drivers
|
||||
v0x55f30e0cdd40_0 .net "and1", 0 0, L_0x55f30e0e3d60; 1 drivers
|
||||
v0x55f30e0cde10_0 .net "and2", 0 0, L_0x55f30e0e3ea0; 1 drivers
|
||||
v0x55f30e0cdee0_0 .net "xor1", 0 0, L_0x55f30e0e3e10; 1 drivers
|
||||
S_0x55f30e0ccca0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55f30e0ccac0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x55f30e0e3d60 .functor AND 1, L_0x55f30e0e41c0, L_0x55f30e0e42f0, C4<1>, C4<1>;
|
||||
L_0x55f30e0e3e10 .functor XOR 1, L_0x55f30e0e41c0, L_0x55f30e0e42f0, C4<0>, C4<0>;
|
||||
v0x55f30e0ccf20_0 .net "A", 0 0, L_0x55f30e0e41c0; alias, 1 drivers
|
||||
v0x55f30e0cd000_0 .net "B", 0 0, L_0x55f30e0e42f0; alias, 1 drivers
|
||||
v0x55f30e0cd0c0_0 .net "Carry", 0 0, L_0x55f30e0e3d60; alias, 1 drivers
|
||||
v0x55f30e0cd190_0 .net "Sum", 0 0, L_0x55f30e0e3e10; alias, 1 drivers
|
||||
S_0x55f30e0cd300 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55f30e0ccac0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x55f30e0e3ea0 .functor AND 1, L_0x55f30e0e3e10, L_0x55f30e0e4480, C4<1>, C4<1>;
|
||||
L_0x55f30e0e4030 .functor XOR 1, L_0x55f30e0e3e10, L_0x55f30e0e4480, C4<0>, C4<0>;
|
||||
v0x55f30e0cd570_0 .net "A", 0 0, L_0x55f30e0e3e10; alias, 1 drivers
|
||||
v0x55f30e0cd640_0 .net "B", 0 0, L_0x55f30e0e4480; alias, 1 drivers
|
||||
v0x55f30e0cd6e0_0 .net "Carry", 0 0, L_0x55f30e0e3ea0; alias, 1 drivers
|
||||
v0x55f30e0cd7b0_0 .net "Sum", 0 0, L_0x55f30e0e4030; alias, 1 drivers
|
||||
S_0x55f30e0cdfd0 .scope module, "od1" "overflowDetect" 4 17, 7 1 0, S_0x55f30e0c88c0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 2 "opCode";
|
||||
.port_info 1 /INPUT 4 "A";
|
||||
.port_info 2 /INPUT 4 "B";
|
||||
.port_info 3 /INPUT 4 "Y";
|
||||
.port_info 4 /INPUT 1 "CarryOUT";
|
||||
.port_info 5 /OUTPUT 1 "overflowDetect";
|
||||
L_0x55f30e0e46c0 .functor OR 1, L_0x55f30e0e4750, L_0x55f30e0e47f0, C4<0>, C4<0>;
|
||||
L_0x55f30e0e4890 .functor XNOR 1, L_0x55f30e0e4900, L_0x55f30e0e4b00, C4<0>, C4<0>;
|
||||
L_0x55f30e0e4bf0 .functor XOR 1, L_0x55f30e0e4c60, L_0x55f30e0e4d50, C4<0>, C4<0>;
|
||||
L_0x55f30e0e4e80 .functor XOR 1, L_0x55f30e0e4ef0, L_0x55f30e0e4fe0, C4<0>, C4<0>;
|
||||
L_0x55f30e0e5120 .functor AND 1, L_0x55f30e0e4890, L_0x55f30e0e51e0, C4<1>, C4<1>;
|
||||
L_0x55f30e0e52d0 .functor AND 1, L_0x55f30e0e4bf0, L_0x55f30e0e5390, C4<1>, C4<1>;
|
||||
L_0x55f30e0e54e0 .functor OR 1, L_0x55f30e0e5120, L_0x55f30e0e52d0, C4<0>, C4<0>;
|
||||
L_0x55f30e0e5550 .functor AND 1, L_0x55f30e0e54e0, L_0x55f30e0e4e80, C4<1>, C4<1>;
|
||||
L_0x55f30e0e56b0 .functor AND 1, L_0x55f30e0e46c0, L_0x55f30e0e5550, C4<1>, C4<1>;
|
||||
v0x55f30e0ce2a0_0 .net "A", 3 0, L_0x55f30e0e20e0; alias, 1 drivers
|
||||
v0x55f30e0ce380_0 .net "B", 3 0, L_0x55f30e0e57c0; alias, 1 drivers
|
||||
v0x55f30e0ce460_0 .net "CarryOUT", 0 0, L_0x55f30e0e4110; alias, 1 drivers
|
||||
v0x55f30e0ce500_0 .net "Y", 3 0, L_0x55f30e0e45b0; alias, 1 drivers
|
||||
v0x55f30e0ce5a0_0 .net *"_ivl_1", 0 0, L_0x55f30e0e4750; 1 drivers
|
||||
v0x55f30e0ce6d0_0 .net *"_ivl_11", 0 0, L_0x55f30e0e4d50; 1 drivers
|
||||
v0x55f30e0ce7b0_0 .net *"_ivl_13", 0 0, L_0x55f30e0e4ef0; 1 drivers
|
||||
v0x55f30e0ce890_0 .net *"_ivl_15", 0 0, L_0x55f30e0e4fe0; 1 drivers
|
||||
v0x55f30e0ce970_0 .net *"_ivl_17", 0 0, L_0x55f30e0e51e0; 1 drivers
|
||||
v0x55f30e0cea50_0 .net *"_ivl_19", 0 0, L_0x55f30e0e5390; 1 drivers
|
||||
v0x55f30e0ceb30_0 .net *"_ivl_3", 0 0, L_0x55f30e0e47f0; 1 drivers
|
||||
v0x55f30e0cec10_0 .net *"_ivl_5", 0 0, L_0x55f30e0e4900; 1 drivers
|
||||
v0x55f30e0cecf0_0 .net *"_ivl_7", 0 0, L_0x55f30e0e4b00; 1 drivers
|
||||
v0x55f30e0cedd0_0 .net *"_ivl_9", 0 0, L_0x55f30e0e4c60; 1 drivers
|
||||
v0x55f30e0ceeb0_0 .net "addOverflow", 0 0, L_0x55f30e0e5120; 1 drivers
|
||||
v0x55f30e0cef70_0 .net "detect1", 0 0, L_0x55f30e0e54e0; 1 drivers
|
||||
v0x55f30e0cf030_0 .net "detect2", 0 0, L_0x55f30e0e5550; 1 drivers
|
||||
v0x55f30e0cf0f0_0 .net "opC", 0 0, L_0x55f30e0e46c0; 1 drivers
|
||||
L_0x7f5d71fc00f0 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55f30e0cf1b0_0 .net "opCode", 1 0, L_0x7f5d71fc00f0; 1 drivers
|
||||
v0x55f30e0cf290_0 .net "overflowDetect", 0 0, L_0x55f30e0e56b0; alias, 1 drivers
|
||||
v0x55f30e0cf350_0 .net "sign1", 0 0, L_0x55f30e0e4890; 1 drivers
|
||||
v0x55f30e0cf410_0 .net "sign2", 0 0, L_0x55f30e0e4e80; 1 drivers
|
||||
v0x55f30e0cf4d0_0 .net "sign3", 0 0, L_0x55f30e0e4bf0; 1 drivers
|
||||
v0x55f30e0cf590_0 .net "subOverflow", 0 0, L_0x55f30e0e52d0; 1 drivers
|
||||
L_0x55f30e0e4750 .part L_0x7f5d71fc00f0, 0, 1;
|
||||
L_0x55f30e0e47f0 .part L_0x7f5d71fc00f0, 1, 1;
|
||||
L_0x55f30e0e4900 .part L_0x55f30e0e20e0, 3, 1;
|
||||
L_0x55f30e0e4b00 .part L_0x55f30e0e57c0, 3, 1;
|
||||
L_0x55f30e0e4c60 .part L_0x55f30e0e20e0, 3, 1;
|
||||
L_0x55f30e0e4d50 .part L_0x55f30e0e57c0, 3, 1;
|
||||
L_0x55f30e0e4ef0 .part L_0x55f30e0e45b0, 3, 1;
|
||||
L_0x55f30e0e4fe0 .part L_0x55f30e0e20e0, 3, 1;
|
||||
L_0x55f30e0e51e0 .part L_0x7f5d71fc00f0, 0, 1;
|
||||
L_0x55f30e0e5390 .part L_0x7f5d71fc00f0, 1, 1;
|
||||
S_0x55f30e0cfe30 .scope module, "add2" "addition" 3 58, 4 1 0, S_0x55f30e070c90;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 4 "A";
|
||||
.port_info 1 /INPUT 4 "B";
|
||||
.port_info 2 /INPUT 1 "CarryIN";
|
||||
.port_info 3 /OUTPUT 4 "Y";
|
||||
.port_info 4 /OUTPUT 1 "CarryOUT";
|
||||
.port_info 5 /OUTPUT 1 "overflow";
|
||||
v0x55f30e0d6fe0_0 .net "A", 3 0, L_0x55f30e0e6160; alias, 1 drivers
|
||||
v0x55f30e0d70c0_0 .net "B", 3 0, L_0x55f30e0e9c70; 1 drivers
|
||||
v0x55f30e0d7190_0 .net "Carry4", 3 0, L_0x55f30e0ebad0; 1 drivers
|
||||
L_0x7f5d71fc01c8 .functor BUFT 1, C4<0>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55f30e0d7260_0 .net "CarryIN", 0 0, L_0x7f5d71fc01c8; 1 drivers
|
||||
v0x55f30e0d7300_0 .net "CarryOUT", 0 0, L_0x55f30e0e8710; 1 drivers
|
||||
v0x55f30e0d7440_0 .net "Y", 3 0, L_0x55f30e0e8bb0; 1 drivers
|
||||
o0x7f5d7200d2d8 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
; Elide local net with no drivers, v0x55f30e0d7500_0 name=_ivl_41
|
||||
v0x55f30e0d75c0_0 .net "overflow", 0 0, L_0x55f30e0e9b60; alias, 1 drivers
|
||||
L_0x55f30e0e71b0 .part L_0x55f30e0e6160, 0, 1;
|
||||
L_0x55f30e0e7370 .part L_0x55f30e0e9c70, 0, 1;
|
||||
L_0x55f30e0e7800 .part L_0x55f30e0e6160, 1, 1;
|
||||
L_0x55f30e0e7930 .part L_0x55f30e0e9c70, 1, 1;
|
||||
L_0x55f30e0e7a60 .part L_0x55f30e0ebad0, 0, 1;
|
||||
L_0x55f30e0e7ef0 .part L_0x55f30e0e6160, 2, 1;
|
||||
L_0x55f30e0e8020 .part L_0x55f30e0e9c70, 2, 1;
|
||||
L_0x55f30e0e81e0 .part L_0x55f30e0ebad0, 1, 1;
|
||||
L_0x55f30e0e87c0 .part L_0x55f30e0e6160, 3, 1;
|
||||
L_0x55f30e0e88f0 .part L_0x55f30e0e9c70, 3, 1;
|
||||
L_0x55f30e0e8a80 .part L_0x55f30e0ebad0, 2, 1;
|
||||
L_0x55f30e0e8bb0 .concat8 [ 1 1 1 1], L_0x55f30e0e7040, L_0x55f30e0e76d0, L_0x55f30e0e7dc0, L_0x55f30e0e8630;
|
||||
L_0x55f30e0ebad0 .concat [ 1 1 1 1], L_0x55f30e0e7140, L_0x55f30e0e7790, L_0x55f30e0e7e80, o0x7f5d7200d2d8;
|
||||
S_0x55f30e0d00b0 .scope module, "f0" "fulladder" 4 11, 5 1 0, S_0x55f30e0cfe30;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "Carry";
|
||||
.port_info 3 /OUTPUT 1 "Sum";
|
||||
.port_info 4 /OUTPUT 1 "CarryO";
|
||||
L_0x55f30e0e7140 .functor OR 1, L_0x55f30e0e6d20, L_0x55f30e0e6ef0, C4<0>, C4<0>;
|
||||
v0x55f30e0d0fe0_0 .net "A", 0 0, L_0x55f30e0e71b0; 1 drivers
|
||||
v0x55f30e0d10a0_0 .net "B", 0 0, L_0x55f30e0e7370; 1 drivers
|
||||
v0x55f30e0d1170_0 .net "Carry", 0 0, L_0x7f5d71fc01c8; alias, 1 drivers
|
||||
v0x55f30e0d1270_0 .net "CarryO", 0 0, L_0x55f30e0e7140; 1 drivers
|
||||
v0x55f30e0d1310_0 .net "Sum", 0 0, L_0x55f30e0e7040; 1 drivers
|
||||
v0x55f30e0d1400_0 .net "and1", 0 0, L_0x55f30e0e6d20; 1 drivers
|
||||
v0x55f30e0d14d0_0 .net "and2", 0 0, L_0x55f30e0e6ef0; 1 drivers
|
||||
v0x55f30e0d15a0_0 .net "xor1", 0 0, L_0x55f30e0e6e80; 1 drivers
|
||||
S_0x55f30e0d0340 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55f30e0d00b0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x55f30e0e6d20 .functor AND 1, L_0x55f30e0e71b0, L_0x55f30e0e7370, C4<1>, C4<1>;
|
||||
L_0x55f30e0e6e80 .functor XOR 1, L_0x55f30e0e71b0, L_0x55f30e0e7370, C4<0>, C4<0>;
|
||||
v0x55f30e0d05e0_0 .net "A", 0 0, L_0x55f30e0e71b0; alias, 1 drivers
|
||||
v0x55f30e0d06c0_0 .net "B", 0 0, L_0x55f30e0e7370; alias, 1 drivers
|
||||
v0x55f30e0d0780_0 .net "Carry", 0 0, L_0x55f30e0e6d20; alias, 1 drivers
|
||||
v0x55f30e0d0850_0 .net "Sum", 0 0, L_0x55f30e0e6e80; alias, 1 drivers
|
||||
S_0x55f30e0d09c0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55f30e0d00b0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x55f30e0e6ef0 .functor AND 1, L_0x55f30e0e6e80, L_0x7f5d71fc01c8, C4<1>, C4<1>;
|
||||
L_0x55f30e0e7040 .functor XOR 1, L_0x55f30e0e6e80, L_0x7f5d71fc01c8, C4<0>, C4<0>;
|
||||
v0x55f30e0d0c30_0 .net "A", 0 0, L_0x55f30e0e6e80; alias, 1 drivers
|
||||
v0x55f30e0d0d00_0 .net "B", 0 0, L_0x7f5d71fc01c8; alias, 1 drivers
|
||||
v0x55f30e0d0da0_0 .net "Carry", 0 0, L_0x55f30e0e6ef0; alias, 1 drivers
|
||||
v0x55f30e0d0e70_0 .net "Sum", 0 0, L_0x55f30e0e7040; alias, 1 drivers
|
||||
S_0x55f30e0d1690 .scope module, "f1" "fulladder" 4 12, 5 1 0, S_0x55f30e0cfe30;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "Carry";
|
||||
.port_info 3 /OUTPUT 1 "Sum";
|
||||
.port_info 4 /OUTPUT 1 "CarryO";
|
||||
L_0x55f30e0e7790 .functor OR 1, L_0x55f30e0e74a0, L_0x55f30e0e7580, C4<0>, C4<0>;
|
||||
v0x55f30e0d2570_0 .net "A", 0 0, L_0x55f30e0e7800; 1 drivers
|
||||
v0x55f30e0d2630_0 .net "B", 0 0, L_0x55f30e0e7930; 1 drivers
|
||||
v0x55f30e0d2700_0 .net "Carry", 0 0, L_0x55f30e0e7a60; 1 drivers
|
||||
v0x55f30e0d2800_0 .net "CarryO", 0 0, L_0x55f30e0e7790; 1 drivers
|
||||
v0x55f30e0d28a0_0 .net "Sum", 0 0, L_0x55f30e0e76d0; 1 drivers
|
||||
v0x55f30e0d2990_0 .net "and1", 0 0, L_0x55f30e0e74a0; 1 drivers
|
||||
v0x55f30e0d2a60_0 .net "and2", 0 0, L_0x55f30e0e7580; 1 drivers
|
||||
v0x55f30e0d2b30_0 .net "xor1", 0 0, L_0x55f30e0e7510; 1 drivers
|
||||
S_0x55f30e0d18f0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55f30e0d1690;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x55f30e0e74a0 .functor AND 1, L_0x55f30e0e7800, L_0x55f30e0e7930, C4<1>, C4<1>;
|
||||
L_0x55f30e0e7510 .functor XOR 1, L_0x55f30e0e7800, L_0x55f30e0e7930, C4<0>, C4<0>;
|
||||
v0x55f30e0d1b70_0 .net "A", 0 0, L_0x55f30e0e7800; alias, 1 drivers
|
||||
v0x55f30e0d1c50_0 .net "B", 0 0, L_0x55f30e0e7930; alias, 1 drivers
|
||||
v0x55f30e0d1d10_0 .net "Carry", 0 0, L_0x55f30e0e74a0; alias, 1 drivers
|
||||
v0x55f30e0d1de0_0 .net "Sum", 0 0, L_0x55f30e0e7510; alias, 1 drivers
|
||||
S_0x55f30e0d1f50 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55f30e0d1690;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x55f30e0e7580 .functor AND 1, L_0x55f30e0e7510, L_0x55f30e0e7a60, C4<1>, C4<1>;
|
||||
L_0x55f30e0e76d0 .functor XOR 1, L_0x55f30e0e7510, L_0x55f30e0e7a60, C4<0>, C4<0>;
|
||||
v0x55f30e0d21c0_0 .net "A", 0 0, L_0x55f30e0e7510; alias, 1 drivers
|
||||
v0x55f30e0d2290_0 .net "B", 0 0, L_0x55f30e0e7a60; alias, 1 drivers
|
||||
v0x55f30e0d2330_0 .net "Carry", 0 0, L_0x55f30e0e7580; alias, 1 drivers
|
||||
v0x55f30e0d2400_0 .net "Sum", 0 0, L_0x55f30e0e76d0; alias, 1 drivers
|
||||
S_0x55f30e0d2c20 .scope module, "f2" "fulladder" 4 13, 5 1 0, S_0x55f30e0cfe30;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "Carry";
|
||||
.port_info 3 /OUTPUT 1 "Sum";
|
||||
.port_info 4 /OUTPUT 1 "CarryO";
|
||||
L_0x55f30e0e7e80 .functor OR 1, L_0x55f30e0e7b90, L_0x55f30e0e7c70, C4<0>, C4<0>;
|
||||
v0x55f30e0d3b10_0 .net "A", 0 0, L_0x55f30e0e7ef0; 1 drivers
|
||||
v0x55f30e0d3bd0_0 .net "B", 0 0, L_0x55f30e0e8020; 1 drivers
|
||||
v0x55f30e0d3ca0_0 .net "Carry", 0 0, L_0x55f30e0e81e0; 1 drivers
|
||||
v0x55f30e0d3da0_0 .net "CarryO", 0 0, L_0x55f30e0e7e80; 1 drivers
|
||||
v0x55f30e0d3e40_0 .net "Sum", 0 0, L_0x55f30e0e7dc0; 1 drivers
|
||||
v0x55f30e0d3f30_0 .net "and1", 0 0, L_0x55f30e0e7b90; 1 drivers
|
||||
v0x55f30e0d4000_0 .net "and2", 0 0, L_0x55f30e0e7c70; 1 drivers
|
||||
v0x55f30e0d40d0_0 .net "xor1", 0 0, L_0x55f30e0e7c00; 1 drivers
|
||||
S_0x55f30e0d2eb0 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55f30e0d2c20;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x55f30e0e7b90 .functor AND 1, L_0x55f30e0e7ef0, L_0x55f30e0e8020, C4<1>, C4<1>;
|
||||
L_0x55f30e0e7c00 .functor XOR 1, L_0x55f30e0e7ef0, L_0x55f30e0e8020, C4<0>, C4<0>;
|
||||
v0x55f30e0d3130_0 .net "A", 0 0, L_0x55f30e0e7ef0; alias, 1 drivers
|
||||
v0x55f30e0d31f0_0 .net "B", 0 0, L_0x55f30e0e8020; alias, 1 drivers
|
||||
v0x55f30e0d32b0_0 .net "Carry", 0 0, L_0x55f30e0e7b90; alias, 1 drivers
|
||||
v0x55f30e0d3380_0 .net "Sum", 0 0, L_0x55f30e0e7c00; alias, 1 drivers
|
||||
S_0x55f30e0d34f0 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55f30e0d2c20;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x55f30e0e7c70 .functor AND 1, L_0x55f30e0e7c00, L_0x55f30e0e81e0, C4<1>, C4<1>;
|
||||
L_0x55f30e0e7dc0 .functor XOR 1, L_0x55f30e0e7c00, L_0x55f30e0e81e0, C4<0>, C4<0>;
|
||||
v0x55f30e0d3760_0 .net "A", 0 0, L_0x55f30e0e7c00; alias, 1 drivers
|
||||
v0x55f30e0d3830_0 .net "B", 0 0, L_0x55f30e0e81e0; alias, 1 drivers
|
||||
v0x55f30e0d38d0_0 .net "Carry", 0 0, L_0x55f30e0e7c70; alias, 1 drivers
|
||||
v0x55f30e0d39a0_0 .net "Sum", 0 0, L_0x55f30e0e7dc0; alias, 1 drivers
|
||||
S_0x55f30e0d41c0 .scope module, "f3" "fulladder" 4 14, 5 1 0, S_0x55f30e0cfe30;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "Carry";
|
||||
.port_info 3 /OUTPUT 1 "Sum";
|
||||
.port_info 4 /OUTPUT 1 "CarryO";
|
||||
L_0x55f30e0e8710 .functor OR 1, L_0x55f30e0e8360, L_0x55f30e0e84a0, C4<0>, C4<0>;
|
||||
v0x55f30e0d50a0_0 .net "A", 0 0, L_0x55f30e0e87c0; 1 drivers
|
||||
v0x55f30e0d5160_0 .net "B", 0 0, L_0x55f30e0e88f0; 1 drivers
|
||||
v0x55f30e0d5230_0 .net "Carry", 0 0, L_0x55f30e0e8a80; 1 drivers
|
||||
v0x55f30e0d5330_0 .net "CarryO", 0 0, L_0x55f30e0e8710; alias, 1 drivers
|
||||
v0x55f30e0d53d0_0 .net "Sum", 0 0, L_0x55f30e0e8630; 1 drivers
|
||||
v0x55f30e0d54c0_0 .net "and1", 0 0, L_0x55f30e0e8360; 1 drivers
|
||||
v0x55f30e0d5590_0 .net "and2", 0 0, L_0x55f30e0e84a0; 1 drivers
|
||||
v0x55f30e0d5660_0 .net "xor1", 0 0, L_0x55f30e0e8410; 1 drivers
|
||||
S_0x55f30e0d4420 .scope module, "h1" "halfadder" 5 8, 6 1 0, S_0x55f30e0d41c0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x55f30e0e8360 .functor AND 1, L_0x55f30e0e87c0, L_0x55f30e0e88f0, C4<1>, C4<1>;
|
||||
L_0x55f30e0e8410 .functor XOR 1, L_0x55f30e0e87c0, L_0x55f30e0e88f0, C4<0>, C4<0>;
|
||||
v0x55f30e0d46a0_0 .net "A", 0 0, L_0x55f30e0e87c0; alias, 1 drivers
|
||||
v0x55f30e0d4780_0 .net "B", 0 0, L_0x55f30e0e88f0; alias, 1 drivers
|
||||
v0x55f30e0d4840_0 .net "Carry", 0 0, L_0x55f30e0e8360; alias, 1 drivers
|
||||
v0x55f30e0d4910_0 .net "Sum", 0 0, L_0x55f30e0e8410; alias, 1 drivers
|
||||
S_0x55f30e0d4a80 .scope module, "h2" "halfadder" 5 9, 6 1 0, S_0x55f30e0d41c0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Sum";
|
||||
.port_info 3 /OUTPUT 1 "Carry";
|
||||
L_0x55f30e0e84a0 .functor AND 1, L_0x55f30e0e8410, L_0x55f30e0e8a80, C4<1>, C4<1>;
|
||||
L_0x55f30e0e8630 .functor XOR 1, L_0x55f30e0e8410, L_0x55f30e0e8a80, C4<0>, C4<0>;
|
||||
v0x55f30e0d4cf0_0 .net "A", 0 0, L_0x55f30e0e8410; alias, 1 drivers
|
||||
v0x55f30e0d4dc0_0 .net "B", 0 0, L_0x55f30e0e8a80; alias, 1 drivers
|
||||
v0x55f30e0d4e60_0 .net "Carry", 0 0, L_0x55f30e0e84a0; alias, 1 drivers
|
||||
v0x55f30e0d4f30_0 .net "Sum", 0 0, L_0x55f30e0e8630; alias, 1 drivers
|
||||
S_0x55f30e0d5750 .scope module, "od1" "overflowDetect" 4 17, 7 1 0, S_0x55f30e0cfe30;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 2 "opCode";
|
||||
.port_info 1 /INPUT 4 "A";
|
||||
.port_info 2 /INPUT 4 "B";
|
||||
.port_info 3 /INPUT 4 "Y";
|
||||
.port_info 4 /INPUT 1 "CarryOUT";
|
||||
.port_info 5 /OUTPUT 1 "overflowDetect";
|
||||
L_0x55f30e0e8cc0 .functor OR 1, L_0x55f30e0e8d50, L_0x55f30e0e8df0, C4<0>, C4<0>;
|
||||
L_0x55f30e0e8e90 .functor XNOR 1, L_0x55f30e0e8f00, L_0x55f30e0e8ff0, C4<0>, C4<0>;
|
||||
L_0x55f30e0e90e0 .functor XOR 1, L_0x55f30e0e9150, L_0x55f30e0e9240, C4<0>, C4<0>;
|
||||
L_0x55f30e0e9330 .functor XOR 1, L_0x55f30e0e93a0, L_0x55f30e0e9490, C4<0>, C4<0>;
|
||||
L_0x55f30e0e95d0 .functor AND 1, L_0x55f30e0e8e90, L_0x55f30e0e9690, C4<1>, C4<1>;
|
||||
L_0x55f30e0e9780 .functor AND 1, L_0x55f30e0e90e0, L_0x55f30e0e9840, C4<1>, C4<1>;
|
||||
L_0x55f30e0e9990 .functor OR 1, L_0x55f30e0e95d0, L_0x55f30e0e9780, C4<0>, C4<0>;
|
||||
L_0x55f30e0e9a00 .functor AND 1, L_0x55f30e0e9990, L_0x55f30e0e9330, C4<1>, C4<1>;
|
||||
L_0x55f30e0e9b60 .functor AND 1, L_0x55f30e0e8cc0, L_0x55f30e0e9a00, C4<1>, C4<1>;
|
||||
v0x55f30e0d5a20_0 .net "A", 3 0, L_0x55f30e0e6160; alias, 1 drivers
|
||||
v0x55f30e0d5b00_0 .net "B", 3 0, L_0x55f30e0e9c70; alias, 1 drivers
|
||||
v0x55f30e0d5be0_0 .net "CarryOUT", 0 0, L_0x55f30e0e8710; alias, 1 drivers
|
||||
v0x55f30e0d5c80_0 .net "Y", 3 0, L_0x55f30e0e8bb0; alias, 1 drivers
|
||||
v0x55f30e0d5d20_0 .net *"_ivl_1", 0 0, L_0x55f30e0e8d50; 1 drivers
|
||||
v0x55f30e0d5e50_0 .net *"_ivl_11", 0 0, L_0x55f30e0e9240; 1 drivers
|
||||
v0x55f30e0d5f30_0 .net *"_ivl_13", 0 0, L_0x55f30e0e93a0; 1 drivers
|
||||
v0x55f30e0d6010_0 .net *"_ivl_15", 0 0, L_0x55f30e0e9490; 1 drivers
|
||||
v0x55f30e0d60f0_0 .net *"_ivl_17", 0 0, L_0x55f30e0e9690; 1 drivers
|
||||
v0x55f30e0d61d0_0 .net *"_ivl_19", 0 0, L_0x55f30e0e9840; 1 drivers
|
||||
v0x55f30e0d62b0_0 .net *"_ivl_3", 0 0, L_0x55f30e0e8df0; 1 drivers
|
||||
v0x55f30e0d6390_0 .net *"_ivl_5", 0 0, L_0x55f30e0e8f00; 1 drivers
|
||||
v0x55f30e0d6470_0 .net *"_ivl_7", 0 0, L_0x55f30e0e8ff0; 1 drivers
|
||||
v0x55f30e0d6550_0 .net *"_ivl_9", 0 0, L_0x55f30e0e9150; 1 drivers
|
||||
v0x55f30e0d6630_0 .net "addOverflow", 0 0, L_0x55f30e0e95d0; 1 drivers
|
||||
v0x55f30e0d66f0_0 .net "detect1", 0 0, L_0x55f30e0e9990; 1 drivers
|
||||
v0x55f30e0d67b0_0 .net "detect2", 0 0, L_0x55f30e0e9a00; 1 drivers
|
||||
v0x55f30e0d6980_0 .net "opC", 0 0, L_0x55f30e0e8cc0; 1 drivers
|
||||
L_0x7f5d71fc0180 .functor BUFT 1, C4<01>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55f30e0d6a40_0 .net "opCode", 1 0, L_0x7f5d71fc0180; 1 drivers
|
||||
v0x55f30e0d6b20_0 .net "overflowDetect", 0 0, L_0x55f30e0e9b60; alias, 1 drivers
|
||||
v0x55f30e0d6be0_0 .net "sign1", 0 0, L_0x55f30e0e8e90; 1 drivers
|
||||
v0x55f30e0d6ca0_0 .net "sign2", 0 0, L_0x55f30e0e9330; 1 drivers
|
||||
v0x55f30e0d6d60_0 .net "sign3", 0 0, L_0x55f30e0e90e0; 1 drivers
|
||||
v0x55f30e0d6e20_0 .net "subOverflow", 0 0, L_0x55f30e0e9780; 1 drivers
|
||||
L_0x55f30e0e8d50 .part L_0x7f5d71fc0180, 0, 1;
|
||||
L_0x55f30e0e8df0 .part L_0x7f5d71fc0180, 1, 1;
|
||||
L_0x55f30e0e8f00 .part L_0x55f30e0e6160, 3, 1;
|
||||
L_0x55f30e0e8ff0 .part L_0x55f30e0e9c70, 3, 1;
|
||||
L_0x55f30e0e9150 .part L_0x55f30e0e6160, 3, 1;
|
||||
L_0x55f30e0e9240 .part L_0x55f30e0e9c70, 3, 1;
|
||||
L_0x55f30e0e93a0 .part L_0x55f30e0e8bb0, 3, 1;
|
||||
L_0x55f30e0e9490 .part L_0x55f30e0e6160, 3, 1;
|
||||
L_0x55f30e0e9690 .part L_0x7f5d71fc0180, 0, 1;
|
||||
L_0x55f30e0e9840 .part L_0x7f5d71fc0180, 1, 1;
|
||||
.scope S_0x55f30e07afd0;
|
||||
T_0 ;
|
||||
%vpi_call 2 12 "$dumpfile", "multiplier.vcd" {0 0 0};
|
||||
%vpi_call 2 13 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 4;
|
||||
%store/vec4 v0x55f30e0dc920_0, 0, 4;
|
||||
%pushi/vec4 0, 0, 4;
|
||||
%store/vec4 v0x55f30e0dc9e0_0, 0, 4;
|
||||
%delay 2, 0;
|
||||
%pushi/vec4 0, 0, 4;
|
||||
%store/vec4 v0x55f30e0dc920_0, 0, 4;
|
||||
%pushi/vec4 8, 0, 4;
|
||||
%store/vec4 v0x55f30e0dc9e0_0, 0, 4;
|
||||
%delay 2, 0;
|
||||
%pushi/vec4 8, 0, 4;
|
||||
%store/vec4 v0x55f30e0dc920_0, 0, 4;
|
||||
%pushi/vec4 8, 0, 4;
|
||||
%store/vec4 v0x55f30e0dc9e0_0, 0, 4;
|
||||
%delay 2, 0;
|
||||
%pushi/vec4 7, 0, 4;
|
||||
%store/vec4 v0x55f30e0dc920_0, 0, 4;
|
||||
%pushi/vec4 7, 0, 4;
|
||||
%store/vec4 v0x55f30e0dc9e0_0, 0, 4;
|
||||
%delay 2, 0;
|
||||
%pushi/vec4 15, 0, 4;
|
||||
%store/vec4 v0x55f30e0dc920_0, 0, 4;
|
||||
%pushi/vec4 15, 0, 4;
|
||||
%store/vec4 v0x55f30e0dc9e0_0, 0, 4;
|
||||
%delay 2, 0;
|
||||
%vpi_call 2 19 "$finish" {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 8;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"multiplierTB.v";
|
||||
"multiplier.v";
|
||||
"addition.v";
|
||||
"fulladder.v";
|
||||
"halfadder.v";
|
||||
"overflowDetect.v";
|
||||
76
project0.2/multiplier.v
Normal file
76
project0.2/multiplier.v
Normal file
@@ -0,0 +1,76 @@
|
||||
module multiplier (
|
||||
input [3:0] A, B,
|
||||
output [7:0] Y
|
||||
);
|
||||
|
||||
wire [3:0] b0, a0, a1, a2;
|
||||
wire [4:0] S0, S1, S2;
|
||||
wire carry0, carry1, carry2;
|
||||
wire overflow0, overflow1, overflow2;
|
||||
|
||||
// Partial product generation
|
||||
and (Y[0], A[0], B[0]); // LSB of the result
|
||||
|
||||
// Generate partial products for B[0] and B[1]
|
||||
and ab00 (b0[0], A[1], B[0]);
|
||||
and ab01 (b0[1], A[2], B[0]);
|
||||
and ab02 (b0[2], A[3], B[0]);
|
||||
not ab03 (b0[3], 1'b1); // Initialize b0[3] to 0
|
||||
|
||||
and aa00 (a0[0], A[0], B[1]);
|
||||
and aa01 (a0[1], A[1], B[1]);
|
||||
and aa02 (a0[2], A[2], B[1]);
|
||||
and aa03 (a0[3], A[3], B[1]);
|
||||
|
||||
// First addition
|
||||
addition add0 (
|
||||
.A(a0),
|
||||
.B(b0),
|
||||
.CarryIN(1'b0),
|
||||
.Y(S0[3:0]),
|
||||
.CarryOUT(S0[4]),
|
||||
.overflow(overflow0)
|
||||
);
|
||||
|
||||
// Generate partial products for B[2]
|
||||
and aa10 (a1[0], A[0], B[2]);
|
||||
and aa11 (a1[1], A[1], B[2]);
|
||||
and aa12 (a1[2], A[2], B[2]);
|
||||
and aa13 (a1[3], A[3], B[2]);
|
||||
|
||||
// Second addition
|
||||
addition add1 (
|
||||
.A(a1),
|
||||
.B(S0[4:1]),
|
||||
.CarryIN(1'b0),
|
||||
.Y(S1[3:0]),
|
||||
.CarryOUT(S1[4]),
|
||||
.overflow(overflow1)
|
||||
);
|
||||
|
||||
// Generate partial products for B[3]
|
||||
and aa20 (a2[0], A[0], B[3]);
|
||||
and aa21 (a2[1], A[1], B[3]);
|
||||
and aa22 (a2[2], A[2], B[3]);
|
||||
and aa23 (a2[3], A[3], B[3]);
|
||||
|
||||
// Third addition
|
||||
addition add2 (
|
||||
.A(a2),
|
||||
.B(S1[4:1]),
|
||||
.CarryIN(1'b0),
|
||||
.Y(S2[3:0]),
|
||||
.CarryOUT(S2[4]),
|
||||
.overflow(overflow2)
|
||||
);
|
||||
|
||||
// Combine results into the final output Y
|
||||
or o01 (Y[1], S0[0], 1'b0);
|
||||
or o02 (Y[2], S1[0], 1'b0);
|
||||
or o03 (Y[3], S2[0], 1'b0);
|
||||
or o04 (Y[4], S2[1], 1'b0);
|
||||
or o05 (Y[5], S2[2], 1'b0);
|
||||
or o06 (Y[6], S2[3], 1'b0);
|
||||
or o07 (Y[7], S2[4], 1'b0);
|
||||
|
||||
endmodule
|
||||
769
project0.2/multiplier.vcd
Normal file
769
project0.2/multiplier.vcd
Normal file
@@ -0,0 +1,769 @@
|
||||
$date
|
||||
Fri Dec 20 19:46:49 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module multiplierTB $end
|
||||
$var wire 8 ! Y [7:0] $end
|
||||
$var reg 4 " A [3:0] $end
|
||||
$var reg 4 # B [3:0] $end
|
||||
$scope module uut $end
|
||||
$var wire 4 $ A [3:0] $end
|
||||
$var wire 4 % B [3:0] $end
|
||||
$var wire 1 & overflow2 $end
|
||||
$var wire 1 ' overflow1 $end
|
||||
$var wire 1 ( overflow0 $end
|
||||
$var wire 4 ) b0 [3:0] $end
|
||||
$var wire 4 * a2 [3:0] $end
|
||||
$var wire 4 + a1 [3:0] $end
|
||||
$var wire 4 , a0 [3:0] $end
|
||||
$var wire 8 - Y [7:0] $end
|
||||
$var wire 5 . S2 [4:0] $end
|
||||
$var wire 5 / S1 [4:0] $end
|
||||
$var wire 5 0 S0 [4:0] $end
|
||||
$scope module add0 $end
|
||||
$var wire 4 1 A [3:0] $end
|
||||
$var wire 4 2 B [3:0] $end
|
||||
$var wire 1 3 CarryIN $end
|
||||
$var wire 1 ( overflow $end
|
||||
$var wire 4 4 Y [3:0] $end
|
||||
$var wire 1 5 CarryOUT $end
|
||||
$var wire 4 6 Carry4 [3:0] $end
|
||||
$scope module f0 $end
|
||||
$var wire 1 7 A $end
|
||||
$var wire 1 8 B $end
|
||||
$var wire 1 3 Carry $end
|
||||
$var wire 1 9 CarryO $end
|
||||
$var wire 1 : xor1 $end
|
||||
$var wire 1 ; and2 $end
|
||||
$var wire 1 < and1 $end
|
||||
$var wire 1 = Sum $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 7 A $end
|
||||
$var wire 1 8 B $end
|
||||
$var wire 1 < Carry $end
|
||||
$var wire 1 : Sum $end
|
||||
$upscope $end
|
||||
$scope module h2 $end
|
||||
$var wire 1 : A $end
|
||||
$var wire 1 3 B $end
|
||||
$var wire 1 ; Carry $end
|
||||
$var wire 1 = Sum $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module f1 $end
|
||||
$var wire 1 > A $end
|
||||
$var wire 1 ? B $end
|
||||
$var wire 1 @ Carry $end
|
||||
$var wire 1 A CarryO $end
|
||||
$var wire 1 B xor1 $end
|
||||
$var wire 1 C and2 $end
|
||||
$var wire 1 D and1 $end
|
||||
$var wire 1 E Sum $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 > A $end
|
||||
$var wire 1 ? B $end
|
||||
$var wire 1 D Carry $end
|
||||
$var wire 1 B Sum $end
|
||||
$upscope $end
|
||||
$scope module h2 $end
|
||||
$var wire 1 B A $end
|
||||
$var wire 1 @ B $end
|
||||
$var wire 1 C Carry $end
|
||||
$var wire 1 E Sum $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module f2 $end
|
||||
$var wire 1 F A $end
|
||||
$var wire 1 G B $end
|
||||
$var wire 1 H Carry $end
|
||||
$var wire 1 I CarryO $end
|
||||
$var wire 1 J xor1 $end
|
||||
$var wire 1 K and2 $end
|
||||
$var wire 1 L and1 $end
|
||||
$var wire 1 M Sum $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 F A $end
|
||||
$var wire 1 G B $end
|
||||
$var wire 1 L Carry $end
|
||||
$var wire 1 J Sum $end
|
||||
$upscope $end
|
||||
$scope module h2 $end
|
||||
$var wire 1 J A $end
|
||||
$var wire 1 H B $end
|
||||
$var wire 1 K Carry $end
|
||||
$var wire 1 M Sum $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module f3 $end
|
||||
$var wire 1 N A $end
|
||||
$var wire 1 O B $end
|
||||
$var wire 1 P Carry $end
|
||||
$var wire 1 5 CarryO $end
|
||||
$var wire 1 Q xor1 $end
|
||||
$var wire 1 R and2 $end
|
||||
$var wire 1 S and1 $end
|
||||
$var wire 1 T Sum $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 N A $end
|
||||
$var wire 1 O B $end
|
||||
$var wire 1 S Carry $end
|
||||
$var wire 1 Q Sum $end
|
||||
$upscope $end
|
||||
$scope module h2 $end
|
||||
$var wire 1 Q A $end
|
||||
$var wire 1 P B $end
|
||||
$var wire 1 R Carry $end
|
||||
$var wire 1 T Sum $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module od1 $end
|
||||
$var wire 4 U A [3:0] $end
|
||||
$var wire 4 V B [3:0] $end
|
||||
$var wire 1 5 CarryOUT $end
|
||||
$var wire 4 W Y [3:0] $end
|
||||
$var wire 1 X addOverflow $end
|
||||
$var wire 1 Y detect1 $end
|
||||
$var wire 1 Z detect2 $end
|
||||
$var wire 1 [ opC $end
|
||||
$var wire 2 \ opCode [1:0] $end
|
||||
$var wire 1 ( overflowDetect $end
|
||||
$var wire 1 ] sign1 $end
|
||||
$var wire 1 ^ sign2 $end
|
||||
$var wire 1 _ sign3 $end
|
||||
$var wire 1 ` subOverflow $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module add1 $end
|
||||
$var wire 4 a A [3:0] $end
|
||||
$var wire 4 b B [3:0] $end
|
||||
$var wire 1 c CarryIN $end
|
||||
$var wire 1 ' overflow $end
|
||||
$var wire 4 d Y [3:0] $end
|
||||
$var wire 1 e CarryOUT $end
|
||||
$var wire 4 f Carry4 [3:0] $end
|
||||
$scope module f0 $end
|
||||
$var wire 1 g A $end
|
||||
$var wire 1 h B $end
|
||||
$var wire 1 c Carry $end
|
||||
$var wire 1 i CarryO $end
|
||||
$var wire 1 j xor1 $end
|
||||
$var wire 1 k and2 $end
|
||||
$var wire 1 l and1 $end
|
||||
$var wire 1 m Sum $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 g A $end
|
||||
$var wire 1 h B $end
|
||||
$var wire 1 l Carry $end
|
||||
$var wire 1 j Sum $end
|
||||
$upscope $end
|
||||
$scope module h2 $end
|
||||
$var wire 1 j A $end
|
||||
$var wire 1 c B $end
|
||||
$var wire 1 k Carry $end
|
||||
$var wire 1 m Sum $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module f1 $end
|
||||
$var wire 1 n A $end
|
||||
$var wire 1 o B $end
|
||||
$var wire 1 p Carry $end
|
||||
$var wire 1 q CarryO $end
|
||||
$var wire 1 r xor1 $end
|
||||
$var wire 1 s and2 $end
|
||||
$var wire 1 t and1 $end
|
||||
$var wire 1 u Sum $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 n A $end
|
||||
$var wire 1 o B $end
|
||||
$var wire 1 t Carry $end
|
||||
$var wire 1 r Sum $end
|
||||
$upscope $end
|
||||
$scope module h2 $end
|
||||
$var wire 1 r A $end
|
||||
$var wire 1 p B $end
|
||||
$var wire 1 s Carry $end
|
||||
$var wire 1 u Sum $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module f2 $end
|
||||
$var wire 1 v A $end
|
||||
$var wire 1 w B $end
|
||||
$var wire 1 x Carry $end
|
||||
$var wire 1 y CarryO $end
|
||||
$var wire 1 z xor1 $end
|
||||
$var wire 1 { and2 $end
|
||||
$var wire 1 | and1 $end
|
||||
$var wire 1 } Sum $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 v A $end
|
||||
$var wire 1 w B $end
|
||||
$var wire 1 | Carry $end
|
||||
$var wire 1 z Sum $end
|
||||
$upscope $end
|
||||
$scope module h2 $end
|
||||
$var wire 1 z A $end
|
||||
$var wire 1 x B $end
|
||||
$var wire 1 { Carry $end
|
||||
$var wire 1 } Sum $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module f3 $end
|
||||
$var wire 1 ~ A $end
|
||||
$var wire 1 !" B $end
|
||||
$var wire 1 "" Carry $end
|
||||
$var wire 1 e CarryO $end
|
||||
$var wire 1 #" xor1 $end
|
||||
$var wire 1 $" and2 $end
|
||||
$var wire 1 %" and1 $end
|
||||
$var wire 1 &" Sum $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 ~ A $end
|
||||
$var wire 1 !" B $end
|
||||
$var wire 1 %" Carry $end
|
||||
$var wire 1 #" Sum $end
|
||||
$upscope $end
|
||||
$scope module h2 $end
|
||||
$var wire 1 #" A $end
|
||||
$var wire 1 "" B $end
|
||||
$var wire 1 $" Carry $end
|
||||
$var wire 1 &" Sum $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module od1 $end
|
||||
$var wire 4 '" A [3:0] $end
|
||||
$var wire 4 (" B [3:0] $end
|
||||
$var wire 1 e CarryOUT $end
|
||||
$var wire 4 )" Y [3:0] $end
|
||||
$var wire 1 *" addOverflow $end
|
||||
$var wire 1 +" detect1 $end
|
||||
$var wire 1 ," detect2 $end
|
||||
$var wire 1 -" opC $end
|
||||
$var wire 2 ." opCode [1:0] $end
|
||||
$var wire 1 ' overflowDetect $end
|
||||
$var wire 1 /" sign1 $end
|
||||
$var wire 1 0" sign2 $end
|
||||
$var wire 1 1" sign3 $end
|
||||
$var wire 1 2" subOverflow $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module add2 $end
|
||||
$var wire 4 3" A [3:0] $end
|
||||
$var wire 4 4" B [3:0] $end
|
||||
$var wire 1 5" CarryIN $end
|
||||
$var wire 1 & overflow $end
|
||||
$var wire 4 6" Y [3:0] $end
|
||||
$var wire 1 7" CarryOUT $end
|
||||
$var wire 4 8" Carry4 [3:0] $end
|
||||
$scope module f0 $end
|
||||
$var wire 1 9" A $end
|
||||
$var wire 1 :" B $end
|
||||
$var wire 1 5" Carry $end
|
||||
$var wire 1 ;" CarryO $end
|
||||
$var wire 1 <" xor1 $end
|
||||
$var wire 1 =" and2 $end
|
||||
$var wire 1 >" and1 $end
|
||||
$var wire 1 ?" Sum $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 9" A $end
|
||||
$var wire 1 :" B $end
|
||||
$var wire 1 >" Carry $end
|
||||
$var wire 1 <" Sum $end
|
||||
$upscope $end
|
||||
$scope module h2 $end
|
||||
$var wire 1 <" A $end
|
||||
$var wire 1 5" B $end
|
||||
$var wire 1 =" Carry $end
|
||||
$var wire 1 ?" Sum $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module f1 $end
|
||||
$var wire 1 @" A $end
|
||||
$var wire 1 A" B $end
|
||||
$var wire 1 B" Carry $end
|
||||
$var wire 1 C" CarryO $end
|
||||
$var wire 1 D" xor1 $end
|
||||
$var wire 1 E" and2 $end
|
||||
$var wire 1 F" and1 $end
|
||||
$var wire 1 G" Sum $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 @" A $end
|
||||
$var wire 1 A" B $end
|
||||
$var wire 1 F" Carry $end
|
||||
$var wire 1 D" Sum $end
|
||||
$upscope $end
|
||||
$scope module h2 $end
|
||||
$var wire 1 D" A $end
|
||||
$var wire 1 B" B $end
|
||||
$var wire 1 E" Carry $end
|
||||
$var wire 1 G" Sum $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module f2 $end
|
||||
$var wire 1 H" A $end
|
||||
$var wire 1 I" B $end
|
||||
$var wire 1 J" Carry $end
|
||||
$var wire 1 K" CarryO $end
|
||||
$var wire 1 L" xor1 $end
|
||||
$var wire 1 M" and2 $end
|
||||
$var wire 1 N" and1 $end
|
||||
$var wire 1 O" Sum $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 H" A $end
|
||||
$var wire 1 I" B $end
|
||||
$var wire 1 N" Carry $end
|
||||
$var wire 1 L" Sum $end
|
||||
$upscope $end
|
||||
$scope module h2 $end
|
||||
$var wire 1 L" A $end
|
||||
$var wire 1 J" B $end
|
||||
$var wire 1 M" Carry $end
|
||||
$var wire 1 O" Sum $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module f3 $end
|
||||
$var wire 1 P" A $end
|
||||
$var wire 1 Q" B $end
|
||||
$var wire 1 R" Carry $end
|
||||
$var wire 1 7" CarryO $end
|
||||
$var wire 1 S" xor1 $end
|
||||
$var wire 1 T" and2 $end
|
||||
$var wire 1 U" and1 $end
|
||||
$var wire 1 V" Sum $end
|
||||
$scope module h1 $end
|
||||
$var wire 1 P" A $end
|
||||
$var wire 1 Q" B $end
|
||||
$var wire 1 U" Carry $end
|
||||
$var wire 1 S" Sum $end
|
||||
$upscope $end
|
||||
$scope module h2 $end
|
||||
$var wire 1 S" A $end
|
||||
$var wire 1 R" B $end
|
||||
$var wire 1 T" Carry $end
|
||||
$var wire 1 V" Sum $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module od1 $end
|
||||
$var wire 4 W" A [3:0] $end
|
||||
$var wire 4 X" B [3:0] $end
|
||||
$var wire 1 7" CarryOUT $end
|
||||
$var wire 4 Y" Y [3:0] $end
|
||||
$var wire 1 Z" addOverflow $end
|
||||
$var wire 1 [" detect1 $end
|
||||
$var wire 1 \" detect2 $end
|
||||
$var wire 1 ]" opC $end
|
||||
$var wire 2 ^" opCode [1:0] $end
|
||||
$var wire 1 & overflowDetect $end
|
||||
$var wire 1 _" sign1 $end
|
||||
$var wire 1 `" sign2 $end
|
||||
$var wire 1 a" sign3 $end
|
||||
$var wire 1 b" subOverflow $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
#0
|
||||
$dumpvars
|
||||
0b"
|
||||
0a"
|
||||
0`"
|
||||
1_"
|
||||
b1 ^"
|
||||
1]"
|
||||
0\"
|
||||
1["
|
||||
1Z"
|
||||
b0 Y"
|
||||
b0 X"
|
||||
b0 W"
|
||||
0V"
|
||||
0U"
|
||||
0T"
|
||||
0S"
|
||||
0R"
|
||||
0Q"
|
||||
0P"
|
||||
0O"
|
||||
0N"
|
||||
0M"
|
||||
0L"
|
||||
0K"
|
||||
0J"
|
||||
0I"
|
||||
0H"
|
||||
0G"
|
||||
0F"
|
||||
0E"
|
||||
0D"
|
||||
0C"
|
||||
0B"
|
||||
0A"
|
||||
0@"
|
||||
0?"
|
||||
0>"
|
||||
0="
|
||||
0<"
|
||||
0;"
|
||||
0:"
|
||||
09"
|
||||
bz000 8"
|
||||
07"
|
||||
b0 6"
|
||||
05"
|
||||
b0 4"
|
||||
b0 3"
|
||||
02"
|
||||
01"
|
||||
00"
|
||||
1/"
|
||||
b1 ."
|
||||
1-"
|
||||
0,"
|
||||
1+"
|
||||
1*"
|
||||
b0 )"
|
||||
b0 ("
|
||||
b0 '"
|
||||
0&"
|
||||
0%"
|
||||
0$"
|
||||
0#"
|
||||
0""
|
||||
0!"
|
||||
0~
|
||||
0}
|
||||
0|
|
||||
0{
|
||||
0z
|
||||
0y
|
||||
0x
|
||||
0w
|
||||
0v
|
||||
0u
|
||||
0t
|
||||
0s
|
||||
0r
|
||||
0q
|
||||
0p
|
||||
0o
|
||||
0n
|
||||
0m
|
||||
0l
|
||||
0k
|
||||
0j
|
||||
0i
|
||||
0h
|
||||
0g
|
||||
bz000 f
|
||||
0e
|
||||
b0 d
|
||||
0c
|
||||
b0 b
|
||||
b0 a
|
||||
0`
|
||||
0_
|
||||
0^
|
||||
1]
|
||||
b1 \
|
||||
1[
|
||||
0Z
|
||||
1Y
|
||||
1X
|
||||
b0 W
|
||||
b0 V
|
||||
b0 U
|
||||
0T
|
||||
0S
|
||||
0R
|
||||
0Q
|
||||
0P
|
||||
0O
|
||||
0N
|
||||
0M
|
||||
0L
|
||||
0K
|
||||
0J
|
||||
0I
|
||||
0H
|
||||
0G
|
||||
0F
|
||||
0E
|
||||
0D
|
||||
0C
|
||||
0B
|
||||
0A
|
||||
0@
|
||||
0?
|
||||
0>
|
||||
0=
|
||||
0<
|
||||
0;
|
||||
0:
|
||||
09
|
||||
08
|
||||
07
|
||||
bz000 6
|
||||
05
|
||||
b0 4
|
||||
03
|
||||
b0 2
|
||||
b0 1
|
||||
b0 0
|
||||
b0 /
|
||||
b0 .
|
||||
b0 -
|
||||
b0 ,
|
||||
b0 +
|
||||
b0 *
|
||||
b0 )
|
||||
0(
|
||||
0'
|
||||
0&
|
||||
b0 %
|
||||
b0 $
|
||||
b0 #
|
||||
b0 "
|
||||
b0 !
|
||||
$end
|
||||
#2
|
||||
b1000 #
|
||||
b1000 %
|
||||
#4
|
||||
b1000000 !
|
||||
b1000000 -
|
||||
0["
|
||||
0&
|
||||
b1000 .
|
||||
b1000 6"
|
||||
b1000 Y"
|
||||
1V"
|
||||
0Z"
|
||||
0\"
|
||||
1S"
|
||||
0_"
|
||||
1a"
|
||||
0`"
|
||||
1P"
|
||||
b1000 *
|
||||
b1000 3"
|
||||
b1000 W"
|
||||
b1000 "
|
||||
b1000 $
|
||||
#6
|
||||
1'
|
||||
1O"
|
||||
1,"
|
||||
1L"
|
||||
10"
|
||||
1I"
|
||||
1(
|
||||
1&"
|
||||
1Z
|
||||
1|
|
||||
1s
|
||||
1""
|
||||
1^
|
||||
1w
|
||||
1p
|
||||
1y
|
||||
1i
|
||||
0{
|
||||
1T
|
||||
1l
|
||||
1x
|
||||
1P
|
||||
1h
|
||||
bz111 f
|
||||
1q
|
||||
0?"
|
||||
1G"
|
||||
1I
|
||||
0t
|
||||
0<"
|
||||
1D"
|
||||
0&
|
||||
1E
|
||||
1K
|
||||
0o
|
||||
0:"
|
||||
1A"
|
||||
0\"
|
||||
1@
|
||||
1H
|
||||
b101 b
|
||||
b101 ("
|
||||
b110 4"
|
||||
b110 X"
|
||||
1["
|
||||
19
|
||||
bz111 6
|
||||
1A
|
||||
b1010 0
|
||||
b1010 4
|
||||
b1010 W
|
||||
0M
|
||||
0m
|
||||
0u
|
||||
b1100 /
|
||||
b1100 d
|
||||
b1100 )"
|
||||
1}
|
||||
b110 .
|
||||
b110 6"
|
||||
b110 Y"
|
||||
0V"
|
||||
1Z"
|
||||
1<
|
||||
1D
|
||||
1J
|
||||
0j
|
||||
1r
|
||||
0z
|
||||
0S"
|
||||
1_"
|
||||
0a"
|
||||
0`"
|
||||
18
|
||||
1?
|
||||
17
|
||||
1>
|
||||
1F
|
||||
1g
|
||||
1n
|
||||
1v
|
||||
0P"
|
||||
b110001 !
|
||||
b110001 -
|
||||
b11 )
|
||||
b11 2
|
||||
b11 V
|
||||
b111 ,
|
||||
b111 1
|
||||
b111 U
|
||||
b111 +
|
||||
b111 a
|
||||
b111 '"
|
||||
b0 *
|
||||
b0 3"
|
||||
b0 W"
|
||||
b111 #
|
||||
b111 %
|
||||
b111 "
|
||||
b111 $
|
||||
#8
|
||||
1E"
|
||||
1B"
|
||||
1;"
|
||||
1>"
|
||||
1:"
|
||||
0A"
|
||||
1%"
|
||||
0s
|
||||
1u
|
||||
1{
|
||||
0}
|
||||
1U"
|
||||
0M"
|
||||
17"
|
||||
1!"
|
||||
1t
|
||||
0r
|
||||
0|
|
||||
1z
|
||||
1Q"
|
||||
0T"
|
||||
1o
|
||||
0w
|
||||
1I"
|
||||
b11100001 !
|
||||
b11100001 -
|
||||
1J"
|
||||
1R"
|
||||
15
|
||||
b1011 b
|
||||
b1011 ("
|
||||
0Y
|
||||
0(
|
||||
1e
|
||||
b1101 4"
|
||||
b1101 X"
|
||||
1+"
|
||||
0'
|
||||
1["
|
||||
0&
|
||||
0?"
|
||||
1C"
|
||||
0G"
|
||||
bz111 8"
|
||||
1K"
|
||||
1O"
|
||||
0K
|
||||
1M
|
||||
1R
|
||||
b10110 0
|
||||
b110 4
|
||||
b110 W
|
||||
0T
|
||||
0X
|
||||
0Z
|
||||
0$"
|
||||
b11010 /
|
||||
b1010 d
|
||||
b1010 )"
|
||||
1&"
|
||||
1*"
|
||||
0,"
|
||||
b11100 .
|
||||
b1100 6"
|
||||
b1100 Y"
|
||||
1V"
|
||||
1Z"
|
||||
0\"
|
||||
0<"
|
||||
0F"
|
||||
1D"
|
||||
1N"
|
||||
0L"
|
||||
1L
|
||||
0J
|
||||
1Q
|
||||
0]
|
||||
1_
|
||||
1^
|
||||
0#"
|
||||
1/"
|
||||
01"
|
||||
00"
|
||||
0S"
|
||||
1_"
|
||||
0a"
|
||||
0`"
|
||||
19"
|
||||
1@"
|
||||
1H"
|
||||
1G
|
||||
1N
|
||||
1~
|
||||
1P"
|
||||
b111 )
|
||||
b111 2
|
||||
b111 V
|
||||
b1111 ,
|
||||
b1111 1
|
||||
b1111 U
|
||||
b1111 +
|
||||
b1111 a
|
||||
b1111 '"
|
||||
b1111 *
|
||||
b1111 3"
|
||||
b1111 W"
|
||||
b1111 #
|
||||
b1111 %
|
||||
b1111 "
|
||||
b1111 $
|
||||
#10
|
||||
22
project0.2/multiplierTB.v
Normal file
22
project0.2/multiplierTB.v
Normal file
@@ -0,0 +1,22 @@
|
||||
module multiplierTB();
|
||||
reg [3:0] A, B;
|
||||
wire [7:0] Y;
|
||||
|
||||
multiplier uut(
|
||||
.A(A),
|
||||
.B(B),
|
||||
.Y(Y)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("multiplier.vcd");
|
||||
$dumpvars;
|
||||
A = 4'b0000; B = 4'b0000; #2;
|
||||
A = 4'b0000; B = 4'b1000; #2;
|
||||
A = 4'b1000; B = 4'b1000; #2;
|
||||
A = 4'b0111; B = 4'b0111; #2;
|
||||
A = 4'b1111; B = 4'b1111; #2;
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
111
project0.2/opCode
Normal file
111
project0.2/opCode
Normal file
@@ -0,0 +1,111 @@
|
||||
#! /usr/bin/vvp
|
||||
:ivl_version "11.0 (stable)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
|
||||
S_0x5602ec702f00 .scope module, "opCodeTB" "opCodeTB" 2 1;
|
||||
.timescale 0 0;
|
||||
v0x5602ec71a9e0_0 .var "A", 2 0;
|
||||
v0x5602ec71aaa0_0 .net "opCode", 7 0, L_0x5602ec71c020; 1 drivers
|
||||
S_0x5602ec703090 .scope module, "uut" "opCode" 2 6, 3 1 0, S_0x5602ec702f00;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 3 "A";
|
||||
.port_info 1 /OUTPUT 8 "opCode";
|
||||
L_0x5602ec71ab70 .functor NOT 1, L_0x5602ec71ac40, C4<0>, C4<0>, C4<0>;
|
||||
L_0x5602ec71ad30 .functor NOT 1, L_0x5602ec71adc0, C4<0>, C4<0>, C4<0>;
|
||||
L_0x5602ec71aeb0 .functor NOT 1, L_0x5602ec71af50, C4<0>, C4<0>, C4<0>;
|
||||
L_0x5602ec71b040 .functor AND 1, L_0x5602ec71b140, L_0x5602ec71b210, C4<1>, C4<1>;
|
||||
L_0x5602ec71b300 .functor AND 1, L_0x5602ec71ab70, L_0x5602ec71b3c0, C4<1>, C4<1>;
|
||||
L_0x5602ec71b4f0 .functor AND 1, L_0x5602ec71b5f0, L_0x5602ec71ad30, C4<1>, C4<1>;
|
||||
L_0x5602ec71b6e0 .functor AND 1, L_0x5602ec71ab70, L_0x5602ec71ad30, C4<1>, C4<1>;
|
||||
L_0x5602ec71b750 .functor AND 1, L_0x5602ec71b6e0, L_0x5602ec71aeb0, C4<1>, C4<1>;
|
||||
L_0x5602ec71b8b0 .functor AND 1, L_0x5602ec71b6e0, L_0x5602ec71b920, C4<1>, C4<1>;
|
||||
L_0x5602ec71ba60 .functor AND 1, L_0x5602ec71b300, L_0x5602ec71aeb0, C4<1>, C4<1>;
|
||||
L_0x5602ec71bb80 .functor AND 1, L_0x5602ec71b300, L_0x5602ec71bbf0, C4<1>, C4<1>;
|
||||
L_0x5602ec71bc90 .functor AND 1, L_0x5602ec71b4f0, L_0x5602ec71aeb0, C4<1>, C4<1>;
|
||||
L_0x5602ec71bdc0 .functor AND 1, L_0x5602ec71b4f0, L_0x5602ec71be30, C4<1>, C4<1>;
|
||||
L_0x5602ec71bf30 .functor AND 1, L_0x5602ec71b040, L_0x5602ec71aeb0, C4<1>, C4<1>;
|
||||
L_0x5602ec71bd50 .functor AND 1, L_0x5602ec71b040, L_0x5602ec71c3e0, C4<1>, C4<1>;
|
||||
v0x5602ec6ef910_0 .net "A", 2 0, v0x5602ec71a9e0_0; 1 drivers
|
||||
v0x5602ec6ef0a0_0 .net *"_ivl_1", 0 0, L_0x5602ec71ac40; 1 drivers
|
||||
v0x5602ec6eec60_0 .net *"_ivl_11", 0 0, L_0x5602ec71b3c0; 1 drivers
|
||||
v0x5602ec6ee3f0_0 .net *"_ivl_13", 0 0, L_0x5602ec71b5f0; 1 drivers
|
||||
v0x5602ec6edfc0_0 .net *"_ivl_14", 0 0, L_0x5602ec71b750; 1 drivers
|
||||
v0x5602ec719640_0 .net *"_ivl_16", 0 0, L_0x5602ec71b8b0; 1 drivers
|
||||
v0x5602ec719720_0 .net *"_ivl_19", 0 0, L_0x5602ec71b920; 1 drivers
|
||||
v0x5602ec719800_0 .net *"_ivl_20", 0 0, L_0x5602ec71ba60; 1 drivers
|
||||
v0x5602ec7198e0_0 .net *"_ivl_22", 0 0, L_0x5602ec71bb80; 1 drivers
|
||||
v0x5602ec7199c0_0 .net *"_ivl_25", 0 0, L_0x5602ec71bbf0; 1 drivers
|
||||
v0x5602ec719aa0_0 .net *"_ivl_26", 0 0, L_0x5602ec71bc90; 1 drivers
|
||||
v0x5602ec719b80_0 .net *"_ivl_28", 0 0, L_0x5602ec71bdc0; 1 drivers
|
||||
v0x5602ec719c60_0 .net *"_ivl_3", 0 0, L_0x5602ec71adc0; 1 drivers
|
||||
v0x5602ec719d40_0 .net *"_ivl_31", 0 0, L_0x5602ec71be30; 1 drivers
|
||||
v0x5602ec719e20_0 .net *"_ivl_32", 0 0, L_0x5602ec71bf30; 1 drivers
|
||||
v0x5602ec719f00_0 .net *"_ivl_34", 0 0, L_0x5602ec71bd50; 1 drivers
|
||||
v0x5602ec719fe0_0 .net *"_ivl_38", 0 0, L_0x5602ec71c3e0; 1 drivers
|
||||
v0x5602ec71a0c0_0 .net *"_ivl_5", 0 0, L_0x5602ec71af50; 1 drivers
|
||||
v0x5602ec71a1a0_0 .net *"_ivl_7", 0 0, L_0x5602ec71b140; 1 drivers
|
||||
v0x5602ec71a280_0 .net *"_ivl_9", 0 0, L_0x5602ec71b210; 1 drivers
|
||||
v0x5602ec71a360_0 .net "and1", 0 0, L_0x5602ec71b040; 1 drivers
|
||||
v0x5602ec71a420_0 .net "and2", 0 0, L_0x5602ec71b300; 1 drivers
|
||||
v0x5602ec71a4e0_0 .net "and3", 0 0, L_0x5602ec71b4f0; 1 drivers
|
||||
v0x5602ec71a5a0_0 .net "and4", 0 0, L_0x5602ec71b6e0; 1 drivers
|
||||
v0x5602ec71a660_0 .net "notA", 0 0, L_0x5602ec71ab70; 1 drivers
|
||||
v0x5602ec71a720_0 .net "notB", 0 0, L_0x5602ec71ad30; 1 drivers
|
||||
v0x5602ec71a7e0_0 .net "notC", 0 0, L_0x5602ec71aeb0; 1 drivers
|
||||
v0x5602ec71a8a0_0 .net "opCode", 7 0, L_0x5602ec71c020; alias, 1 drivers
|
||||
L_0x5602ec71ac40 .part v0x5602ec71a9e0_0, 2, 1;
|
||||
L_0x5602ec71adc0 .part v0x5602ec71a9e0_0, 1, 1;
|
||||
L_0x5602ec71af50 .part v0x5602ec71a9e0_0, 0, 1;
|
||||
L_0x5602ec71b140 .part v0x5602ec71a9e0_0, 2, 1;
|
||||
L_0x5602ec71b210 .part v0x5602ec71a9e0_0, 1, 1;
|
||||
L_0x5602ec71b3c0 .part v0x5602ec71a9e0_0, 1, 1;
|
||||
L_0x5602ec71b5f0 .part v0x5602ec71a9e0_0, 2, 1;
|
||||
L_0x5602ec71b920 .part v0x5602ec71a9e0_0, 0, 1;
|
||||
L_0x5602ec71bbf0 .part v0x5602ec71a9e0_0, 0, 1;
|
||||
L_0x5602ec71be30 .part v0x5602ec71a9e0_0, 0, 1;
|
||||
LS_0x5602ec71c020_0_0 .concat8 [ 1 1 1 1], L_0x5602ec71b750, L_0x5602ec71b8b0, L_0x5602ec71ba60, L_0x5602ec71bb80;
|
||||
LS_0x5602ec71c020_0_4 .concat8 [ 1 1 1 1], L_0x5602ec71bc90, L_0x5602ec71bdc0, L_0x5602ec71bf30, L_0x5602ec71bd50;
|
||||
L_0x5602ec71c020 .concat8 [ 4 4 0 0], LS_0x5602ec71c020_0_0, LS_0x5602ec71c020_0_4;
|
||||
L_0x5602ec71c3e0 .part v0x5602ec71a9e0_0, 0, 1;
|
||||
.scope S_0x5602ec702f00;
|
||||
T_0 ;
|
||||
%vpi_call 2 13 "$dumpfile", "opCode.vcd" {0 0 0};
|
||||
%vpi_call 2 14 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 3;
|
||||
%store/vec4 v0x5602ec71a9e0_0, 0, 3;
|
||||
%delay 3, 0;
|
||||
%pushi/vec4 1, 0, 3;
|
||||
%store/vec4 v0x5602ec71a9e0_0, 0, 3;
|
||||
%delay 3, 0;
|
||||
%pushi/vec4 2, 0, 3;
|
||||
%store/vec4 v0x5602ec71a9e0_0, 0, 3;
|
||||
%delay 3, 0;
|
||||
%pushi/vec4 3, 0, 3;
|
||||
%store/vec4 v0x5602ec71a9e0_0, 0, 3;
|
||||
%delay 3, 0;
|
||||
%pushi/vec4 4, 0, 3;
|
||||
%store/vec4 v0x5602ec71a9e0_0, 0, 3;
|
||||
%delay 3, 0;
|
||||
%pushi/vec4 5, 0, 3;
|
||||
%store/vec4 v0x5602ec71a9e0_0, 0, 3;
|
||||
%delay 3, 0;
|
||||
%pushi/vec4 6, 0, 3;
|
||||
%store/vec4 v0x5602ec71a9e0_0, 0, 3;
|
||||
%delay 3, 0;
|
||||
%pushi/vec4 7, 0, 3;
|
||||
%store/vec4 v0x5602ec71a9e0_0, 0, 3;
|
||||
%delay 3, 0;
|
||||
%vpi_call 2 23 "$finish" {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 4;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"opCodeTB.v";
|
||||
"opCode.v";
|
||||
25
project0.2/opCode.v
Normal file
25
project0.2/opCode.v
Normal file
@@ -0,0 +1,25 @@
|
||||
module opCode (
|
||||
input [2:0] A,
|
||||
output [7:0] opCode
|
||||
);
|
||||
wire and1, and2, and3, and4, notA, notB, notC;
|
||||
|
||||
not n1(notA, A[2]);
|
||||
not n2(notB, A[1]);
|
||||
not n3(notC, A[0]);
|
||||
|
||||
and a01(and1, A[2], A[1]);
|
||||
and a02(and2, notA, A[1]);
|
||||
and a03(and3, A[2], notB);
|
||||
and a04(and4, notA, notB);
|
||||
|
||||
and a1(opCode[0], and4, notC);
|
||||
and a2(opCode[1], and4, A[0]);
|
||||
and a3(opCode[2], and2, notC);
|
||||
and a4(opCode[3], and2, A[0]);
|
||||
and a5(opCode[4], and3, notC);
|
||||
and a6(opCode[5], and3, A[0]);
|
||||
and a7(opCode[6], and1, notC);
|
||||
and a8(opCode[7], and1, A[0]);
|
||||
|
||||
endmodule
|
||||
92
project0.2/opCode.vcd
Normal file
92
project0.2/opCode.vcd
Normal file
@@ -0,0 +1,92 @@
|
||||
$date
|
||||
Sun Dec 15 04:12:35 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module opCodeTB $end
|
||||
$var wire 8 ! opCode [7:0] $end
|
||||
$var reg 3 " A [2:0] $end
|
||||
$scope module uut $end
|
||||
$var wire 3 # A [2:0] $end
|
||||
$var wire 1 $ and1 $end
|
||||
$var wire 1 % and2 $end
|
||||
$var wire 1 & and3 $end
|
||||
$var wire 1 ' and4 $end
|
||||
$var wire 1 ( notA $end
|
||||
$var wire 1 ) notB $end
|
||||
$var wire 1 * notC $end
|
||||
$var wire 8 + opCode [7:0] $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
#0
|
||||
$dumpvars
|
||||
b1 +
|
||||
1*
|
||||
1)
|
||||
1(
|
||||
1'
|
||||
0&
|
||||
0%
|
||||
0$
|
||||
b0 #
|
||||
b0 "
|
||||
b1 !
|
||||
$end
|
||||
#3
|
||||
0*
|
||||
b10 !
|
||||
b10 +
|
||||
b1 "
|
||||
b1 #
|
||||
#6
|
||||
0'
|
||||
0)
|
||||
1*
|
||||
1%
|
||||
b100 !
|
||||
b100 +
|
||||
b10 "
|
||||
b10 #
|
||||
#9
|
||||
0*
|
||||
b1000 !
|
||||
b1000 +
|
||||
b11 "
|
||||
b11 #
|
||||
#12
|
||||
1&
|
||||
0(
|
||||
1)
|
||||
1*
|
||||
0%
|
||||
b10000 !
|
||||
b10000 +
|
||||
b100 "
|
||||
b100 #
|
||||
#15
|
||||
0*
|
||||
b100000 !
|
||||
b100000 +
|
||||
b101 "
|
||||
b101 #
|
||||
#18
|
||||
0&
|
||||
0)
|
||||
1*
|
||||
1$
|
||||
b1000000 !
|
||||
b1000000 +
|
||||
b110 "
|
||||
b110 #
|
||||
#21
|
||||
0*
|
||||
b10000000 !
|
||||
b10000000 +
|
||||
b111 "
|
||||
b111 #
|
||||
#24
|
||||
26
project0.2/opCodeTB.v
Normal file
26
project0.2/opCodeTB.v
Normal file
@@ -0,0 +1,26 @@
|
||||
module opCodeTB();
|
||||
|
||||
reg [2:0] A;
|
||||
wire [7:0] opCode;
|
||||
|
||||
opCode uut (
|
||||
.A(A),
|
||||
|
||||
.opCode(opCode)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("opCode.vcd");
|
||||
$dumpvars;
|
||||
A = 3'b000; #3;
|
||||
A = 3'b001; #3;
|
||||
A = 3'b010; #3;
|
||||
A = 3'b011; #3;
|
||||
A = 3'b100; #3;
|
||||
A = 3'b101; #3;
|
||||
A = 3'b110; #3;
|
||||
A = 3'b111; #3;
|
||||
$finish;
|
||||
end
|
||||
|
||||
endmodule
|
||||
29
project0.2/overflowDetect.v
Normal file
29
project0.2/overflowDetect.v
Normal file
@@ -0,0 +1,29 @@
|
||||
module overflowDetect (
|
||||
input [1:0] opCode,
|
||||
input [3:0] A, B,
|
||||
input [3:0] Y,
|
||||
input CarryOUT,
|
||||
output overflowDetect
|
||||
);
|
||||
|
||||
wire opC;
|
||||
wire sign1, sign2, sign3, sign4;
|
||||
wire addOverflow, subOverflow;
|
||||
wire detect1, detect2;
|
||||
|
||||
or o1 (opC, opCode[0], opCode[1]); //check add or sub
|
||||
|
||||
xnor xno1 (sign1, A[3], B[3]); // A B same sign
|
||||
xor xo2 (sign3, A[3], B[3]); // A and B opposite sign
|
||||
|
||||
xor xo1 (sign2, Y[3], A[3]); // A and Sum opposite sign
|
||||
|
||||
and a01 (addOverflow, sign1, opCode[0]); // A B same for add
|
||||
and a02 (subOverflow, sign3, opCode[1]); // A B diff for sub
|
||||
|
||||
or o2 (detect1, addOverflow, subOverflow);
|
||||
|
||||
and a03(detect2, detect1, sign2);
|
||||
and a04(overflowDetect, opC, detect2);
|
||||
|
||||
endmodule
|
||||
331
project0.2/subtraction
Normal file
331
project0.2/subtraction
Normal file
@@ -0,0 +1,331 @@
|
||||
#! /usr/bin/vvp
|
||||
:ivl_version "11.0 (stable)";
|
||||
:ivl_delay_selection "TYPICAL";
|
||||
:vpi_time_precision + 0;
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
|
||||
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
|
||||
S_0x55fdbe99f210 .scope module, "subtractionTB" "subtractionTB" 2 1;
|
||||
.timescale 0 0;
|
||||
v0x55fdbe9cae90_0 .var "A", 3 0;
|
||||
v0x55fdbe9cafc0_0 .var "B", 3 0;
|
||||
v0x55fdbe9cb0d0_0 .var "BorrowIN", 0 0;
|
||||
v0x55fdbe9cb170_0 .net "BorrowOut", 0 0, L_0x55fdbe9cd610; 1 drivers
|
||||
v0x55fdbe9cb210_0 .net "Y", 3 0, L_0x55fdbe9cdb40; 1 drivers
|
||||
v0x55fdbe9cb350_0 .net "overflow", 0 0, L_0x55fdbe9ceb90; 1 drivers
|
||||
S_0x55fdbe99f550 .scope module, "uut" "subtraction" 2 10, 3 1 0, S_0x55fdbe99f210;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 4 "A";
|
||||
.port_info 1 /INPUT 4 "B";
|
||||
.port_info 2 /INPUT 1 "BorrowIN";
|
||||
.port_info 3 /OUTPUT 4 "Y";
|
||||
.port_info 4 /OUTPUT 1 "BorrowOut";
|
||||
.port_info 5 /OUTPUT 1 "overflow";
|
||||
v0x55fdbe9ca770_0 .net "A", 3 0, v0x55fdbe9cae90_0; 1 drivers
|
||||
v0x55fdbe9ca850_0 .net "B", 3 0, v0x55fdbe9cafc0_0; 1 drivers
|
||||
v0x55fdbe9ca920_0 .net "BorrowIN", 0 0, v0x55fdbe9cb0d0_0; 1 drivers
|
||||
v0x55fdbe9ca9f0_0 .net "BorrowOut", 0 0, L_0x55fdbe9cd610; alias, 1 drivers
|
||||
v0x55fdbe9caae0_0 .net "Y", 3 0, L_0x55fdbe9cdb40; alias, 1 drivers
|
||||
o0x7f3602c5f6c8 .functor BUFZ 1, C4<z>; HiZ drive
|
||||
; Elide local net with no drivers, v0x55fdbe9cabd0_0 name=_ivl_41
|
||||
v0x55fdbe9cac70_0 .net "overflow", 0 0, L_0x55fdbe9ceb90; alias, 1 drivers
|
||||
v0x55fdbe9cad10_0 .net "tempB", 3 0, L_0x55fdbe9ceca0; 1 drivers
|
||||
L_0x55fdbe9cba50 .part v0x55fdbe9cae90_0, 0, 1;
|
||||
L_0x55fdbe9cbba0 .part v0x55fdbe9cafc0_0, 0, 1;
|
||||
L_0x55fdbe9cc2e0 .part v0x55fdbe9cae90_0, 1, 1;
|
||||
L_0x55fdbe9cc4a0 .part v0x55fdbe9cafc0_0, 1, 1;
|
||||
L_0x55fdbe9cc660 .part L_0x55fdbe9ceca0, 0, 1;
|
||||
L_0x55fdbe9ccc70 .part v0x55fdbe9cae90_0, 2, 1;
|
||||
L_0x55fdbe9ccde0 .part v0x55fdbe9cafc0_0, 2, 1;
|
||||
L_0x55fdbe9ccf10 .part L_0x55fdbe9ceca0, 1, 1;
|
||||
L_0x55fdbe9cd750 .part v0x55fdbe9cae90_0, 3, 1;
|
||||
L_0x55fdbe9cd880 .part v0x55fdbe9cafc0_0, 3, 1;
|
||||
L_0x55fdbe9cda10 .part L_0x55fdbe9ceca0, 2, 1;
|
||||
L_0x55fdbe9cdb40 .concat8 [ 1 1 1 1], L_0x55fdbe9cb730, L_0x55fdbe9cbf20, L_0x55fdbe9cc900, L_0x55fdbe9cd2e0;
|
||||
L_0x55fdbe9ceca0 .concat [ 1 1 1 1], L_0x55fdbe9cb9c0, L_0x55fdbe9cc250, L_0x55fdbe9ccbe0, o0x7f3602c5f6c8;
|
||||
S_0x55fdbe98a330 .scope module, "f0" "fullsubtraction" 3 12, 4 1 0, S_0x55fdbe99f550;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "BorrowIN";
|
||||
.port_info 3 /OUTPUT 1 "Difference";
|
||||
.port_info 4 /OUTPUT 1 "BorrowOut";
|
||||
L_0x55fdbe9cb9c0 .functor OR 1, L_0x55fdbe9cb620, L_0x55fdbe9cb950, C4<0>, C4<0>;
|
||||
v0x55fdbe9c4400_0 .net "A", 0 0, L_0x55fdbe9cba50; 1 drivers
|
||||
v0x55fdbe9c44c0_0 .net "B", 0 0, L_0x55fdbe9cbba0; 1 drivers
|
||||
v0x55fdbe9c4590_0 .net "BorrowIN", 0 0, v0x55fdbe9cb0d0_0; alias, 1 drivers
|
||||
v0x55fdbe9c4690_0 .net "BorrowOut", 0 0, L_0x55fdbe9cb9c0; 1 drivers
|
||||
v0x55fdbe9c4730_0 .net "Difference", 0 0, L_0x55fdbe9cb730; 1 drivers
|
||||
v0x55fdbe9c4820_0 .net "tempB1", 0 0, L_0x55fdbe9cb620; 1 drivers
|
||||
v0x55fdbe9c48f0_0 .net "tempB2", 0 0, L_0x55fdbe9cb950; 1 drivers
|
||||
v0x55fdbe9c49c0_0 .net "tempD", 0 0, L_0x55fdbe9cb440; 1 drivers
|
||||
S_0x55fdbe996d90 .scope module, "hf1" "halfsubtraction" 4 8, 5 1 0, S_0x55fdbe98a330;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Difference";
|
||||
.port_info 3 /OUTPUT 1 "Borrow";
|
||||
L_0x55fdbe9cb440 .functor XOR 1, L_0x55fdbe9cba50, L_0x55fdbe9cbba0, C4<0>, C4<0>;
|
||||
L_0x55fdbe9cb590 .functor NOT 1, L_0x55fdbe9cba50, C4<0>, C4<0>, C4<0>;
|
||||
L_0x55fdbe9cb620 .functor AND 1, L_0x55fdbe9cb590, L_0x55fdbe9cbba0, C4<1>, C4<1>;
|
||||
v0x55fdbe99fb80_0 .net "A", 0 0, L_0x55fdbe9cba50; alias, 1 drivers
|
||||
v0x55fdbe98c6e0_0 .net "B", 0 0, L_0x55fdbe9cbba0; alias, 1 drivers
|
||||
v0x55fdbe98a9d0_0 .net "Borrow", 0 0, L_0x55fdbe9cb620; alias, 1 drivers
|
||||
v0x55fdbe9c3b10_0 .net "Difference", 0 0, L_0x55fdbe9cb440; alias, 1 drivers
|
||||
v0x55fdbe9c3bd0_0 .net "notA", 0 0, L_0x55fdbe9cb590; 1 drivers
|
||||
S_0x55fdbe9c3d60 .scope module, "hf2" "halfsubtraction" 4 9, 5 1 0, S_0x55fdbe98a330;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Difference";
|
||||
.port_info 3 /OUTPUT 1 "Borrow";
|
||||
L_0x55fdbe9cb730 .functor XOR 1, L_0x55fdbe9cb440, v0x55fdbe9cb0d0_0, C4<0>, C4<0>;
|
||||
L_0x55fdbe9cb8c0 .functor NOT 1, L_0x55fdbe9cb440, C4<0>, C4<0>, C4<0>;
|
||||
L_0x55fdbe9cb950 .functor AND 1, L_0x55fdbe9cb8c0, v0x55fdbe9cb0d0_0, C4<1>, C4<1>;
|
||||
v0x55fdbe9c3fd0_0 .net "A", 0 0, L_0x55fdbe9cb440; alias, 1 drivers
|
||||
v0x55fdbe9c4070_0 .net "B", 0 0, v0x55fdbe9cb0d0_0; alias, 1 drivers
|
||||
v0x55fdbe9c4110_0 .net "Borrow", 0 0, L_0x55fdbe9cb950; alias, 1 drivers
|
||||
v0x55fdbe9c41b0_0 .net "Difference", 0 0, L_0x55fdbe9cb730; alias, 1 drivers
|
||||
v0x55fdbe9c4270_0 .net "notA", 0 0, L_0x55fdbe9cb8c0; 1 drivers
|
||||
S_0x55fdbe9c4ab0 .scope module, "f1" "fullsubtraction" 3 13, 4 1 0, S_0x55fdbe99f550;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "BorrowIN";
|
||||
.port_info 3 /OUTPUT 1 "Difference";
|
||||
.port_info 4 /OUTPUT 1 "BorrowOut";
|
||||
L_0x55fdbe9cc250 .functor OR 1, L_0x55fdbe9cbe10, L_0x55fdbe9cc140, C4<0>, C4<0>;
|
||||
v0x55fdbe9c5ad0_0 .net "A", 0 0, L_0x55fdbe9cc2e0; 1 drivers
|
||||
v0x55fdbe9c5b90_0 .net "B", 0 0, L_0x55fdbe9cc4a0; 1 drivers
|
||||
v0x55fdbe9c5c60_0 .net "BorrowIN", 0 0, L_0x55fdbe9cc660; 1 drivers
|
||||
v0x55fdbe9c5d60_0 .net "BorrowOut", 0 0, L_0x55fdbe9cc250; 1 drivers
|
||||
v0x55fdbe9c5e00_0 .net "Difference", 0 0, L_0x55fdbe9cbf20; 1 drivers
|
||||
v0x55fdbe9c5ef0_0 .net "tempB1", 0 0, L_0x55fdbe9cbe10; 1 drivers
|
||||
v0x55fdbe9c5fc0_0 .net "tempB2", 0 0, L_0x55fdbe9cc140; 1 drivers
|
||||
v0x55fdbe9c6090_0 .net "tempD", 0 0, L_0x55fdbe9cbcd0; 1 drivers
|
||||
S_0x55fdbe9c4c90 .scope module, "hf1" "halfsubtraction" 4 8, 5 1 0, S_0x55fdbe9c4ab0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Difference";
|
||||
.port_info 3 /OUTPUT 1 "Borrow";
|
||||
L_0x55fdbe9cbcd0 .functor XOR 1, L_0x55fdbe9cc2e0, L_0x55fdbe9cc4a0, C4<0>, C4<0>;
|
||||
L_0x55fdbe9cbd80 .functor NOT 1, L_0x55fdbe9cc2e0, C4<0>, C4<0>, C4<0>;
|
||||
L_0x55fdbe9cbe10 .functor AND 1, L_0x55fdbe9cbd80, L_0x55fdbe9cc4a0, C4<1>, C4<1>;
|
||||
v0x55fdbe9c4f10_0 .net "A", 0 0, L_0x55fdbe9cc2e0; alias, 1 drivers
|
||||
v0x55fdbe9c4ff0_0 .net "B", 0 0, L_0x55fdbe9cc4a0; alias, 1 drivers
|
||||
v0x55fdbe9c50b0_0 .net "Borrow", 0 0, L_0x55fdbe9cbe10; alias, 1 drivers
|
||||
v0x55fdbe9c5180_0 .net "Difference", 0 0, L_0x55fdbe9cbcd0; alias, 1 drivers
|
||||
v0x55fdbe9c5240_0 .net "notA", 0 0, L_0x55fdbe9cbd80; 1 drivers
|
||||
S_0x55fdbe9c53d0 .scope module, "hf2" "halfsubtraction" 4 9, 5 1 0, S_0x55fdbe9c4ab0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Difference";
|
||||
.port_info 3 /OUTPUT 1 "Borrow";
|
||||
L_0x55fdbe9cbf20 .functor XOR 1, L_0x55fdbe9cbcd0, L_0x55fdbe9cc660, C4<0>, C4<0>;
|
||||
L_0x55fdbe9cc0b0 .functor NOT 1, L_0x55fdbe9cbcd0, C4<0>, C4<0>, C4<0>;
|
||||
L_0x55fdbe9cc140 .functor AND 1, L_0x55fdbe9cc0b0, L_0x55fdbe9cc660, C4<1>, C4<1>;
|
||||
v0x55fdbe9c5640_0 .net "A", 0 0, L_0x55fdbe9cbcd0; alias, 1 drivers
|
||||
v0x55fdbe9c5710_0 .net "B", 0 0, L_0x55fdbe9cc660; alias, 1 drivers
|
||||
v0x55fdbe9c57b0_0 .net "Borrow", 0 0, L_0x55fdbe9cc140; alias, 1 drivers
|
||||
v0x55fdbe9c5880_0 .net "Difference", 0 0, L_0x55fdbe9cbf20; alias, 1 drivers
|
||||
v0x55fdbe9c5940_0 .net "notA", 0 0, L_0x55fdbe9cc0b0; 1 drivers
|
||||
S_0x55fdbe9c6180 .scope module, "f2" "fullsubtraction" 3 14, 4 1 0, S_0x55fdbe99f550;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "BorrowIN";
|
||||
.port_info 3 /OUTPUT 1 "Difference";
|
||||
.port_info 4 /OUTPUT 1 "BorrowOut";
|
||||
L_0x55fdbe9ccbe0 .functor OR 1, L_0x55fdbe9cc890, L_0x55fdbe9ccad0, C4<0>, C4<0>;
|
||||
v0x55fdbe9c7230_0 .net "A", 0 0, L_0x55fdbe9ccc70; 1 drivers
|
||||
v0x55fdbe9c72f0_0 .net "B", 0 0, L_0x55fdbe9ccde0; 1 drivers
|
||||
v0x55fdbe9c73c0_0 .net "BorrowIN", 0 0, L_0x55fdbe9ccf10; 1 drivers
|
||||
v0x55fdbe9c74c0_0 .net "BorrowOut", 0 0, L_0x55fdbe9ccbe0; 1 drivers
|
||||
v0x55fdbe9c7560_0 .net "Difference", 0 0, L_0x55fdbe9cc900; 1 drivers
|
||||
v0x55fdbe9c7650_0 .net "tempB1", 0 0, L_0x55fdbe9cc890; 1 drivers
|
||||
v0x55fdbe9c7720_0 .net "tempB2", 0 0, L_0x55fdbe9ccad0; 1 drivers
|
||||
v0x55fdbe9c77f0_0 .net "tempD", 0 0, L_0x55fdbe9cc790; 1 drivers
|
||||
S_0x55fdbe9c6410 .scope module, "hf1" "halfsubtraction" 4 8, 5 1 0, S_0x55fdbe9c6180;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Difference";
|
||||
.port_info 3 /OUTPUT 1 "Borrow";
|
||||
L_0x55fdbe9cc790 .functor XOR 1, L_0x55fdbe9ccc70, L_0x55fdbe9ccde0, C4<0>, C4<0>;
|
||||
L_0x55fdbe9cc800 .functor NOT 1, L_0x55fdbe9ccc70, C4<0>, C4<0>, C4<0>;
|
||||
L_0x55fdbe9cc890 .functor AND 1, L_0x55fdbe9cc800, L_0x55fdbe9ccde0, C4<1>, C4<1>;
|
||||
v0x55fdbe9c6690_0 .net "A", 0 0, L_0x55fdbe9ccc70; alias, 1 drivers
|
||||
v0x55fdbe9c6750_0 .net "B", 0 0, L_0x55fdbe9ccde0; alias, 1 drivers
|
||||
v0x55fdbe9c6810_0 .net "Borrow", 0 0, L_0x55fdbe9cc890; alias, 1 drivers
|
||||
v0x55fdbe9c68e0_0 .net "Difference", 0 0, L_0x55fdbe9cc790; alias, 1 drivers
|
||||
v0x55fdbe9c69a0_0 .net "notA", 0 0, L_0x55fdbe9cc800; 1 drivers
|
||||
S_0x55fdbe9c6b30 .scope module, "hf2" "halfsubtraction" 4 9, 5 1 0, S_0x55fdbe9c6180;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Difference";
|
||||
.port_info 3 /OUTPUT 1 "Borrow";
|
||||
L_0x55fdbe9cc900 .functor XOR 1, L_0x55fdbe9cc790, L_0x55fdbe9ccf10, C4<0>, C4<0>;
|
||||
L_0x55fdbe9cca40 .functor NOT 1, L_0x55fdbe9cc790, C4<0>, C4<0>, C4<0>;
|
||||
L_0x55fdbe9ccad0 .functor AND 1, L_0x55fdbe9cca40, L_0x55fdbe9ccf10, C4<1>, C4<1>;
|
||||
v0x55fdbe9c6da0_0 .net "A", 0 0, L_0x55fdbe9cc790; alias, 1 drivers
|
||||
v0x55fdbe9c6e70_0 .net "B", 0 0, L_0x55fdbe9ccf10; alias, 1 drivers
|
||||
v0x55fdbe9c6f10_0 .net "Borrow", 0 0, L_0x55fdbe9ccad0; alias, 1 drivers
|
||||
v0x55fdbe9c6fe0_0 .net "Difference", 0 0, L_0x55fdbe9cc900; alias, 1 drivers
|
||||
v0x55fdbe9c70a0_0 .net "notA", 0 0, L_0x55fdbe9cca40; 1 drivers
|
||||
S_0x55fdbe9c78e0 .scope module, "f3" "fullsubtraction" 3 15, 4 1 0, S_0x55fdbe99f550;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /INPUT 1 "BorrowIN";
|
||||
.port_info 3 /OUTPUT 1 "Difference";
|
||||
.port_info 4 /OUTPUT 1 "BorrowOut";
|
||||
L_0x55fdbe9cd610 .functor OR 1, L_0x55fdbe9cd1d0, L_0x55fdbe9cd500, C4<0>, C4<0>;
|
||||
v0x55fdbe9c8980_0 .net "A", 0 0, L_0x55fdbe9cd750; 1 drivers
|
||||
v0x55fdbe9c8a40_0 .net "B", 0 0, L_0x55fdbe9cd880; 1 drivers
|
||||
v0x55fdbe9c8b10_0 .net "BorrowIN", 0 0, L_0x55fdbe9cda10; 1 drivers
|
||||
v0x55fdbe9c8c10_0 .net "BorrowOut", 0 0, L_0x55fdbe9cd610; alias, 1 drivers
|
||||
v0x55fdbe9c8cb0_0 .net "Difference", 0 0, L_0x55fdbe9cd2e0; 1 drivers
|
||||
v0x55fdbe9c8da0_0 .net "tempB1", 0 0, L_0x55fdbe9cd1d0; 1 drivers
|
||||
v0x55fdbe9c8e70_0 .net "tempB2", 0 0, L_0x55fdbe9cd500; 1 drivers
|
||||
v0x55fdbe9c8f40_0 .net "tempD", 0 0, L_0x55fdbe9cd090; 1 drivers
|
||||
S_0x55fdbe9c7b40 .scope module, "hf1" "halfsubtraction" 4 8, 5 1 0, S_0x55fdbe9c78e0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Difference";
|
||||
.port_info 3 /OUTPUT 1 "Borrow";
|
||||
L_0x55fdbe9cd090 .functor XOR 1, L_0x55fdbe9cd750, L_0x55fdbe9cd880, C4<0>, C4<0>;
|
||||
L_0x55fdbe9cd140 .functor NOT 1, L_0x55fdbe9cd750, C4<0>, C4<0>, C4<0>;
|
||||
L_0x55fdbe9cd1d0 .functor AND 1, L_0x55fdbe9cd140, L_0x55fdbe9cd880, C4<1>, C4<1>;
|
||||
v0x55fdbe9c7dc0_0 .net "A", 0 0, L_0x55fdbe9cd750; alias, 1 drivers
|
||||
v0x55fdbe9c7ea0_0 .net "B", 0 0, L_0x55fdbe9cd880; alias, 1 drivers
|
||||
v0x55fdbe9c7f60_0 .net "Borrow", 0 0, L_0x55fdbe9cd1d0; alias, 1 drivers
|
||||
v0x55fdbe9c8030_0 .net "Difference", 0 0, L_0x55fdbe9cd090; alias, 1 drivers
|
||||
v0x55fdbe9c80f0_0 .net "notA", 0 0, L_0x55fdbe9cd140; 1 drivers
|
||||
S_0x55fdbe9c8280 .scope module, "hf2" "halfsubtraction" 4 9, 5 1 0, S_0x55fdbe9c78e0;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 1 "A";
|
||||
.port_info 1 /INPUT 1 "B";
|
||||
.port_info 2 /OUTPUT 1 "Difference";
|
||||
.port_info 3 /OUTPUT 1 "Borrow";
|
||||
L_0x55fdbe9cd2e0 .functor XOR 1, L_0x55fdbe9cd090, L_0x55fdbe9cda10, C4<0>, C4<0>;
|
||||
L_0x55fdbe9cd470 .functor NOT 1, L_0x55fdbe9cd090, C4<0>, C4<0>, C4<0>;
|
||||
L_0x55fdbe9cd500 .functor AND 1, L_0x55fdbe9cd470, L_0x55fdbe9cda10, C4<1>, C4<1>;
|
||||
v0x55fdbe9c84f0_0 .net "A", 0 0, L_0x55fdbe9cd090; alias, 1 drivers
|
||||
v0x55fdbe9c85c0_0 .net "B", 0 0, L_0x55fdbe9cda10; alias, 1 drivers
|
||||
v0x55fdbe9c8660_0 .net "Borrow", 0 0, L_0x55fdbe9cd500; alias, 1 drivers
|
||||
v0x55fdbe9c8730_0 .net "Difference", 0 0, L_0x55fdbe9cd2e0; alias, 1 drivers
|
||||
v0x55fdbe9c87f0_0 .net "notA", 0 0, L_0x55fdbe9cd470; 1 drivers
|
||||
S_0x55fdbe9c9030 .scope module, "od1" "overflowDetect" 3 18, 6 1 0, S_0x55fdbe99f550;
|
||||
.timescale 0 0;
|
||||
.port_info 0 /INPUT 2 "opCode";
|
||||
.port_info 1 /INPUT 4 "A";
|
||||
.port_info 2 /INPUT 4 "B";
|
||||
.port_info 3 /INPUT 4 "Y";
|
||||
.port_info 4 /INPUT 1 "CarryOUT";
|
||||
.port_info 5 /OUTPUT 1 "overflowDetect";
|
||||
L_0x55fdbe9cdc50 .functor OR 1, L_0x55fdbe9cdce0, L_0x55fdbe9cdd80, C4<0>, C4<0>;
|
||||
L_0x55fdbe9cde20 .functor XNOR 1, L_0x55fdbe9cde90, L_0x55fdbe9cdf30, C4<0>, C4<0>;
|
||||
L_0x55fdbe9cdfd0 .functor XOR 1, L_0x55fdbe9ce040, L_0x55fdbe9ce130, C4<0>, C4<0>;
|
||||
L_0x55fdbe9ce370 .functor XOR 1, L_0x55fdbe9ce3e0, L_0x55fdbe9ce4d0, C4<0>, C4<0>;
|
||||
L_0x55fdbe9ce5c0 .functor AND 1, L_0x55fdbe9cde20, L_0x55fdbe9ce680, C4<1>, C4<1>;
|
||||
L_0x55fdbe9ce770 .functor AND 1, L_0x55fdbe9cdfd0, L_0x55fdbe9ce870, C4<1>, C4<1>;
|
||||
L_0x55fdbe9ce9c0 .functor OR 1, L_0x55fdbe9ce5c0, L_0x55fdbe9ce770, C4<0>, C4<0>;
|
||||
L_0x55fdbe9cea30 .functor AND 1, L_0x55fdbe9ce9c0, L_0x55fdbe9ce370, C4<1>, C4<1>;
|
||||
L_0x55fdbe9ceb90 .functor AND 1, L_0x55fdbe9cdc50, L_0x55fdbe9cea30, C4<1>, C4<1>;
|
||||
v0x55fdbe9c9300_0 .net "A", 3 0, v0x55fdbe9cae90_0; alias, 1 drivers
|
||||
v0x55fdbe9c93e0_0 .net "B", 3 0, v0x55fdbe9cafc0_0; alias, 1 drivers
|
||||
v0x55fdbe9c94c0_0 .net "CarryOUT", 0 0, L_0x55fdbe9cd610; alias, 1 drivers
|
||||
v0x55fdbe9c9560_0 .net "Y", 3 0, L_0x55fdbe9cdb40; alias, 1 drivers
|
||||
v0x55fdbe9c9600_0 .net *"_ivl_1", 0 0, L_0x55fdbe9cdce0; 1 drivers
|
||||
v0x55fdbe9c9730_0 .net *"_ivl_11", 0 0, L_0x55fdbe9ce130; 1 drivers
|
||||
v0x55fdbe9c9810_0 .net *"_ivl_13", 0 0, L_0x55fdbe9ce3e0; 1 drivers
|
||||
v0x55fdbe9c98f0_0 .net *"_ivl_15", 0 0, L_0x55fdbe9ce4d0; 1 drivers
|
||||
v0x55fdbe9c99d0_0 .net *"_ivl_17", 0 0, L_0x55fdbe9ce680; 1 drivers
|
||||
v0x55fdbe9c9ab0_0 .net *"_ivl_19", 0 0, L_0x55fdbe9ce870; 1 drivers
|
||||
v0x55fdbe9c9b90_0 .net *"_ivl_3", 0 0, L_0x55fdbe9cdd80; 1 drivers
|
||||
v0x55fdbe9c9c70_0 .net *"_ivl_5", 0 0, L_0x55fdbe9cde90; 1 drivers
|
||||
v0x55fdbe9c9d50_0 .net *"_ivl_7", 0 0, L_0x55fdbe9cdf30; 1 drivers
|
||||
v0x55fdbe9c9e30_0 .net *"_ivl_9", 0 0, L_0x55fdbe9ce040; 1 drivers
|
||||
v0x55fdbe9c9f10_0 .net "addOverflow", 0 0, L_0x55fdbe9ce5c0; 1 drivers
|
||||
v0x55fdbe9c9fd0_0 .net "detect1", 0 0, L_0x55fdbe9ce9c0; 1 drivers
|
||||
v0x55fdbe9ca090_0 .net "detect2", 0 0, L_0x55fdbe9cea30; 1 drivers
|
||||
v0x55fdbe9ca150_0 .net "opC", 0 0, L_0x55fdbe9cdc50; 1 drivers
|
||||
L_0x7f3602c15018 .functor BUFT 1, C4<10>, C4<0>, C4<0>, C4<0>;
|
||||
v0x55fdbe9ca210_0 .net "opCode", 1 0, L_0x7f3602c15018; 1 drivers
|
||||
v0x55fdbe9ca2f0_0 .net "overflowDetect", 0 0, L_0x55fdbe9ceb90; alias, 1 drivers
|
||||
v0x55fdbe9ca3b0_0 .net "sign1", 0 0, L_0x55fdbe9cde20; 1 drivers
|
||||
v0x55fdbe9ca470_0 .net "sign2", 0 0, L_0x55fdbe9ce370; 1 drivers
|
||||
v0x55fdbe9ca530_0 .net "sign3", 0 0, L_0x55fdbe9cdfd0; 1 drivers
|
||||
v0x55fdbe9ca5f0_0 .net "subOverflow", 0 0, L_0x55fdbe9ce770; 1 drivers
|
||||
L_0x55fdbe9cdce0 .part L_0x7f3602c15018, 0, 1;
|
||||
L_0x55fdbe9cdd80 .part L_0x7f3602c15018, 1, 1;
|
||||
L_0x55fdbe9cde90 .part v0x55fdbe9cae90_0, 3, 1;
|
||||
L_0x55fdbe9cdf30 .part v0x55fdbe9cafc0_0, 3, 1;
|
||||
L_0x55fdbe9ce040 .part v0x55fdbe9cae90_0, 3, 1;
|
||||
L_0x55fdbe9ce130 .part v0x55fdbe9cafc0_0, 3, 1;
|
||||
L_0x55fdbe9ce3e0 .part L_0x55fdbe9cdb40, 3, 1;
|
||||
L_0x55fdbe9ce4d0 .part v0x55fdbe9cae90_0, 3, 1;
|
||||
L_0x55fdbe9ce680 .part L_0x7f3602c15018, 0, 1;
|
||||
L_0x55fdbe9ce870 .part L_0x7f3602c15018, 1, 1;
|
||||
.scope S_0x55fdbe99f210;
|
||||
T_0 ;
|
||||
%vpi_call 2 20 "$dumpfile", "subtraction.vcd" {0 0 0};
|
||||
%vpi_call 2 21 "$dumpvars" {0 0 0};
|
||||
%pushi/vec4 0, 0, 4;
|
||||
%store/vec4 v0x55fdbe9cae90_0, 0, 4;
|
||||
%pushi/vec4 0, 0, 4;
|
||||
%store/vec4 v0x55fdbe9cafc0_0, 0, 4;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x55fdbe9cb0d0_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 6, 0, 4;
|
||||
%store/vec4 v0x55fdbe9cae90_0, 0, 4;
|
||||
%pushi/vec4 2, 0, 4;
|
||||
%store/vec4 v0x55fdbe9cafc0_0, 0, 4;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x55fdbe9cb0d0_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 12, 0, 4;
|
||||
%store/vec4 v0x55fdbe9cae90_0, 0, 4;
|
||||
%pushi/vec4 4, 0, 4;
|
||||
%store/vec4 v0x55fdbe9cafc0_0, 0, 4;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x55fdbe9cb0d0_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 8, 0, 4;
|
||||
%store/vec4 v0x55fdbe9cae90_0, 0, 4;
|
||||
%pushi/vec4 8, 0, 4;
|
||||
%store/vec4 v0x55fdbe9cafc0_0, 0, 4;
|
||||
%pushi/vec4 0, 0, 1;
|
||||
%store/vec4 v0x55fdbe9cb0d0_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%pushi/vec4 15, 0, 4;
|
||||
%store/vec4 v0x55fdbe9cae90_0, 0, 4;
|
||||
%pushi/vec4 1, 0, 4;
|
||||
%store/vec4 v0x55fdbe9cafc0_0, 0, 4;
|
||||
%pushi/vec4 1, 0, 1;
|
||||
%store/vec4 v0x55fdbe9cb0d0_0, 0, 1;
|
||||
%delay 10, 0;
|
||||
%vpi_call 2 34 "$finish" {0 0 0};
|
||||
%end;
|
||||
.thread T_0;
|
||||
.scope S_0x55fdbe99f210;
|
||||
T_1 ;
|
||||
%vpi_call 2 39 "$monitor", "At time %t: A = %b, B = %b, Y = %b, BorrowOut = %b, overflow = %b", $time, v0x55fdbe9cae90_0, v0x55fdbe9cafc0_0, v0x55fdbe9cb210_0, v0x55fdbe9cb170_0, v0x55fdbe9cb350_0 {0 0 0};
|
||||
%end;
|
||||
.thread T_1;
|
||||
# The file index is used to find the file name in the following table.
|
||||
:file_names 7;
|
||||
"N/A";
|
||||
"<interactive>";
|
||||
"subtractionTB.v";
|
||||
"subtraction.v";
|
||||
"fullsubtraction.v";
|
||||
"halfsubtraction.v";
|
||||
"overflowDetect.v";
|
||||
27
project0.2/subtraction.v
Normal file
27
project0.2/subtraction.v
Normal file
@@ -0,0 +1,27 @@
|
||||
module subtraction (
|
||||
input [3:0] A, B,
|
||||
input BorrowIN,
|
||||
output [3:0] Y,
|
||||
output BorrowOut,
|
||||
output overflow
|
||||
);
|
||||
|
||||
wire [3:0] tempB;
|
||||
|
||||
// Full Subtraction logic for each bit (borrow-in for each subsequent bit)
|
||||
fullsubtraction f0 (.A(A[0]), .B(B[0]), .BorrowIN(BorrowIN), .Difference(Y[0]), .BorrowOut(tempB[0]));
|
||||
fullsubtraction f1 (.A(A[1]), .B(B[1]), .BorrowIN(tempB[0]), .Difference(Y[1]), .BorrowOut(tempB[1]));
|
||||
fullsubtraction f2 (.A(A[2]), .B(B[2]), .BorrowIN(tempB[1]), .Difference(Y[2]), .BorrowOut(tempB[2]));
|
||||
fullsubtraction f3 (.A(A[3]), .B(B[3]), .BorrowIN(tempB[2]), .Difference(Y[3]), .BorrowOut(BorrowOut));
|
||||
|
||||
// Overflow detection logic as provided
|
||||
overflowDetect od1 (
|
||||
.opCode(2'b10),
|
||||
.A(A),
|
||||
.B(B),
|
||||
.Y(Y),
|
||||
.CarryOUT(BorrowOut),
|
||||
.overflowDetect(overflow)
|
||||
);
|
||||
|
||||
endmodule
|
||||
312
project0.2/subtraction.vcd
Normal file
312
project0.2/subtraction.vcd
Normal file
@@ -0,0 +1,312 @@
|
||||
$date
|
||||
Fri Dec 20 21:26:28 2024
|
||||
$end
|
||||
$version
|
||||
Icarus Verilog
|
||||
$end
|
||||
$timescale
|
||||
1s
|
||||
$end
|
||||
$scope module subtractionTB $end
|
||||
$var wire 1 ! overflow $end
|
||||
$var wire 4 " Y [3:0] $end
|
||||
$var wire 1 # BorrowOut $end
|
||||
$var reg 4 $ A [3:0] $end
|
||||
$var reg 4 % B [3:0] $end
|
||||
$var reg 1 & BorrowIN $end
|
||||
$scope module uut $end
|
||||
$var wire 4 ' A [3:0] $end
|
||||
$var wire 4 ( B [3:0] $end
|
||||
$var wire 1 & BorrowIN $end
|
||||
$var wire 4 ) tempB [3:0] $end
|
||||
$var wire 1 ! overflow $end
|
||||
$var wire 4 * Y [3:0] $end
|
||||
$var wire 1 # BorrowOut $end
|
||||
$scope module f0 $end
|
||||
$var wire 1 + A $end
|
||||
$var wire 1 , B $end
|
||||
$var wire 1 & BorrowIN $end
|
||||
$var wire 1 - BorrowOut $end
|
||||
$var wire 1 . tempD $end
|
||||
$var wire 1 / tempB2 $end
|
||||
$var wire 1 0 tempB1 $end
|
||||
$var wire 1 1 Difference $end
|
||||
$scope module hf1 $end
|
||||
$var wire 1 + A $end
|
||||
$var wire 1 , B $end
|
||||
$var wire 1 0 Borrow $end
|
||||
$var wire 1 . Difference $end
|
||||
$var wire 1 2 notA $end
|
||||
$upscope $end
|
||||
$scope module hf2 $end
|
||||
$var wire 1 . A $end
|
||||
$var wire 1 & B $end
|
||||
$var wire 1 / Borrow $end
|
||||
$var wire 1 1 Difference $end
|
||||
$var wire 1 3 notA $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module f1 $end
|
||||
$var wire 1 4 A $end
|
||||
$var wire 1 5 B $end
|
||||
$var wire 1 6 BorrowIN $end
|
||||
$var wire 1 7 BorrowOut $end
|
||||
$var wire 1 8 tempD $end
|
||||
$var wire 1 9 tempB2 $end
|
||||
$var wire 1 : tempB1 $end
|
||||
$var wire 1 ; Difference $end
|
||||
$scope module hf1 $end
|
||||
$var wire 1 4 A $end
|
||||
$var wire 1 5 B $end
|
||||
$var wire 1 : Borrow $end
|
||||
$var wire 1 8 Difference $end
|
||||
$var wire 1 < notA $end
|
||||
$upscope $end
|
||||
$scope module hf2 $end
|
||||
$var wire 1 8 A $end
|
||||
$var wire 1 6 B $end
|
||||
$var wire 1 9 Borrow $end
|
||||
$var wire 1 ; Difference $end
|
||||
$var wire 1 = notA $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module f2 $end
|
||||
$var wire 1 > A $end
|
||||
$var wire 1 ? B $end
|
||||
$var wire 1 @ BorrowIN $end
|
||||
$var wire 1 A BorrowOut $end
|
||||
$var wire 1 B tempD $end
|
||||
$var wire 1 C tempB2 $end
|
||||
$var wire 1 D tempB1 $end
|
||||
$var wire 1 E Difference $end
|
||||
$scope module hf1 $end
|
||||
$var wire 1 > A $end
|
||||
$var wire 1 ? B $end
|
||||
$var wire 1 D Borrow $end
|
||||
$var wire 1 B Difference $end
|
||||
$var wire 1 F notA $end
|
||||
$upscope $end
|
||||
$scope module hf2 $end
|
||||
$var wire 1 B A $end
|
||||
$var wire 1 @ B $end
|
||||
$var wire 1 C Borrow $end
|
||||
$var wire 1 E Difference $end
|
||||
$var wire 1 G notA $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module f3 $end
|
||||
$var wire 1 H A $end
|
||||
$var wire 1 I B $end
|
||||
$var wire 1 J BorrowIN $end
|
||||
$var wire 1 # BorrowOut $end
|
||||
$var wire 1 K tempD $end
|
||||
$var wire 1 L tempB2 $end
|
||||
$var wire 1 M tempB1 $end
|
||||
$var wire 1 N Difference $end
|
||||
$scope module hf1 $end
|
||||
$var wire 1 H A $end
|
||||
$var wire 1 I B $end
|
||||
$var wire 1 M Borrow $end
|
||||
$var wire 1 K Difference $end
|
||||
$var wire 1 O notA $end
|
||||
$upscope $end
|
||||
$scope module hf2 $end
|
||||
$var wire 1 K A $end
|
||||
$var wire 1 J B $end
|
||||
$var wire 1 L Borrow $end
|
||||
$var wire 1 N Difference $end
|
||||
$var wire 1 P notA $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module od1 $end
|
||||
$var wire 4 Q A [3:0] $end
|
||||
$var wire 4 R B [3:0] $end
|
||||
$var wire 1 # CarryOUT $end
|
||||
$var wire 4 S Y [3:0] $end
|
||||
$var wire 1 T addOverflow $end
|
||||
$var wire 1 U detect1 $end
|
||||
$var wire 1 V detect2 $end
|
||||
$var wire 1 W opC $end
|
||||
$var wire 2 X opCode [1:0] $end
|
||||
$var wire 1 ! overflowDetect $end
|
||||
$var wire 1 Y sign1 $end
|
||||
$var wire 1 Z sign2 $end
|
||||
$var wire 1 [ sign3 $end
|
||||
$var wire 1 \ subOverflow $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
#0
|
||||
$dumpvars
|
||||
0\
|
||||
0[
|
||||
0Z
|
||||
1Y
|
||||
b10 X
|
||||
1W
|
||||
0V
|
||||
0U
|
||||
0T
|
||||
b0 S
|
||||
b0 R
|
||||
b0 Q
|
||||
1P
|
||||
1O
|
||||
0N
|
||||
0M
|
||||
0L
|
||||
0K
|
||||
0J
|
||||
0I
|
||||
0H
|
||||
1G
|
||||
1F
|
||||
0E
|
||||
0D
|
||||
0C
|
||||
0B
|
||||
0A
|
||||
0@
|
||||
0?
|
||||
0>
|
||||
1=
|
||||
1<
|
||||
0;
|
||||
0:
|
||||
09
|
||||
08
|
||||
07
|
||||
06
|
||||
05
|
||||
04
|
||||
13
|
||||
12
|
||||
01
|
||||
00
|
||||
0/
|
||||
0.
|
||||
0-
|
||||
0,
|
||||
0+
|
||||
b0 *
|
||||
bz000 )
|
||||
b0 (
|
||||
b0 '
|
||||
0&
|
||||
b0 %
|
||||
b0 $
|
||||
0#
|
||||
b0 "
|
||||
0!
|
||||
$end
|
||||
#10
|
||||
b100 "
|
||||
b100 *
|
||||
b100 S
|
||||
1E
|
||||
0G
|
||||
0<
|
||||
1B
|
||||
0F
|
||||
15
|
||||
14
|
||||
1>
|
||||
b10 %
|
||||
b10 (
|
||||
b10 R
|
||||
b110 $
|
||||
b110 '
|
||||
b110 Q
|
||||
#20
|
||||
0!
|
||||
0V
|
||||
1U
|
||||
0E
|
||||
1G
|
||||
b1000 "
|
||||
b1000 *
|
||||
b1000 S
|
||||
1N
|
||||
0P
|
||||
1\
|
||||
0B
|
||||
1<
|
||||
1K
|
||||
0O
|
||||
0Y
|
||||
1[
|
||||
0Z
|
||||
05
|
||||
1?
|
||||
04
|
||||
1H
|
||||
b100 %
|
||||
b100 (
|
||||
b100 R
|
||||
b1100 $
|
||||
b1100 '
|
||||
b1100 Q
|
||||
#30
|
||||
1Z
|
||||
0U
|
||||
b0 "
|
||||
b0 *
|
||||
b0 S
|
||||
0N
|
||||
1P
|
||||
0\
|
||||
0K
|
||||
1Y
|
||||
0[
|
||||
1F
|
||||
0?
|
||||
1I
|
||||
0>
|
||||
b1000 %
|
||||
b1000 (
|
||||
b1000 R
|
||||
b1000 $
|
||||
b1000 '
|
||||
b1000 Q
|
||||
#40
|
||||
0!
|
||||
0Z
|
||||
0V
|
||||
1U
|
||||
16
|
||||
1N
|
||||
0P
|
||||
1\
|
||||
0;
|
||||
0=
|
||||
1E
|
||||
0G
|
||||
bz001 )
|
||||
1-
|
||||
1K
|
||||
0Y
|
||||
1[
|
||||
02
|
||||
18
|
||||
0<
|
||||
1B
|
||||
0F
|
||||
b1101 "
|
||||
b1101 *
|
||||
b1101 S
|
||||
11
|
||||
1/
|
||||
1,
|
||||
0I
|
||||
1+
|
||||
14
|
||||
1>
|
||||
1&
|
||||
b1 %
|
||||
b1 (
|
||||
b1 R
|
||||
b1111 $
|
||||
b1111 '
|
||||
b1111 Q
|
||||
#50
|
||||
42
project0.2/subtractionTB.v
Normal file
42
project0.2/subtractionTB.v
Normal file
@@ -0,0 +1,42 @@
|
||||
module subtractionTB;
|
||||
|
||||
reg [3:0] A, B;
|
||||
reg BorrowIN;
|
||||
wire [3:0] Y;
|
||||
wire BorrowOut;
|
||||
wire overflow;
|
||||
|
||||
// Instantiate the subtraction module
|
||||
subtraction uut (
|
||||
.A(A),
|
||||
.B(B),
|
||||
.BorrowIN(BorrowIN),
|
||||
.Y(Y),
|
||||
.BorrowOut(BorrowOut),
|
||||
.overflow(overflow)
|
||||
);
|
||||
|
||||
initial begin
|
||||
$dumpfile("subtraction.vcd");
|
||||
$dumpvars;
|
||||
// Initialize inputs
|
||||
A = 4'b0000; // Set A to 0
|
||||
B = 4'b0000; // Set B to 0
|
||||
BorrowIN = 0; // No borrow input
|
||||
|
||||
// Apply test cases
|
||||
#10 A = 4'b0110; B = 4'b0010; BorrowIN = 0; // A = 6, B = 2
|
||||
#10 A = 4'b1100; B = 4'b0100; BorrowIN = 0; // A = -4, B = 4
|
||||
#10 A = 4'b1000; B = 4'b1000; BorrowIN = 0; // A = -8, B = -8
|
||||
#10 A = 4'b1111; B = 4'b0001; BorrowIN = 1; // A = -1, B = 1, with borrow input
|
||||
|
||||
// Wait for the results
|
||||
#10 $finish;
|
||||
end
|
||||
|
||||
initial begin
|
||||
// Monitor the values of Y and overflow
|
||||
$monitor("At time %t: A = %b, B = %b, Y = %b, BorrowOut = %b, overflow = %b", $time, A, B, Y, BorrowOut, overflow);
|
||||
end
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user