kaltinsoy/verilog
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

verilog

Browse Source
This commit is contained in:
k0rrluna
2024-05-07 16:15:21 +03:00
parent ed465dd690
commit 492a55d360
44 changed files with 11289 additions and 194 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
lab3/impl/gwsynthesis/lab3_syn_resource.html
View File

@ -30,10 +30,30 @@ table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-co
<th class="label">ROM16 NUMBER</th>
</tr>
<tr>
<td class="label">Adder3Bit (C:/cygwin64/home/koray/verilog/lab3/src/Adder3Bit.v)</td>
<td class="label">mult2bit (C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v)</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">6</td>
<td align = "center">1</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
</tr>
<td class="label">&nbsp&nbsp&nbsp&nbsp|--h0
(C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v)</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">1</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>
</tr>
<td class="label">&nbsp&nbsp&nbsp&nbsp|--h1
(C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v)</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">2</td>
<td align = "center">-</td>
<td align = "center">-</td>
<td align = "center">-</td>