fpga
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@ -83,7 +83,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
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</tr>
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<tr>
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<td class="label">Created Time</td>
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<td>Mon Jan 20 18:31:06 2025
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<td>Tue Jan 21 15:29:14 2025
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</td>
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</tr>
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<tr>
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@ -97,24 +97,24 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
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<tr>
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<td class="label">Place & Route Process</td>
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<td>Running placement:
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Placement Phase 0: CPU time = 0h 0m 0.025s, Elapsed time = 0h 0m 0.025s
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Placement Phase 1: CPU time = 0h 0m 0.346s, Elapsed time = 0h 0m 0.345s
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Placement Phase 2: CPU time = 0h 0m 0.008s, Elapsed time = 0h 0m 0.008s
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Placement Phase 0: CPU time = 0h 0m 0.131s, Elapsed time = 0h 0m 0.131s
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Placement Phase 1: CPU time = 0h 0m 0.403s, Elapsed time = 0h 0m 0.402s
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Placement Phase 2: CPU time = 0h 0m 0.015s, Elapsed time = 0h 0m 0.015s
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Placement Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
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Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
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Running routing:
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Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
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Routing Phase 1: CPU time = 0h 0m 0.178s, Elapsed time = 0h 0m 0.177s
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Routing Phase 2: CPU time = 0h 0m 0.228s, Elapsed time = 0h 0m 0.228s
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Routing Phase 0: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.001s
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Routing Phase 1: CPU time = 0h 0m 0.21s, Elapsed time = 0h 0m 0.21s
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Routing Phase 2: CPU time = 0h 0m 0.263s, Elapsed time = 0h 0m 0.264s
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Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
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Total Routing: CPU time = 0h 0m 0.406s, Elapsed time = 0h 0m 0.405s
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Total Routing: CPU time = 0h 0m 0.475s, Elapsed time = 0h 0m 0.475s
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Generate output files:
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CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s
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CPU time = 0h 0m 5s, Elapsed time = 0h 0m 5s
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</td>
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</tr>
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<tr>
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<td class="label">Total Time and Memory Usage</td>
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<td>CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 433MB</td>
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<td>CPU time = 0h 0m 7s, Elapsed time = 0h 0m 7s, Peak memory usage = 413MB</td>
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</tr>
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</table>
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<br/>
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