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k0rrluna
2025-01-20 18:23:08 +03:00
parent a007343feb
commit 8e613a767e
19 changed files with 1158 additions and 1012 deletions
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110
gowin/bttn/impl/pnr/bttn.rpt.html
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@ -83,7 +83,7 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
</tr>
<tr>
<td class="label">Created Time</td>
<td>Sat Jan 18 22:12:44 2025
<td>Mon Jan 20 17:48:14 2025
</td>
</tr>
<tr>
@ -97,24 +97,24 @@ table.detail_table th.label { min-width: 8%; width: 8%; }
<tr>
<td class="label">Place & Route Process</td>
<td>Running placement:
Placement Phase 0: CPU time = 0h 0m 0.021s, Elapsed time = 0h 0m 0.021s
Placement Phase 1: CPU time = 0h 0m 0.354s, Elapsed time = 0h 0m 0.354s
Placement Phase 2: CPU time = 0h 0m 0.008s, Elapsed time = 0h 0m 0.008s
Placement Phase 0: CPU time = 0h 0m 0.024s, Elapsed time = 0h 0m 0.024s
Placement Phase 1: CPU time = 0h 0m 0.348s, Elapsed time = 0h 0m 0.348s
Placement Phase 2: CPU time = 0h 0m 0.009s, Elapsed time = 0h 0m 0.009s
Placement Phase 3: CPU time = 0h 0m 1s, Elapsed time = 0h 0m 1s
Total Placement: CPU time = 0h 0m 2s, Elapsed time = 0h 0m 2s
Running routing:
Routing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
Routing Phase 1: CPU time = 0h 0m 0.173s, Elapsed time = 0h 0m 0.173s
Routing Phase 2: CPU time = 0h 0m 0.224s, Elapsed time = 0h 0m 0.224s
Routing Phase 2: CPU time = 0h 0m 0.232s, Elapsed time = 0h 0m 0.231s
Routing Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s
Total Routing: CPU time = 0h 0m 0.397s, Elapsed time = 0h 0m 0.397s
Total Routing: CPU time = 0h 0m 0.405s, Elapsed time = 0h 0m 0.404s
Generate output files:
CPU time = 0h 0m 4s, Elapsed time = 0h 0m 4s
</td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 391MB</td>
<td>CPU time = 0h 0m 6s, Elapsed time = 0h 0m 6s, Peak memory usage = 443MB</td>
</tr>
</table>
<br/>
@ -129,12 +129,12 @@ Generate output files:
</tr>
<tr>
<td class="label">Logic</td>
<td>137/20736</td>
<td>141/20736</td>
<td><1%</td>
</tr>
<tr>
<td class="label">&nbsp &nbsp --LUT,ALU,ROM16</td>
<td>137(137 LUT, 0 ALU, 0 ROM16)</td>
<td>141(141 LUT, 0 ALU, 0 ROM16)</td>
<td>-</td>
</tr>
<tr>
@ -169,27 +169,27 @@ Generate output files:
</tr>
<tr>
<td class="label">CLS</td>
<td>74/10368</td>
<td>75/10368</td>
<td><1%</td>
</tr>
<tr>
<td class="label">I/O Port</td>
<td>25</td>
<td>28</td>
<td>-</td>
</tr>
<tr>
<td class="label">I/O Buf</td>
<td>25</td>
<td>28</td>
<td>-</td>
</tr>
<tr>
<td class="label"> &nbsp &nbsp --Input Buf</td>
<td>13</td>
<td>14</td>
<td>-</td>
</tr>
<tr>
<td class="label"> &nbsp &nbsp --Output Buf</td>
<td>12</td>
<td>14</td>
<td>-</td>
</tr>
<tr>
@ -264,7 +264,7 @@ Generate output files:
</tr>
<tr>
<td class="label">bank 1</td>
<td>3/20(15%)</td>
<td>5/20(25%)</td>
</tr>
<tr>
<td class="label">bank 2</td>
@ -284,7 +284,7 @@ Generate output files:
</tr>
<tr>
<td class="label">bank 6</td>
<td>1/18(5%)</td>
<td>2/18(11%)</td>
</tr>
<tr>
<td class="label">bank 7</td>
@ -588,6 +588,60 @@ Generate output files:
<td>1.8</td>
</tr>
<tr>
<td class="label">Cin</td>
<td></td>
<td>E9/6</td>
<td>Y</td>
<td>in</td>
<td>IOL38[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">leds[0]</td>
<td></td>
<td>L16/1</td>
<td>Y</td>
<td>out</td>
<td>IOT34[A]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">leds[1]</td>
<td></td>
<td>L14/1</td>
<td>Y</td>
<td>out</td>
<td>IOT34[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">Y[0]</td>
<td></td>
<td>P6/3</td>
@ -1353,32 +1407,32 @@ Generate output files:
</tr>
<tr>
<td class="label">L16/1</td>
<td>-</td>
<td>in</td>
<td>leds[0]</td>
<td>out</td>
<td>IOT34[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">L14/1</td>
<td>-</td>
<td>in</td>
<td>leds[1]</td>
<td>out</td>
<td>IOT34[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>ON</td>
<td>8</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
@ -3161,7 +3215,7 @@ Generate output files:
</tr>
<tr>
<td class="label">E9/6</td>
<td>-</td>
<td>Cin</td>
<td>in</td>
<td>IOL38[B]</td>
<td>LVCMOS18</td>
@ -3171,7 +3225,7 @@ Generate output files:
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>NA</td>
<td>1.8</td>
</tr>