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verilog

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This commit is contained in:
k0rrluna
2024-07-14 04:03:23 +03:00
parent d71ea508e1
commit 927028192e
73 changed files with 2984 additions and 63 deletions
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tetirs/tb.v Normal file
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module tb();
reg [2:0] parca;
reg clk = 0;
wire [4:0] yukseklik;
wire [4:0] cevrim;
wire bitti_mi;
tetris uut(
.parca(parca),
.clk(clk),
.yukseklik(yukseklik),
.cevrim(cevrim),
.bitti_mi(bitti_mi)
);
always begin
clk = ~clk; #5;
end
initial begin
$dumpvars;
parca = 3'b101; #10;
parca = 3'b000; #10;
parca = 3'b101; #10;
parca = 3'b000; #10;
parca = 3'b101; #10;
parca = 3'b000; #10;
parca = 3'b101; #10;
parca = 3'b000; #10;
parca = 3'b101; #10;
parca = 3'b000; #10;
parca = 3'b101; #10;
parca = 3'b000; #10;
parca = 3'b101; #10;
parca = 3'b000; #10;
parca = 3'b101; #10;
parca = 3'b000; #10;
parca = 3'b101; #10;
parca = 3'b000; #10;
$finish;
end
endmodule