kaltinsoy/verilog
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

verilog

Browse Source
This commit is contained in:
k0rrluna
2024-07-12 23:57:42 +03:00
parent 610e059b8a
commit 997713f8f2
11 changed files with 359 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
gowin/bibp/impl/gwsynthesis/bibp.log Normal file
View File

@ -0,0 +1,14 @@
GowinSynthesis start
Running parser ...
Analyzing Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v'
ERROR (EX3812) : 'buyruk' is not a constant("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":7)
ERROR (EX3812) : 'buyruk' is not a constant("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":8)
ERROR (EX3900) : Procedural assignment to a non-register 'sonuc' is not permitted("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":12)
ERROR (EX3900) : Procedural assignment to a non-register 'sonuc' is not permitted("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":13)
ERROR (EX3900) : Procedural assignment to a non-register 'sonuc' is not permitted("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":14)
ERROR (EX3900) : Procedural assignment to a non-register 'sonuc' is not permitted("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":15)
ERROR (EX3900) : Procedural assignment to a non-register 'sonuc' is not permitted("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":16)
ERROR (EX3900) : Procedural assignment to a non-register 'sonuc' is not permitted("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":17)
ERROR (EX3928) : Module 'bibp' is ignored due to previous errors("\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v":21)
Verilog file '\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v' ignored due to errors
GowinSynthesis finish

19
gowin/bibp/impl/gwsynthesis/bibp.prj Normal file
View File

@ -0,0 +1,19 @@
<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE gowin-synthesis-project>
<Project>
<Version>beta</Version>
<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
<FileList>
<File path="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\src\bibp.v" type="verilog"/>
</FileList>
<OptionList>
<Option type="disable_insert_pad" value="0"/>
<Option type="global_freq" value="100.000"/>
<Option type="looplimit" value="2000"/>
<Option type="output_file" value="\\wsl.localhost\Debian\home\koray\code\verilog\gowin\bibp\impl\gwsynthesis\bibp.vg"/>
<Option type="print_all_synthesis_warning" value="0"/>
<Option type="ram_rw_check" value="0"/>
<Option type="verilog_language" value="verilog-2001"/>
<Option type="vhdl_language" value="vhdl-1993"/>
</OptionList>
</Project>