fpga added
This commit is contained in:
2109
spartanTest/ALU
Normal file
2109
spartanTest/ALU
Normal file
File diff suppressed because it is too large
Load Diff
1074
spartanTest/ALU.vcd
Normal file
1074
spartanTest/ALU.vcd
Normal file
File diff suppressed because it is too large
Load Diff
26
spartanTest/ALUtb.v
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26
spartanTest/ALUtb.v
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@ -0,0 +1,26 @@
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module ALUtb ();
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reg [3:0] A, B;
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reg CarryIN;
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reg [2:0] opCodeA;
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wire [11:0] bcd;
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wire CarryOUT, overflow;
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ALU uut (
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.A(A),
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.B(B),
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.CarryIN(CarryIN),
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.opCodeA(opCodeA),
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.bcd(bcd),
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.CarryOUT(CarryOUT),
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.overflow(overflow)
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);
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initial begin
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$dumpfile("ALU.vcd");
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$dumpvars;
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A = 4'b1100; B = 4'b1100; CarryIN = 1'b0; opCodeA = 3'b010; #5;
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$finish;
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end
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endmodule
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140
spartanTest/selector
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140
spartanTest/selector
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#! /usr/bin/vvp
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:ivl_version "11.0 (stable)";
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:ivl_delay_selection "TYPICAL";
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:vpi_time_precision + 0;
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
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:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
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S_0x558eb92edb80 .scope module, "selectorTB" "selectorTB" 2 1;
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.timescale 0 0;
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v0x558eb9317af0_0 .var "A", 3 0;
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v0x558eb9317bd0_0 .var "ALUY", 7 0;
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v0x558eb9317ca0_0 .var "B", 3 0;
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v0x558eb9317da0_0 .net "Y", 7 0, v0x558eb9317740_0; 1 drivers
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v0x558eb9317e70_0 .var "opCodeA", 2 0;
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v0x558eb9317f60_0 .var "select", 1 0;
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S_0x558eb9302140 .scope module, "uut" "selector" 2 9, 3 1 0, S_0x558eb92edb80;
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.timescale 0 0;
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.port_info 0 /INPUT 4 "A";
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.port_info 1 /INPUT 4 "B";
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.port_info 2 /INPUT 3 "opCodeA";
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.port_info 3 /INPUT 2 "select";
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.port_info 4 /INPUT 8 "ALUY";
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.port_info 5 /OUTPUT 8 "Y";
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v0x558eb9302350_0 .net "A", 3 0, v0x558eb9317af0_0; 1 drivers
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v0x558eb93175a0_0 .net "ALUY", 7 0, v0x558eb9317bd0_0; 1 drivers
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v0x558eb9317680_0 .net "B", 3 0, v0x558eb9317ca0_0; 1 drivers
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v0x558eb9317740_0 .var "Y", 7 0;
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v0x558eb9317820_0 .net "opCodeA", 2 0, v0x558eb9317e70_0; 1 drivers
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v0x558eb9317950_0 .net "select", 1 0, v0x558eb9317f60_0; 1 drivers
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E_0x558eb93001f0/0 .event edge, v0x558eb9317950_0, v0x558eb9302350_0, v0x558eb9317680_0, v0x558eb9317820_0;
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E_0x558eb93001f0/1 .event edge, v0x558eb93175a0_0;
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E_0x558eb93001f0 .event/or E_0x558eb93001f0/0, E_0x558eb93001f0/1;
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.scope S_0x558eb9302140;
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T_0 ;
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%wait E_0x558eb93001f0;
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%load/vec4 v0x558eb9317950_0;
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%dup/vec4;
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%pushi/vec4 0, 0, 2;
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%cmp/u;
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%jmp/1 T_0.0, 6;
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%dup/vec4;
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%pushi/vec4 1, 0, 2;
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%cmp/u;
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%jmp/1 T_0.1, 6;
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%dup/vec4;
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%pushi/vec4 2, 0, 2;
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%cmp/u;
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%jmp/1 T_0.2, 6;
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%dup/vec4;
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%pushi/vec4 3, 0, 2;
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%cmp/u;
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%jmp/1 T_0.3, 6;
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%pushi/vec4 0, 0, 8;
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%store/vec4 v0x558eb9317740_0, 0, 8;
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%jmp T_0.5;
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T_0.0 ;
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%pushi/vec4 0, 0, 4;
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%load/vec4 v0x558eb9302350_0;
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%concat/vec4; draw_concat_vec4
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%store/vec4 v0x558eb9317740_0, 0, 8;
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%jmp T_0.5;
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T_0.1 ;
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%pushi/vec4 0, 0, 4;
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%load/vec4 v0x558eb9317680_0;
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%concat/vec4; draw_concat_vec4
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%store/vec4 v0x558eb9317740_0, 0, 8;
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%jmp T_0.5;
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T_0.2 ;
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%pushi/vec4 0, 0, 5;
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%load/vec4 v0x558eb9317820_0;
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%concat/vec4; draw_concat_vec4
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%store/vec4 v0x558eb9317740_0, 0, 8;
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%jmp T_0.5;
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T_0.3 ;
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%load/vec4 v0x558eb93175a0_0;
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%store/vec4 v0x558eb9317740_0, 0, 8;
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%jmp T_0.5;
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T_0.5 ;
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%pop/vec4 1;
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%jmp T_0;
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.thread T_0, $push;
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.scope S_0x558eb92edb80;
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T_1 ;
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%vpi_call 2 19 "$dumpfile", "selector.vcd" {0 0 0};
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%vpi_call 2 20 "$dumpvars" {0 0 0};
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%pushi/vec4 1, 0, 4;
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%store/vec4 v0x558eb9317af0_0, 0, 4;
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%pushi/vec4 2, 0, 4;
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%store/vec4 v0x558eb9317ca0_0, 0, 4;
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%pushi/vec4 7, 0, 3;
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%store/vec4 v0x558eb9317e70_0, 0, 3;
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%pushi/vec4 240, 0, 8;
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%store/vec4 v0x558eb9317bd0_0, 0, 8;
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%pushi/vec4 0, 0, 2;
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%store/vec4 v0x558eb9317f60_0, 0, 2;
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%delay 5, 0;
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%pushi/vec4 1, 0, 4;
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%store/vec4 v0x558eb9317af0_0, 0, 4;
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%pushi/vec4 2, 0, 4;
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%store/vec4 v0x558eb9317ca0_0, 0, 4;
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%pushi/vec4 7, 0, 3;
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%store/vec4 v0x558eb9317e70_0, 0, 3;
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%pushi/vec4 240, 0, 8;
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%store/vec4 v0x558eb9317bd0_0, 0, 8;
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%pushi/vec4 1, 0, 2;
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%store/vec4 v0x558eb9317f60_0, 0, 2;
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%delay 5, 0;
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%pushi/vec4 1, 0, 4;
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%store/vec4 v0x558eb9317af0_0, 0, 4;
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%pushi/vec4 2, 0, 4;
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%store/vec4 v0x558eb9317ca0_0, 0, 4;
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%pushi/vec4 7, 0, 3;
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%store/vec4 v0x558eb9317e70_0, 0, 3;
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%pushi/vec4 112, 0, 8;
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%store/vec4 v0x558eb9317bd0_0, 0, 8;
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%pushi/vec4 2, 0, 2;
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%store/vec4 v0x558eb9317f60_0, 0, 2;
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%delay 5, 0;
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%pushi/vec4 1, 0, 4;
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%store/vec4 v0x558eb9317af0_0, 0, 4;
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%pushi/vec4 2, 0, 4;
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%store/vec4 v0x558eb9317ca0_0, 0, 4;
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%pushi/vec4 7, 0, 3;
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%store/vec4 v0x558eb9317e70_0, 0, 3;
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%pushi/vec4 112, 0, 8;
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%store/vec4 v0x558eb9317bd0_0, 0, 8;
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%pushi/vec4 3, 0, 2;
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%store/vec4 v0x558eb9317f60_0, 0, 2;
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%delay 5, 0;
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%vpi_call 2 25 "$finish" {0 0 0};
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%end;
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.thread T_1;
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# The file index is used to find the file name in the following table.
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:file_names 4;
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"N/A";
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"<interactive>";
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"selectorTB.v";
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"selector.v";
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@ -1,68 +1,20 @@
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module selector (
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input [3:0] select,
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input [7:0] Y,
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input [3:0] A, B,
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input [3:0] A,
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input [3:0] B,
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input [2:0] opCodeA,
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output [7:0] s0
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input [1:0] select,
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input [7:0] ALUY,
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output reg [7:0] Y
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);
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wire [3:0] a0, b0, tempAB, tempYO;
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wire [7:0] y0;
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wire [2:0] op0;
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wire tempsO, temps;
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// Select signals for A
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and a00 (a0[0], select[0], A[0]);
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and a01 (a0[1], select[0], A[1]);
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and a02 (a0[2], select[0], A[2]);
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and a03 (a0[3], select[0], A[3]);
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// Select signals for B
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and b00 (b0[0], select[1], B[0]);
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and b01 (b0[1], select[1], B[1]);
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and b02 (b0[2], select[1], B[2]);
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and b03 (b0[3], select[1], B[3]);
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// Select signals for Y
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and y00 (y0[0], select[2], Y[0]);
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and y01 (y0[1], select[2], Y[1]);
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and y02 (y0[2], select[2], Y[2]);
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and y03 (y0[3], select[2], Y[3]);
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and y04 (y0[4], select[2], Y[4]);
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and y05 (y0[5], select[2], Y[5]);
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and y06 (y0[6], select[2], Y[6]);
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and y07 (y0[7], select[2], Y[7]);
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// Select signals for opCodeA
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and op00 (op0[0], select[3], opCodeA[0]);
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and op01 (op0[1], select[3], opCodeA[1]);
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and op02 (op0[2], select[3], opCodeA[2]);
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// Combine A and B
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or or1 (tempAB[0], a0[0], b0[0]);
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or or2 (tempAB[1], a0[1], b0[1]);
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or or3 (tempAB[2], a0[2], b0[2]);
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or or4 (tempAB[3], a0[3], b0[3]);
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// Combine Y and opCodeA
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or or5 (tempYO[0], y0[0], op0[0]);
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or or6 (tempYO[1], y0[1], op0[1]);
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or or7 (tempYO[2], y0[2], op0[2]);
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or or8 (tempYO[3], y0[3], 1'b0);
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// NOR for select logic
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nor s01 (tempsO, select[0], select[1]);
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nor s02 (temps, tempsO, select[3]);
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// Final s0 connections
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or or9 (s0[0], tempAB[0], tempYO[0]);
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or or10 (s0[1], tempAB[1], tempYO[1]);
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or or11 (s0[2], tempAB[2], tempYO[2]);
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or or12 (s0[3], tempAB[3], tempYO[3]);
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and and13 (s0[4], y0[4], temps);
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and and14 (s0[5], y0[5], temps);
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and and15 (s0[6], y0[6], temps);
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and and16 (s0[7], y0[7], temps);
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always @(*) begin
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case (select)
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2'b00: Y = {4'b0000, A}; // Zero-extend A to 8 bits
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2'b01: Y = {4'b0000, B}; // Zero-extend B to 8 bits
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2'b10: Y = {5'b00000, opCodeA}; // Zero-extend opCodeA to 8 bits
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2'b11: Y = ALUY; // Directly assign ALUY
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default: Y = 8'b00000000; // Default case for safety
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endcase
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end
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endmodule
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59
spartanTest/selector.vcd
Normal file
59
spartanTest/selector.vcd
Normal file
@ -0,0 +1,59 @@
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$date
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Sat Jan 18 17:21:23 2025
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$end
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$version
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Icarus Verilog
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$end
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$timescale
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1s
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$end
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$scope module selectorTB $end
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$var wire 8 ! Y [7:0] $end
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$var reg 4 " A [3:0] $end
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$var reg 8 # ALUY [7:0] $end
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$var reg 4 $ B [3:0] $end
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$var reg 3 % opCodeA [2:0] $end
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$var reg 2 & select [1:0] $end
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$scope module uut $end
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$var wire 4 ' A [3:0] $end
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$var wire 8 ( ALUY [7:0] $end
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$var wire 4 ) B [3:0] $end
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$var wire 3 * opCodeA [2:0] $end
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$var wire 2 + select [1:0] $end
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$var reg 8 , Y [7:0] $end
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$upscope $end
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$upscope $end
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$enddefinitions $end
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#0
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$dumpvars
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b1 ,
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b0 +
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b111 *
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b10 )
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b11110000 (
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b1 '
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b0 &
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b111 %
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b10 $
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b11110000 #
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b1 "
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b1 !
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$end
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#5
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b10 !
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b10 ,
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b1 &
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b1 +
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#10
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b111 !
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b111 ,
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b10 &
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b10 +
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b1110000 #
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b1110000 (
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#15
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b1110000 !
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b1110000 ,
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b11 &
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b11 +
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#20
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@ -1,25 +1,27 @@
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module selectorTB();
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reg [3:0] select, A, B;
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reg [7:0] Y;
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reg [1:0] select;
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reg [3:0] A, B;
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reg [7:0] ALUY;
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reg [2:0] opCodeA;
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wire [7:0] s0;
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wire [7:0] Y;
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selector uut (
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.select(select),
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.A(A),
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.B(B),
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.opCodeA(opCodeA),
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.s0(s0)
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.ALUY(ALUY),
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.Y(Y)
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);
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initial begin
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$dumpfile("selector.vcd");
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$dumpvars;
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A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; Y = 8'b1111_0000; select = 4'b0010; #5;
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A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; Y = 8'b1111_0000; select = 4'b0001; #5;
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A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; Y = 8'b0111_0000; select = 4'b0100; #5;
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A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; Y = 8'b0111_0000; select = 4'b1000; #5;
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A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; ALUY = 8'b1111_0000; select = 2'b00; #5;
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A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; ALUY = 8'b1111_0000; select = 2'b01; #5;
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A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; ALUY = 8'b0111_0000; select = 2'b10; #5;
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A = 4'b0001; B = 4'b0010; opCodeA = 3'b111; ALUY = 8'b0111_0000; select = 2'b11; #5;
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$finish;
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end
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|
||||
|
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Reference in New Issue
Block a user