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nand2Tetris

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k0rrluna
2024-12-01 13:42:54 +03:00
parent 0237c7bcb2
commit a69386c7b4
14 changed files with 274 additions and 17 deletions
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27
iverilog/nand2tetris/nands/notGate.vcd Normal file
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$date
Sun Dec 1 02:50:52 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module notGateTB $end
$var wire 1 ! B $end
$var reg 1 " A $end
$scope module uut $end
$var wire 1 " A $end
$var wire 1 ! B $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
0"
1!
$end
#10
0!
1"
#20