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nand2tetris

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This commit is contained in:
k0rrluna
2024-12-10 01:25:05 +03:00
parent 2acbfd9d8d
commit c1d75786ef
31 changed files with 1058 additions and 24 deletions
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58
iverilog/nand2tetris/nands/and/andGate Normal file
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#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x56317b794200 .scope module, "andGateTB" "andGateTB" 2 1;
.timescale 0 0;
v0x56317b7a5140_0 .var "A_i", 0 0;
v0x56317b7a5210_0 .var "B_i", 0 0;
v0x56317b7a52e0_0 .net "Y_o", 0 0, L_0x56317b7a5520; 1 drivers
S_0x56317b794390 .scope module, "uut" "andGate" 2 5, 3 1 0, S_0x56317b794200;
.timescale 0 0;
.port_info 0 /INPUT 1 "A_i";
.port_info 1 /INPUT 1 "B_i";
.port_info 2 /OUTPUT 1 "Y_o";
L_0x56317b7a53e0 .functor NAND 1, v0x56317b7a5140_0, v0x56317b7a5210_0, C4<1>, C4<1>;
L_0x56317b7a5520 .functor NAND 1, L_0x56317b7a53e0, L_0x56317b7a53e0, C4<1>, C4<1>;
v0x56317b75cc00_0 .net "A_i", 0 0, v0x56317b7a5140_0; 1 drivers
v0x56317b7a4ea0_0 .net "B_i", 0 0, v0x56317b7a5210_0; 1 drivers
v0x56317b7a4f60_0 .net "Y_o", 0 0, L_0x56317b7a5520; alias, 1 drivers
v0x56317b7a5000_0 .net "nand_out", 0 0, L_0x56317b7a53e0; 1 drivers
.scope S_0x56317b794200;
T_0 ;
%vpi_call 2 12 "$dumpfile", "andGate.vcd" {0 0 0};
%vpi_call 2 13 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56317b7a5140_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56317b7a5210_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56317b7a5140_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x56317b7a5210_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x56317b7a5140_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x56317b7a5210_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x56317b7a5140_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x56317b7a5210_0, 0, 1;
%delay 10, 0;
%vpi_call 2 26 "$finish" {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"andGateTB.v";
"andGate.v";

12
iverilog/nand2tetris/nands/and/andGate.v Normal file
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module andGate (
input A_i,
input B_i,
output Y_o
);
wire nand_out;
nand nand1 (nand_out, A_i, B_i);
nand nand2 (Y_o, nand_out, nand_out);
endmodule

38
iverilog/nand2tetris/nands/and/andGate.vcd Normal file
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$date
Mon Dec 9 23:49:40 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module andGateTB $end
$var wire 1 ! Y_o $end
$var reg 1 " A_i $end
$var reg 1 # B_i $end
$scope module uut $end
$var wire 1 " A_i $end
$var wire 1 # B_i $end
$var wire 1 ! Y_o $end
$var wire 1 $ nand_out $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
1$
0#
0"
0!
$end
#10
1#
#20
0#
1"
#30
1!
0$
1#
#40

29
iverilog/nand2tetris/nands/and/andGateTB.v Normal file
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module andGateTB ();
reg A_i, B_i;
wire Y_o;
andGate uut (
.A_i(A_i),
.B_i(B_i),
.Y_o(Y_o)
);
initial begin
$dumpfile("andGate.vcd");
$dumpvars;
A_i = 1'b0;
B_i = 1'b0;
#10;
A_i = 1'b0;
B_i = 1'b1;
#10;
A_i = 1'b1;
B_i = 1'b0;
#10;
A_i = 1'b1;
B_i = 1'b1;
#10;
$finish;
end
endmodule