kaltinsoy/verilog
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

nand2tetris

Browse Source
This commit is contained in:
k0rrluna
2024-12-10 01:25:05 +03:00
parent 2acbfd9d8d
commit c1d75786ef
31 changed files with 1058 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files

66
iverilog/nand2tetris/nands/dmux/dmuxGate Normal file
View File

@ -0,0 +1,66 @@
#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55e3e0602d50 .scope module, "dmuxGateTB" "dmuxGateTB" 2 1;
.timescale 0 0;
v0x55e3e0628ba0_0 .var "A_i", 0 0;
v0x55e3e0628c60_0 .var "S_i", 0 0;
v0x55e3e0628d30_0 .net "Y0_o", 0 0, L_0x55e3e0629100; 1 drivers
v0x55e3e0628e30_0 .net "Y1_o", 0 0, L_0x55e3e06292b0; 1 drivers
S_0x55e3e0617050 .scope module, "uut" "dmuxGate" 2 5, 3 1 0, S_0x55e3e0602d50;
.timescale 0 0;
.port_info 0 /INPUT 1 "A_i";
.port_info 1 /INPUT 1 "S_i";
.port_info 2 /OUTPUT 1 "Y0_o";
.port_info 3 /OUTPUT 1 "Y1_o";
L_0x55e3e0628f00 .functor NAND 1, v0x55e3e0628c60_0, v0x55e3e0628c60_0, C4<1>, C4<1>;
L_0x55e3e0628ff0 .functor NAND 1, L_0x55e3e0628f00, v0x55e3e0628ba0_0, C4<1>, C4<1>;
L_0x55e3e0629100 .functor NAND 1, L_0x55e3e0628ff0, L_0x55e3e0628ff0, C4<1>, C4<1>;
L_0x55e3e0629210 .functor NAND 1, v0x55e3e0628c60_0, v0x55e3e0628ba0_0, C4<1>, C4<1>;
L_0x55e3e06292b0 .functor NAND 1, L_0x55e3e0629210, L_0x55e3e0629210, C4<1>, C4<1>;
v0x55e3e06172a0_0 .net "A_i", 0 0, v0x55e3e0628ba0_0; 1 drivers
v0x55e3e0628640_0 .net "S_i", 0 0, v0x55e3e0628c60_0; 1 drivers
v0x55e3e0628700_0 .net "Y0_o", 0 0, L_0x55e3e0629100; alias, 1 drivers
v0x55e3e06287d0_0 .net "Y1_o", 0 0, L_0x55e3e06292b0; alias, 1 drivers
v0x55e3e0628890_0 .net "nand2_out", 0 0, L_0x55e3e0628ff0; 1 drivers
v0x55e3e06289a0_0 .net "nand4_out", 0 0, L_0x55e3e0629210; 1 drivers
v0x55e3e0628a60_0 .net "notS", 0 0, L_0x55e3e0628f00; 1 drivers
.scope S_0x55e3e0602d50;
T_0 ;
%vpi_call 2 13 "$dumpfile", "dmuxGate.vcd" {0 0 0};
%vpi_call 2 14 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55e3e0628ba0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55e3e0628c60_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55e3e0628ba0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55e3e0628c60_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55e3e0628ba0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55e3e0628c60_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55e3e0628ba0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55e3e0628c60_0, 0, 1;
%delay 10, 0;
%vpi_call 2 20 "$finish" {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"dmuxGateTB.v";
"dmuxGate.v";

16
iverilog/nand2tetris/nands/dmux/dmuxGate.v Normal file
View File

@ -0,0 +1,16 @@
module dmuxGate(
input A_i, S_i,
output Y0_o, Y1_o
);
wire notS, nand2_out, nand4_out;
nand nand1(notS, S_i, S_i);
nand nand2(nand2_out, notS, A_i);
nand nand3(Y0_o, nand2_out, nand2_out);
nand nand4(nand4_out, S_i, A_i);
nand nand5(Y1_o, nand4_out, nand4_out);
endmodule

50
iverilog/nand2tetris/nands/dmux/dmuxGate.vcd Normal file
View File

@ -0,0 +1,50 @@
$date
Tue Dec 10 00:15:58 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module dmuxGateTB $end
$var wire 1 ! Y1_o $end
$var wire 1 " Y0_o $end
$var reg 1 # A_i $end
$var reg 1 $ S_i $end
$scope module uut $end
$var wire 1 # A_i $end
$var wire 1 $ S_i $end
$var wire 1 " Y0_o $end
$var wire 1 ! Y1_o $end
$var wire 1 % nand2_out $end
$var wire 1 & nand4_out $end
$var wire 1 ' notS $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
1'
1&
1%
0$
0#
0"
0!
$end
#10
1"
0%
1#
#20
0"
0'
1%
1$
0#
#30
1!
0&
1#
#40

23
iverilog/nand2tetris/nands/dmux/dmuxGateTB.v Normal file
View File

@ -0,0 +1,23 @@
module dmuxGateTB();
reg A_i, S_i;
wire Y0_o, Y1_o;
dmuxGate uut(
.A_i(A_i),
.S_i(S_i),
.Y0_o(Y0_o),
.Y1_o(Y1_o)
);
initial begin
$dumpfile("dmuxGate.vcd");
$dumpvars;
A_i = 1'b0; S_i = 1'b0; #10;
A_i = 1'b1; S_i = 1'b0; #10;
A_i = 1'b0; S_i = 1'b1; #10;
A_i = 1'b1; S_i = 1'b1; #10;
$finish;
end
endmodule