nand2tetris

iverilog/nand2tetris/nands/not/notGate

@@ -0,0 +1,39 @@
+#! /usr/bin/vvp
+:ivl_version "11.0 (stable)";
+:ivl_delay_selection "TYPICAL";
+:vpi_time_precision + 0;
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
+:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
+S_0x56057d7feb60 .scope module, "notGateTB" "notGateTB" 2 1;
+ .timescale 0 0;
+v0x56057d80ddd0_0 .var "A_i", 0 0;
+v0x56057d80de70_0 .net "B_o", 0 0, L_0x56057d80df40;  1 drivers
+S_0x56057d7fecf0 .scope module, "uut" "notGate" 2 6, 3 1 0, S_0x56057d7feb60;
+ .timescale 0 0;
+    .port_info 0 /INPUT 1 "A_i";
+    .port_info 1 /OUTPUT 1 "B_o";
+L_0x56057d80df40 .functor NAND 1, v0x56057d80ddd0_0, v0x56057d80ddd0_0, C4<1>, C4<1>;
+v0x56057d7c77f0_0 .net "A_i", 0 0, v0x56057d80ddd0_0;  1 drivers
+v0x56057d7c7c00_0 .net "B_o", 0 0, L_0x56057d80df40;  alias, 1 drivers
+    .scope S_0x56057d7feb60;
+T_0 ;
+    %vpi_call 2 12 "$dumpfile", "notGate.vcd" {0 0 0};
+    %vpi_call 2 13 "$dumpvars" {0 0 0};
+    %pushi/vec4 0, 0, 1;
+    %store/vec4 v0x56057d80ddd0_0, 0, 1;
+    %delay 10, 0;
+    %pushi/vec4 1, 0, 1;
+    %store/vec4 v0x56057d80ddd0_0, 0, 1;
+    %delay 10, 0;
+    %vpi_call 2 18 "$finish" {0 0 0};
+    %end;
+    .thread T_0;
+# The file index is used to find the file name in the following table.
+:file_names 4;
+    "N/A";
+    "<interactive>";
+    "notGateTB.v";
+    "notGate.v";

iverilog/nand2tetris/nands/not/notGate.v

@@ -0,0 +1,7 @@
+module notGate (
+    input  A_i,
+    output B_o
+);
+
+   nand nand1 (B_o, A_i, A_i);
+endmodule

iverilog/nand2tetris/nands/not/notGate.vcd

@@ -0,0 +1,27 @@
+$date
+	Mon Dec  9 22:38:49 2024
+$end
+$version
+	Icarus Verilog
+$end
+$timescale
+	1s
+$end
+$scope module notGateTB $end
+$var wire 1 ! B_o $end
+$var reg 1 " A_i $end
+$scope module uut $end
+$var wire 1 " A_i $end
+$var wire 1 ! B_o $end
+$upscope $end
+$upscope $end
+$enddefinitions $end
+#0
+$dumpvars
+0"
+1!
+$end
+#10
+0!
+1"
+#20

iverilog/nand2tetris/nands/not/notGateTB.v

@@ -0,0 +1,20 @@
+module notGateTB;
+
+    reg  A_i;
+    wire B_o;
+
+    notGate uut (
+        .A_i(A_i),
+        .B_o(B_o)
+    );
+
+    initial begin
+        $dumpfile("notGate.vcd");
+        $dumpvars;
+        A_i = 1'b0;
+        #10;
+        A_i = 1'b1;
+        #10;
+        $finish;
+    end
+endmodule