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nand2tetris

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This commit is contained in:
k0rrluna
2024-12-10 01:25:05 +03:00
parent 2acbfd9d8d
commit c1d75786ef
31 changed files with 1058 additions and 24 deletions
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60
iverilog/nand2tetris/nands/or/orGate Normal file
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#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55778f5946b0 .scope module, "orGateTB" "orGateTB" 2 1;
.timescale 0 0;
v0x55778f5a58d0_0 .var "A_i", 0 0;
v0x55778f5a5970_0 .var "B_i", 0 0;
v0x55778f5a5a40_0 .net "F_o", 0 0, L_0x55778f5a5cf0; 1 drivers
S_0x55778f594840 .scope module, "uut" "orGate" 2 5, 3 1 0, S_0x55778f5946b0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A_i";
.port_info 1 /INPUT 1 "B_i";
.port_info 2 /OUTPUT 1 "F_o";
L_0x55778f5a5b40 .functor NAND 1, v0x55778f5a58d0_0, v0x55778f5a58d0_0, C4<1>, C4<1>;
L_0x55778f5a5c30 .functor NAND 1, v0x55778f5a5970_0, v0x55778f5a5970_0, C4<1>, C4<1>;
L_0x55778f5a5cf0 .functor NAND 1, L_0x55778f5a5b40, L_0x55778f5a5c30, C4<1>, C4<1>;
v0x55778f581720_0 .net "A_i", 0 0, v0x55778f5a58d0_0; 1 drivers
v0x55778f5a5520_0 .net "B_i", 0 0, v0x55778f5a5970_0; 1 drivers
v0x55778f5a55e0_0 .net "F_o", 0 0, L_0x55778f5a5cf0; alias, 1 drivers
v0x55778f5a5680_0 .net "nand1_out", 0 0, L_0x55778f5a5b40; 1 drivers
v0x55778f5a5740_0 .net "nand2_out", 0 0, L_0x55778f5a5c30; 1 drivers
.scope S_0x55778f5946b0;
T_0 ;
%vpi_call 2 12 "$dumpfile", "orGate.vcd" {0 0 0};
%vpi_call 2 13 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55778f5a58d0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55778f5a5970_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55778f5a58d0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55778f5a5970_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55778f5a58d0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55778f5a5970_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55778f5a58d0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55778f5a5970_0, 0, 1;
%delay 10, 0;
%vpi_call 2 18 "$finish" {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"orGateTB.v";
"orGate.v";

13
iverilog/nand2tetris/nands/or/orGate.v Normal file
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module orGate (
input A_i,
input B_i,
output F_o
);
wire nand1_out, nand2_out;
nand nand1 (nand1_out, A_i, A_i);
nand nand2 (nand2_out, B_i, B_i);
nand nand3 (F_o, nand1_out, nand2_out);
endmodule

43
iverilog/nand2tetris/nands/or/orGate.vcd Normal file
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$date
Mon Dec 9 22:45:31 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module orGateTB $end
$var wire 1 ! F_o $end
$var reg 1 " A_i $end
$var reg 1 # B_i $end
$scope module uut $end
$var wire 1 " A_i $end
$var wire 1 # B_i $end
$var wire 1 ! F_o $end
$var wire 1 $ nand1_out $end
$var wire 1 % nand2_out $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
1%
1$
0#
0"
0!
$end
#10
1!
0%
1#
#20
1%
0$
0#
1"
#30
0%
1#
#40

21
iverilog/nand2tetris/nands/or/orGateTB.v Normal file
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module orGateTB();
reg A_i, B_i;
wire F_o;
orGate uut(
.A_i(A_i),
.B_i(B_i),
.F_o(F_o)
);
initial begin
$dumpfile("orGate.vcd");
$dumpvars;
A_i = 1'b0; B_i = 1'b0; #10;
A_i = 1'b0; B_i = 1'b1; #10;
A_i = 1'b1; B_i = 1'b0; #10;
A_i = 1'b1; B_i = 1'b1; #10;
$finish;
end
endmodule