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nand2tetris

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This commit is contained in:
k0rrluna
2024-12-10 01:25:05 +03:00
parent 2acbfd9d8d
commit c1d75786ef
31 changed files with 1058 additions and 24 deletions
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62
iverilog/nand2tetris/nands/xor/xorGate Normal file
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#! /usr/bin/vvp
:ivl_version "11.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/system.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_sys.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/vhdl_textio.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/v2005_math.vpi";
:vpi_module "/usr/lib/x86_64-linux-gnu/ivl/va_math.vpi";
S_0x55594b700b30 .scope module, "xorGateTB" "xorGateTB" 2 1;
.timescale 0 0;
v0x55594b712090_0 .var "A_i", 0 0;
v0x55594b712130_0 .var "B_i", 0 0;
v0x55594b712200_0 .net "F_o", 0 0, L_0x55594b712570; 1 drivers
S_0x55594b700cc0 .scope module, "uut" "xorGate" 2 5, 3 1 0, S_0x55594b700b30;
.timescale 0 0;
.port_info 0 /INPUT 1 "A_i";
.port_info 1 /INPUT 1 "B_i";
.port_info 2 /OUTPUT 1 "F_o";
L_0x55594b712300 .functor NAND 1, v0x55594b712090_0, v0x55594b712130_0, C4<1>, C4<1>;
L_0x55594b712440 .functor NAND 1, v0x55594b712090_0, L_0x55594b712300, C4<1>, C4<1>;
L_0x55594b712500 .functor NAND 1, v0x55594b712130_0, L_0x55594b712300, C4<1>, C4<1>;
L_0x55594b712570 .functor NAND 1, L_0x55594b712500, L_0x55594b712440, C4<1>, C4<1>;
v0x55594b6eda80_0 .net "A_i", 0 0, v0x55594b712090_0; 1 drivers
v0x55594b711c20_0 .net "B_i", 0 0, v0x55594b712130_0; 1 drivers
v0x55594b711ce0_0 .net "F_o", 0 0, L_0x55594b712570; alias, 1 drivers
v0x55594b711d80_0 .net "nand1_out", 0 0, L_0x55594b712300; 1 drivers
v0x55594b711e40_0 .net "nand2_out", 0 0, L_0x55594b712440; 1 drivers
v0x55594b711f50_0 .net "nand3_out", 0 0, L_0x55594b712500; 1 drivers
.scope S_0x55594b700b30;
T_0 ;
%vpi_call 2 12 "$dumpfile", "xorGate.vcd" {0 0 0};
%vpi_call 2 13 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55594b712090_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55594b712130_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55594b712090_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55594b712130_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55594b712090_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0x55594b712130_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55594b712090_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0x55594b712130_0, 0, 1;
%delay 10, 0;
%vpi_call 2 18 "$finish" {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"xorGateTB.v";
"xorGate.v";

14
iverilog/nand2tetris/nands/xor/xorGate.v Normal file
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module xorGate (
input A_i,
input B_i,
output F_o
);
wire nand1_out, nand2_out, nand3_out;
nand nand1(nand1_out, A_i, B_i);
nand nand2(nand2_out, A_i, nand1_out);
nand nand3(nand3_out, B_i, nand1_out);
nand nand4(F_o, nand3_out, nand2_out);
endmodule

48
iverilog/nand2tetris/nands/xor/xorGate.vcd Normal file
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$date
Mon Dec 9 22:56:38 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module xorGateTB $end
$var wire 1 ! F_o $end
$var reg 1 " A_i $end
$var reg 1 # B_i $end
$scope module uut $end
$var wire 1 " A_i $end
$var wire 1 # B_i $end
$var wire 1 ! F_o $end
$var wire 1 $ nand1_out $end
$var wire 1 % nand2_out $end
$var wire 1 & nand3_out $end
$upscope $end
$upscope $end
$enddefinitions $end
#0
$dumpvars
1&
1%
1$
0#
0"
0!
$end
#10
1!
0&
1#
#20
1&
0%
0#
1"
#30
0!
1%
0$
1&
1#
#40

21
iverilog/nand2tetris/nands/xor/xorGateTB.v Normal file
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module xorGateTB();
reg A_i, B_i;
wire F_o;
xorGate uut(
.A_i(A_i),
.B_i(B_i),
.F_o(F_o)
);
initial begin
$dumpfile("xorGate.vcd");
$dumpvars;
A_i = 1'b0; B_i = 1'b0; #10;
A_i = 1'b0; B_i = 1'b1; #10;
A_i = 1'b1; B_i = 1'b0; #10;
A_i = 1'b1; B_i = 1'b1; #10;
$finish;
end
endmodule