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verilog

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k0rrluna
2024-07-05 19:15:16 +03:00
parent 492a55d360
commit c1f0851a45
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bit3-ledTest/halfadder.v Normal file
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module halfadder(
input A,B,
output S,C
);
xor (S, A, B);
and (C, A, B);
endmodule