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verilog

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This commit is contained in:
k0rrluna
2024-07-05 19:15:16 +03:00
parent 492a55d360
commit c1f0851a45
136 changed files with 11599 additions and 0 deletions
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19
labs/lab2/src/BitM.v Normal file
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module BitM(
input A,
input B,
output AlB,
output AeB,
output AgB
);
wire An, Bn;
not n1 (An, A);
not n2 (Bn, B);
and a1 (AlB, An, B);
and a2 (AgB, Bn, A);
nor nor1 (AeB, AlB, AgB);
endmodule

26
labs/lab2/src/BitM_tb.v Normal file
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module BitM_tb();
reg r1, r2;
wire w1, w2, w3;
BitM uut(
.A(r1),
.B(r2),
.AlB(w1),
.AeB(w2),
.AgB(w3)
);
initial begin
$dumpfile("bdmp.vcd");
$dumpvars;
r1 = 0; r2 = 0; #10
r1 = 0; r2 = 1; #10
r1 = 1; r2 = 0; #10
r1 = 1; r2 = 1; #10
$display(w1);
$display(w2);
$display(w3);
end
endmodule

58
labs/lab2/src/bdmp.vcd Normal file
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$date
Thu Apr 11 07:50:26 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module BitM_tb $end
$var wire 1 ! w3 $end
$var wire 1 " w2 $end
$var wire 1 # w1 $end
$var reg 1 $ r1 $end
$var reg 1 % r2 $end
$scope module uut $end
$var wire 1 $ A $end
$var wire 1 " AeB $end
$var wire 1 ! AgB $end
$var wire 1 # AlB $end
$var wire 1 & An $end
$var wire 1 % B $end
$var wire 1 ' Bn $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
$end
#0
$dumpvars
1'
1&
0%
0$
0#
1"
0!
$end
#10
0"
0'
1#
1%
#20
1!
0"
1'
0#
0&
0%
1$
#30
1"
0!
0'
1%
#40

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#! /c/Source/iverilog-install/bin/vvp
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
S_000002114102cad0 .scope module, "BitM_tb" "BitM_tb" 2 1;
.timescale 0 0;
v0000021140f146e0_0 .var "r1", 0 0;
v0000021140f14780_0 .var "r2", 0 0;
v0000021140f14820_0 .net "w1", 0 0, L_0000021140ee32f0; 1 drivers
v0000021140f148c0_0 .net "w2", 0 0, L_0000021140f14f60; 1 drivers
v0000021140f14960_0 .net "w3", 0 0, L_0000021140f14de0; 1 drivers
S_000002114102cc60 .scope module, "uut" "BitM" 2 6, 3 1 0, S_000002114102cad0;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "AlB";
.port_info 3 /OUTPUT 1 "AeB";
.port_info 4 /OUTPUT 1 "AgB";
L_000002114102af60 .functor NOT 1, v0000021140f146e0_0, C4<0>, C4<0>, C4<0>;
L_0000021140ee3190 .functor NOT 1, v0000021140f14780_0, C4<0>, C4<0>, C4<0>;
L_0000021140ee32f0 .functor AND 1, L_000002114102af60, v0000021140f14780_0, C4<1>, C4<1>;
L_0000021140f14de0 .functor AND 1, L_0000021140ee3190, v0000021140f146e0_0, C4<1>, C4<1>;
L_0000021140f14f60 .functor NOR 1, L_0000021140ee32f0, L_0000021140f14de0, C4<0>, C4<0>;
v0000021141028fc0_0 .net "A", 0 0, v0000021140f146e0_0; 1 drivers
v0000021140ee2ee0_0 .net "AeB", 0 0, L_0000021140f14f60; alias, 1 drivers
v000002114102aec0_0 .net "AgB", 0 0, L_0000021140f14de0; alias, 1 drivers
v000002114102cdf0_0 .net "AlB", 0 0, L_0000021140ee32f0; alias, 1 drivers
v000002114102ce90_0 .net "An", 0 0, L_000002114102af60; 1 drivers
v0000021140f145a0_0 .net "B", 0 0, v0000021140f14780_0; 1 drivers
v0000021140f14640_0 .net "Bn", 0 0, L_0000021140ee3190; 1 drivers
.scope S_000002114102cad0;
T_0 ;
%vpi_call 2 15 "$dumpfile", "bdmp.vcd" {0 0 0};
%vpi_call 2 16 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v0000021140f146e0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0000021140f14780_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v0000021140f146e0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0000021140f14780_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0000021140f146e0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v0000021140f14780_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v0000021140f146e0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v0000021140f14780_0, 0, 1;
%delay 10, 0;
%vpi_call 2 21 "$display", v0000021140f14820_0 {0 0 0};
%vpi_call 2 22 "$display", v0000021140f148c0_0 {0 0 0};
%vpi_call 2 23 "$display", v0000021140f14960_0 {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"BitM_tb.v";
"BitM.v";

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$date
Thu Apr 11 06:36:34 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module tb $end
$var wire 1 ! w2 $end
$var wire 1 " w1 $end
$var reg 1 # r1 $end
$var reg 1 $ r2 $end
$scope module uut $end
$var wire 1 # A $end
$var wire 1 $ B $end
$var wire 1 ! C $end
$var wire 1 " S $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
$end
#0
$dumpvars
0$
0#
0"
0!
$end
#20
1"
1#
#40
1$
0#
#60
0"
1!
1#
#80

75
labs/lab2/src/fdmp.vcd Normal file
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$date
Thu Apr 11 07:39:27 2024
$end
$version
Icarus Verilog
$end
$timescale
1s
$end
$scope module ftb $end
$var wire 1 ! w2 $end
$var wire 1 " w1 $end
$var reg 1 # r1 $end
$var reg 1 $ r2 $end
$var reg 1 % r3 $end
$scope module uut $end
$var wire 1 # A $end
$var wire 1 & AB $end
$var wire 1 ' ABCin $end
$var wire 1 ( AaB $end
$var wire 1 $ B $end
$var wire 1 % Cin $end
$var wire 1 ! Cout $end
$var wire 1 " S $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
$end
#0
$dumpvars
0(
0'
0&
0%
0$
0#
0"
0!
$end
#10
1"
1%
#20
1&
0%
1$
#30
1!
0"
1'
1%
#40
0!
1"
0'
0%
0$
1#
#50
1!
0"
1'
1%
#60
0'
0&
1(
0%
1$
#70
1"
1%
#80

106
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#! /c/Source/iverilog-install/bin/vvp
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
S_000001da0354ad70 .scope module, "ftb" "ftb" 2 1;
.timescale 0 0;
v000001da035dc840_0 .var "r1", 0 0;
v000001da035dc8e0_0 .var "r2", 0 0;
v000001da035dc980_0 .var "r3", 0 0;
v000001da035dca20_0 .net "w1", 0 0, L_000001da03594080; 1 drivers
v000001da035935f0_0 .net "w2", 0 0, L_000001da03594470; 1 drivers
S_000001da0354e9e0 .scope module, "uut" "fullAdder" 2 6, 3 1 0, S_000001da0354ad70;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /INPUT 1 "Cin";
.port_info 3 /OUTPUT 1 "S";
.port_info 4 /OUTPUT 1 "Cout";
L_000001da03594010 .functor XOR 1, v000001da035dc840_0, v000001da035dc8e0_0, C4<0>, C4<0>;
L_000001da03594080 .functor XOR 1, L_000001da03594010, v000001da035dc980_0, C4<0>, C4<0>;
L_000001da03593e50 .functor AND 1, L_000001da03594010, v000001da035dc980_0, C4<1>, C4<1>;
L_000001da035940f0 .functor AND 1, v000001da035dc840_0, v000001da035dc8e0_0, C4<1>, C4<1>;
L_000001da03594470 .functor OR 1, L_000001da03593e50, L_000001da035940f0, C4<0>, C4<0>;
v000001da03563310_0 .net "A", 0 0, v000001da035dc840_0; 1 drivers
v000001da03562ee0_0 .net "AB", 0 0, L_000001da03594010; 1 drivers
v000001da0354af00_0 .net "ABCin", 0 0, L_000001da03593e50; 1 drivers
v000001da03549850_0 .net "AaB", 0 0, L_000001da035940f0; 1 drivers
v000001da0354eb70_0 .net "B", 0 0, v000001da035dc8e0_0; 1 drivers
v000001da0354ec10_0 .net "Cin", 0 0, v000001da035dc980_0; 1 drivers
v000001da0354ecb0_0 .net "Cout", 0 0, L_000001da03594470; alias, 1 drivers
v000001da0354ed50_0 .net "S", 0 0, L_000001da03594080; alias, 1 drivers
.scope S_000001da0354ad70;
T_0 ;
%vpi_call 2 15 "$dumpfile", "fdmp.vcd" {0 0 0};
%vpi_call 2 16 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v000001da035dc840_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001da035dc8e0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001da035dc980_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001da035dc840_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001da035dc8e0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001da035dc980_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001da035dc840_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001da035dc8e0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001da035dc980_0, 0, 1;
%delay 10, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001da035dc840_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001da035dc8e0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001da035dc980_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001da035dc840_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001da035dc8e0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001da035dc980_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001da035dc840_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001da035dc8e0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001da035dc980_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001da035dc840_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001da035dc8e0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001da035dc980_0, 0, 1;
%delay 10, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001da035dc840_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001da035dc8e0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001da035dc980_0, 0, 1;
%delay 10, 0;
%vpi_call 2 25 "$display", v000001da035dca20_0 {0 0 0};
%vpi_call 2 26 "$display", v000001da035935f0_0 {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"ftb.v";
"fullAdder.v";

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module ftb ();
reg r1, r2, r3;
wire w1, w2;
fullAdder uut(
.A(r1),
.B(r2),
.Cin(r3),
.S(w1),
.Cout(w2)
);
initial begin
$dumpfile("fdmp.vcd");
$dumpvars;
r1 = 0; r2 = 0; r3 = 0; #10
r1 = 0; r2 = 0; r3 = 1; #10
r1 = 0; r2 = 1; r3 = 0; #10
r1 = 0; r2 = 1; r3 = 1; #10
r1 = 1; r2 = 0; r3 = 0; #10
r1 = 1; r2 = 0; r3 = 1; #10
r1 = 1; r2 = 1; r3 = 0; #10
r1 = 1; r2 = 1; r3 = 1; #10
$display(w1);
$display(w2);
end
endmodule

20
labs/lab2/src/fullAdder.v Normal file
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module fullAdder(
input A,
input B,
input Cin,
output S,
output Cout
);
wire AB;
wire ABCin, AaB;
xor (AB, A, B);
xor (S, AB, Cin);
and (ABCin, AB, Cin);
and (AaB, A, B);
or (Cout, ABCin, AaB);
endmodule

11
labs/lab2/src/halfAdder.v Normal file
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module halfAdder(
input A,
input B,
output S,
output C
);
xor (S, A, B);
and (C, A, B);
endmodule

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#! /c/Source/iverilog-install/bin/vvp
:ivl_version "12.0 (devel)" "(s20150603-1539-g2693dd32b)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "C:\iverilog\lib\ivl\system.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_sys.vpi";
:vpi_module "C:\iverilog\lib\ivl\vhdl_textio.vpi";
:vpi_module "C:\iverilog\lib\ivl\v2005_math.vpi";
:vpi_module "C:\iverilog\lib\ivl\va_math.vpi";
S_000001b4458eec80 .scope module, "tb" "tb" 2 1;
.timescale 0 0;
v000001b4458ec1d0_0 .var "r1", 0 0;
v000001b4458ec270_0 .var "r2", 0 0;
v000001b4458ec310_0 .net "w1", 0 0, L_000001b445783190; 1 drivers
v000001b4458ec3b0_0 .net "w2", 0 0, L_000001b4457832f0; 1 drivers
S_000001b4458eee10 .scope module, "uut" "halfAdder" 2 6, 3 1 0, S_000001b4458eec80;
.timescale 0 0;
.port_info 0 /INPUT 1 "A";
.port_info 1 /INPUT 1 "B";
.port_info 2 /OUTPUT 1 "S";
.port_info 3 /OUTPUT 1 "C";
L_000001b445783190 .functor XOR 1, v000001b4458ec1d0_0, v000001b4458ec270_0, C4<0>, C4<0>;
L_000001b4457832f0 .functor AND 1, v000001b4458ec1d0_0, v000001b4458ec270_0, C4<1>, C4<1>;
v000001b4458ebff0_0 .net "A", 0 0, v000001b4458ec1d0_0; 1 drivers
v000001b445782ee0_0 .net "B", 0 0, v000001b4458ec270_0; 1 drivers
v000001b4458ec090_0 .net "C", 0 0, L_000001b4457832f0; alias, 1 drivers
v000001b4458ec130_0 .net "S", 0 0, L_000001b445783190; alias, 1 drivers
.scope S_000001b4458eec80;
T_0 ;
%vpi_call 2 14 "$dumpfile", "dmp.vcd" {0 0 0};
%vpi_call 2 15 "$dumpvars" {0 0 0};
%pushi/vec4 0, 0, 1;
%store/vec4 v000001b4458ec1d0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001b4458ec270_0, 0, 1;
%delay 20, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001b4458ec1d0_0, 0, 1;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001b4458ec270_0, 0, 1;
%delay 20, 0;
%pushi/vec4 0, 0, 1;
%store/vec4 v000001b4458ec1d0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001b4458ec270_0, 0, 1;
%delay 20, 0;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001b4458ec1d0_0, 0, 1;
%pushi/vec4 1, 0, 1;
%store/vec4 v000001b4458ec270_0, 0, 1;
%delay 20, 0;
%vpi_call 2 20 "$display", v000001b4458ec310_0 {0 0 0};
%vpi_call 2 21 "$display", v000001b4458ec3b0_0 {0 0 0};
%end;
.thread T_0;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"tb.v";
"halfAdder.v";

24
labs/lab2/src/tb.v Normal file
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module tb();
reg r1, r2;
wire w1, w2;
halfAdder uut(
.A(r1),
.B(r2),
.S(w1),
.C(w2)
);
initial begin
$dumpfile("dmp.vcd");
$dumpvars;
r1 = 0; r2 = 0; #20
r1 = 1; r2 = 0; #20
r1 = 0; r2 = 1; #20
r1 = 1; r2 = 1; #20
$display(w1);
$display(w2);
end
endmodule