verilog
This commit is contained in:
40
labs/lab2_prep/impl/gwsynthesis/lab2.log
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40
labs/lab2_prep/impl/gwsynthesis/lab2.log
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GowinSynthesis start
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Running parser ...
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Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab2\src\lab2.v'
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Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab2\src\tb.v'
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Compiling module 'tb'("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":1)
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WARN (EX3858) : System task 'dumpfile' is ignored for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":17)
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WARN (EX3858) : System task 'dumpvars' is ignored for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":18)
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WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":19)
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WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":20)
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WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":21)
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WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":22)
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WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":23)
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WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":24)
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WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":25)
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WARN (EX2629) : Delay control is not supported for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":26)
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WARN (EX3858) : System task 'display' is ignored for synthesis("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":27)
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WARN (EX3780) : Using initial value of 'r1' since it is never assigned("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":28)
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Compiling module 'lab2'("C:\cygwin64\home\koray\verilog\lab2\src\lab2.v":1)
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NOTE (EX0101) : Current top module is "tb"
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WARN (EX0203) : Top module "tb" has no ports("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":1)
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[5%] Running netlist conversion ...
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Running device independent optimization ...
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[10%] Optimizing Phase 0 completed
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[15%] Optimizing Phase 1 completed
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[25%] Optimizing Phase 2 completed
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Running inference ...
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[30%] Inferring Phase 0 completed
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[40%] Inferring Phase 1 completed
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[50%] Inferring Phase 2 completed
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[55%] Inferring Phase 3 completed
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Running technical mapping ...
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[60%] Tech-Mapping Phase 0 completed
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[65%] Tech-Mapping Phase 1 completed
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[75%] Tech-Mapping Phase 2 completed
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[80%] Tech-Mapping Phase 3 completed
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[90%] Tech-Mapping Phase 4 completed
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WARN (NL0002) : The module "lab2" instantiated to "uut" is swept in optimizing("C:\cygwin64\home\koray\verilog\lab2\src\tb.v":12)
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[95%] Generate netlist file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2.vg" completed
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[100%] Generate report file "C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2_syn.rpt.html" completed
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GowinSynthesis finish
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20
labs/lab2_prep/impl/gwsynthesis/lab2.prj
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20
labs/lab2_prep/impl/gwsynthesis/lab2.prj
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<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE gowin-synthesis-project>
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<Project>
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<Version>beta</Version>
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<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
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<FileList>
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<File path="C:\cygwin64\home\koray\verilog\lab2\src\lab2.v" type="verilog"/>
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<File path="C:\cygwin64\home\koray\verilog\lab2\src\tb.v" type="verilog"/>
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</FileList>
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<OptionList>
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<Option type="disable_insert_pad" value="0"/>
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<Option type="global_freq" value="100.000"/>
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<Option type="looplimit" value="2000"/>
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<Option type="output_file" value="C:\cygwin64\home\koray\verilog\lab2\impl\gwsynthesis\lab2.vg"/>
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<Option type="print_all_synthesis_warning" value="0"/>
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<Option type="ram_rw_check" value="0"/>
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<Option type="verilog_language" value="verilog-2001"/>
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<Option type="vhdl_language" value="vhdl-1993"/>
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</OptionList>
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</Project>
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25
labs/lab2_prep/impl/gwsynthesis/lab2.vg
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25
labs/lab2_prep/impl/gwsynthesis/lab2.vg
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//
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//Written by GowinSynthesis
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//Tool Version "V1.9.9.02"
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//Thu Apr 11 06:15:18 2024
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//Source file index table:
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//file0 "\C:/cygwin64/home/koray/verilog/lab2/src/lab2.v"
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//file1 "\C:/cygwin64/home/koray/verilog/lab2/src/tb.v"
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`timescale 100 ps/100 ps
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module tb (
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)
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;
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wire VCC;
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wire GND;
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VCC VCC_cZ (
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.V(VCC)
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);
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GND GND_cZ (
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.G(GND)
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);
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GSR GSR (
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.GSRI(VCC)
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);
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endmodule /* tb */
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144
labs/lab2_prep/impl/gwsynthesis/lab2_syn.rpt.html
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144
labs/lab2_prep/impl/gwsynthesis/lab2_syn.rpt.html
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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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<html>
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<head>
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<title>synthesis Report</title>
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<style type="text/css">
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body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
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div#main_wrapper{ width: 100%; }
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div#content { margin-left: 350px; margin-right: 30px; }
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div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
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div#catalog ul { list-style-type: none; }
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||||
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
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||||
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
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||||
div#catalog a:visited { color: #0084ff; }
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||||
div#catalog a:hover { color: #fff; background: #0084ff; }
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hr { margin-top: 30px; margin-bottom: 30px; }
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h1, h3 { text-align: center; }
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h1 {margin-top: 50px; }
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table, th, td { border: 1px solid #aaa; }
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||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
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th, td { padding: 5px 5px 5px 5px; }
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||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
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table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
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table.detail_table td.label { min-width: 100px; width: 8%;}
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||||
</style>
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||||
</head>
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||||
<body>
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||||
<div id="main_wrapper">
|
||||
<div id="catalog_wrapper">
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||||
<div id="catalog">
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||||
<ul>
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||||
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
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<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
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<li><a href="#resource" style=" font-size: 16px;">Resource</a>
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||||
<ul>
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<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
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||||
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
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||||
</ul>
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||||
</li>
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||||
</ul>
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</div><!-- catalog -->
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</div><!-- catalog_wrapper -->
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<div id="content">
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<h1><a name="about">Synthesis Messages</a></h1>
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<table class="summary_table">
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<tr>
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<td class="label">Report Title</td>
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<td>GowinSynthesis Report</td>
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</tr>
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||||
<tr>
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<td class="label">Design File</td>
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<td>C:\cygwin64\home\koray\verilog\lab2\src\lab2.v<br>
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C:\cygwin64\home\koray\verilog\lab2\src\tb.v<br>
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</td>
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</tr>
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<tr>
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<td class="label">GowinSynthesis Constraints File</td>
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<td>---</td>
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</tr>
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<tr>
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<td class="label">Tool Version</td>
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<td>V1.9.9.02</td>
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</tr>
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<tr>
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<td class="label">Part Number</td>
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<td>GW2A-LV18PG256C8/I7</td>
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</tr>
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<tr>
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<td class="label">Device</td>
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<td>GW2A-18</td>
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</tr>
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<tr>
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<td class="label">Device Version</td>
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<td>C</td>
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</tr>
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<tr>
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<td class="label">Created Time</td>
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<td>Thu Apr 11 06:15:18 2024
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</td>
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</tr>
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<tr>
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<td class="label">Legal Announcement</td>
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<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
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</tr>
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</table>
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<h1><a name="summary">Synthesis Details</a></h1>
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<table class="summary_table">
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<tr>
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<td class="label">Top Level Module</td>
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<td>tb</td>
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</tr>
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<tr>
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<td class="label">Synthesis Process</td>
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<td>Running parser:<br/> CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.148s, Peak memory usage = 184.680MB<br/>Running netlist conversion:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/> Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>Running inference:<br/> Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>Running technical mapping:<br/> Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/> Tech-Mapping Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.058s, Peak memory usage = 184.680MB<br/> Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 184.680MB<br/>Generate output files:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 184.680MB<br/></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Total Time and Memory Usage</td>
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||||
<td>CPU time = 0h 0m 0.14s, Elapsed time = 0h 0m 0.208s, Peak memory usage = 184.680MB</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="resource">Resource</a></h1>
|
||||
<h2><a name="usage">Resource Usage Summary</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label"><b>Resource</b></td>
|
||||
<td><b>Usage</b></td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="utilization">Resource Utilization Summary</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label"><b>Resource</b></td>
|
||||
<td><b>Usage</b></td>
|
||||
<td><b>Utilization</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Logic</td>
|
||||
<td>0(0 LUT, 0 ALU) / 20736</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Register</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">  --Register as Latch</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">  --Register as FF</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">BSRAM</td>
|
||||
<td>0 / 46</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
||||
46
labs/lab2_prep/impl/gwsynthesis/lab2_syn_resource.html
Normal file
46
labs/lab2_prep/impl/gwsynthesis/lab2_syn_resource.html
Normal file
@ -0,0 +1,46 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>Hierarchy Module Resource</title>
|
||||
<style type="text/css">
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
|
||||
div#main_wrapper{ width: 100%; }
|
||||
h1 {text-align: center; }
|
||||
h1 {margin-top: 36px; }
|
||||
table, th, td { border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { align = "center"; padding: 5px 2px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="main_wrapper">
|
||||
<div id="content">
|
||||
<h1>Hierarchy Module Resource</h1>
|
||||
<table>
|
||||
<tr>
|
||||
<th class="label">MODULE NAME</th>
|
||||
<th class="label">REG NUMBER</th>
|
||||
<th class="label">ALU NUMBER</th>
|
||||
<th class="label">LUT NUMBER</th>
|
||||
<th class="label">DSP NUMBER</th>
|
||||
<th class="label">BSRAM NUMBER</th>
|
||||
<th class="label">SSRAM NUMBER</th>
|
||||
<th class="label">ROM16 NUMBER</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">tb (C:/cygwin64/home/koray/verilog/lab2/src/tb.v)</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
||||
2
labs/lab2_prep/impl/gwsynthesis/lab2_syn_rsc.xml
Normal file
2
labs/lab2_prep/impl/gwsynthesis/lab2_syn_rsc.xml
Normal file
@ -0,0 +1,2 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Module name="tb"/>
|
||||
88
labs/lab2_prep/impl/lab2_process_config.json
Normal file
88
labs/lab2_prep/impl/lab2_process_config.json
Normal file
@ -0,0 +1,88 @@
|
||||
{
|
||||
"BACKGROUND_PROGRAMMING" : "off",
|
||||
"COMPRESS" : false,
|
||||
"CPU" : false,
|
||||
"CRC_CHECK" : true,
|
||||
"Clock_Route_Order" : 0,
|
||||
"Correct_Hold_Violation" : true,
|
||||
"DONE" : false,
|
||||
"DOWNLOAD_SPEED" : "default",
|
||||
"Disable_Insert_Pad" : false,
|
||||
"ENABLE_CTP" : false,
|
||||
"ENABLE_MERGE_MODE" : false,
|
||||
"ENCRYPTION_KEY" : false,
|
||||
"ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
|
||||
"ERROR_DECTION_AND_CORRECTION" : false,
|
||||
"ERROR_DECTION_ONLY" : false,
|
||||
"ERROR_INJECTION" : false,
|
||||
"EXTERNAL_MASTER_CONFIG_CLOCK" : false,
|
||||
"Enable_DSRM" : false,
|
||||
"FORMAT" : "binary",
|
||||
"FREQUENCY_DIVIDER" : "",
|
||||
"Generate_Constraint_File_of_Ports" : false,
|
||||
"Generate_IBIS_File" : false,
|
||||
"Generate_Plain_Text_Timing_Report" : false,
|
||||
"Generate_Post_PNR_Simulation_Model_File" : false,
|
||||
"Generate_Post_Place_File" : false,
|
||||
"Generate_SDF_File" : false,
|
||||
"Generate_VHDL_Post_PNR_Simulation_Model_File" : false,
|
||||
"Global_Freq" : "default",
|
||||
"GwSyn_Loop_Limit" : 2000,
|
||||
"HOTBOOT" : false,
|
||||
"I2C" : false,
|
||||
"I2C_SLAVE_ADDR" : "00",
|
||||
"IncludePath" : [
|
||||
|
||||
],
|
||||
"Incremental_Compile" : "",
|
||||
"Initialize_Primitives" : false,
|
||||
"JTAG" : false,
|
||||
"MODE_IO" : false,
|
||||
"MSPI" : false,
|
||||
"MSPI_JUMP" : false,
|
||||
"MULTIBOOT_ADDRESS_WIDTH" : "24",
|
||||
"MULTIBOOT_MODE" : "Normal",
|
||||
"MULTIBOOT_SPI_FLASH_ADDRESS" : "00000000",
|
||||
"MULTIJUMP_ADDRESS_WIDTH" : "24",
|
||||
"MULTIJUMP_MODE" : "Normal",
|
||||
"MULTIJUMP_SPI_FLASH_ADDRESS" : "000000",
|
||||
"Multi_Boot" : true,
|
||||
"OUTPUT_BASE_NAME" : "lab2",
|
||||
"POWER_ON_RESET_MONITOR" : true,
|
||||
"PRINT_BSRAM_VALUE" : true,
|
||||
"PROGRAM_DONE_BYPASS" : false,
|
||||
"PlaceInRegToIob" : true,
|
||||
"PlaceIoRegToIob" : true,
|
||||
"PlaceOutRegToIob" : true,
|
||||
"Place_Option" : "0",
|
||||
"Process_Configuration_Verion" : "1.0",
|
||||
"Promote_Physical_Constraint_Warning_to_Error" : true,
|
||||
"READY" : false,
|
||||
"RECONFIG_N" : false,
|
||||
"Ram_RW_Check" : false,
|
||||
"Replicate_Resources" : false,
|
||||
"Report_Auto-Placed_Io_Information" : false,
|
||||
"Route_Maxfan" : 23,
|
||||
"Route_Option" : "0",
|
||||
"Run_Timing_Driven" : true,
|
||||
"SECURE_MODE" : false,
|
||||
"SECURITY_BIT" : true,
|
||||
"SEU_HANDLER" : false,
|
||||
"SEU_HANDLER_CHECKSUM" : false,
|
||||
"SEU_HANDLER_MODE" : "auto",
|
||||
"SSPI" : false,
|
||||
"STOP_SEU_HANDLER" : false,
|
||||
"Show_All_Warnings" : false,
|
||||
"Synthesize_tool" : "GowinSyn",
|
||||
"TclPre" : "",
|
||||
"TopModule" : "",
|
||||
"USERCODE" : "default",
|
||||
"Unused_Pin" : "As_input_tri_stated_with_pull_up",
|
||||
"VCCAUX" : 3.3,
|
||||
"VCCX" : "3.3",
|
||||
"VHDL_Standard" : "VHDL_Std_1993",
|
||||
"Verilog_Standard" : "Vlg_Std_2001",
|
||||
"WAKE_UP" : "0",
|
||||
"show_all_warnings" : false,
|
||||
"turn_off_bg" : false
|
||||
}
|
||||
20
labs/lab2_prep/impl/temp/rtl_parser.result
Normal file
20
labs/lab2_prep/impl/temp/rtl_parser.result
Normal file
@ -0,0 +1,20 @@
|
||||
[
|
||||
{
|
||||
"InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
|
||||
"InstLine" : 1,
|
||||
"InstName" : "tb",
|
||||
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "tb",
|
||||
"SubInsts" : [
|
||||
{
|
||||
"InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
|
||||
"InstLine" : 6,
|
||||
"InstName" : "uut",
|
||||
"ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/lab2.v",
|
||||
"ModuleLine" : 1,
|
||||
"ModuleName" : "lab2"
|
||||
}
|
||||
]
|
||||
}
|
||||
]
|
||||
21
labs/lab2_prep/impl/temp/rtl_parser_arg.json
Normal file
21
labs/lab2_prep/impl/temp/rtl_parser_arg.json
Normal file
@ -0,0 +1,21 @@
|
||||
{
|
||||
"Device" : "GW2A-18C",
|
||||
"Files" : [
|
||||
{
|
||||
"Path" : "C:/cygwin64/home/koray/verilog/lab2/src/lab2.v",
|
||||
"Type" : "verilog"
|
||||
},
|
||||
{
|
||||
"Path" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
|
||||
"Type" : "verilog"
|
||||
}
|
||||
],
|
||||
"IncludePath" : [
|
||||
|
||||
],
|
||||
"LoopLimit" : 2000,
|
||||
"ResultFile" : "C:/cygwin64/home/koray/verilog/lab2/impl/temp/rtl_parser.result",
|
||||
"Top" : "",
|
||||
"VerilogStd" : "verilog_2001",
|
||||
"VhdlStd" : "vhdl_93"
|
||||
}
|
||||
Reference in New Issue
Block a user