verilog

2024-07-05 19:15:16 +03:00
parent 492a55d360
commit c1f0851a45
136 changed files with 11599 additions and 0 deletions
--- a/labs/lab2_prep/impl/temp/rtl_parser.result
+++ b/labs/lab2_prep/impl/temp/rtl_parser.result
@ -0,0 +1,20 @@
+[
+ {
+  "InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
+  "InstLine" : 1,
+  "InstName" : "tb",
+  "ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
+  "ModuleLine" : 1,
+  "ModuleName" : "tb",
+  "SubInsts" : [
+   {
+    "InstFile" : "C:/cygwin64/home/koray/verilog/lab2/src/tb.v",
+    "InstLine" : 6,
+    "InstName" : "uut",
+    "ModuleFile" : "C:/cygwin64/home/koray/verilog/lab2/src/lab2.v",
+    "ModuleLine" : 1,
+    "ModuleName" : "lab2"
+   }
+  ]
+ }
+]