verilog
This commit is contained in:
27
labs/lab3/impl/gwsynthesis/lab3.log
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27
labs/lab3/impl/gwsynthesis/lab3.log
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GowinSynthesis start
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Running parser ...
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Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\fullAdder.v'
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Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\halfAdder.v'
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Analyzing Verilog file 'C:\cygwin64\home\koray\verilog\lab3\src\mult2bit.v'
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Compiling module 'mult2bit'("C:\cygwin64\home\koray\verilog\lab3\src\mult2bit.v":1)
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Compiling module 'halfAdder'("C:\cygwin64\home\koray\verilog\lab3\src\halfAdder.v":1)
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NOTE (EX0101) : Current top module is "mult2bit"
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[5%] Running netlist conversion ...
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Running device independent optimization ...
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[10%] Optimizing Phase 0 completed
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[15%] Optimizing Phase 1 completed
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[25%] Optimizing Phase 2 completed
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Running inference ...
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[30%] Inferring Phase 0 completed
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[40%] Inferring Phase 1 completed
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[50%] Inferring Phase 2 completed
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[55%] Inferring Phase 3 completed
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Running technical mapping ...
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[60%] Tech-Mapping Phase 0 completed
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[65%] Tech-Mapping Phase 1 completed
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[75%] Tech-Mapping Phase 2 completed
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[80%] Tech-Mapping Phase 3 completed
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[90%] Tech-Mapping Phase 4 completed
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[95%] Generate netlist file "C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg" completed
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[100%] Generate report file "C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3_syn.rpt.html" completed
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GowinSynthesis finish
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21
labs/lab3/impl/gwsynthesis/lab3.prj
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21
labs/lab3/impl/gwsynthesis/lab3.prj
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<?xml version="1.0" encoding="UTF-8"?>
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<!DOCTYPE gowin-synthesis-project>
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<Project>
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<Version>beta</Version>
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<Device id="GW2A-18C" package="PBGA256" speed="8" partNumber="GW2A-LV18PG256C8/I7"/>
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<FileList>
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<File path="C:\cygwin64\home\koray\verilog\lab3\src\fullAdder.v" type="verilog"/>
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<File path="C:\cygwin64\home\koray\verilog\lab3\src\halfAdder.v" type="verilog"/>
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<File path="C:\cygwin64\home\koray\verilog\lab3\src\mult2bit.v" type="verilog"/>
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</FileList>
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<OptionList>
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<Option type="disable_insert_pad" value="0"/>
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<Option type="global_freq" value="100.000"/>
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<Option type="looplimit" value="2000"/>
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<Option type="output_file" value="C:\cygwin64\home\koray\verilog\lab3\impl\gwsynthesis\lab3.vg"/>
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<Option type="print_all_synthesis_warning" value="0"/>
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<Option type="ram_rw_check" value="0"/>
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||||
<Option type="verilog_language" value="verilog-2001"/>
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<Option type="vhdl_language" value="vhdl-1993"/>
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</OptionList>
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</Project>
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144
labs/lab3/impl/gwsynthesis/lab3.vg
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144
labs/lab3/impl/gwsynthesis/lab3.vg
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//
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//Written by GowinSynthesis
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//Tool Version "V1.9.9.02"
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//Sat May 4 01:07:38 2024
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//Source file index table:
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//file0 "\C:/cygwin64/home/koray/verilog/lab3/src/fullAdder.v"
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//file1 "\C:/cygwin64/home/koray/verilog/lab3/src/halfAdder.v"
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//file2 "\C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v"
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`timescale 100 ps/100 ps
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module halfAdder (
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A_d,
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B_d,
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C_d
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)
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;
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input [1:0] A_d;
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input [1:0] B_d;
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output [1:1] C_d;
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wire VCC;
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wire GND;
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LUT4 C_d_1_s (
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.F(C_d[1]),
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.I0(A_d[1]),
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.I1(B_d[0]),
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.I2(A_d[0]),
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.I3(B_d[1])
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);
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defparam C_d_1_s.INIT=16'h7888;
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VCC VCC_cZ (
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.V(VCC)
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);
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GND GND_cZ (
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.G(GND)
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);
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endmodule /* halfAdder */
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module halfAdder_0 (
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A_d,
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B_d,
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C_d
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)
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;
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input [1:0] A_d;
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input [1:0] B_d;
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output [3:2] C_d;
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wire VCC;
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wire GND;
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LUT4 C_d_3_s (
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.F(C_d[3]),
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.I0(A_d[0]),
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.I1(B_d[0]),
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.I2(A_d[1]),
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.I3(B_d[1])
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);
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defparam C_d_3_s.INIT=16'h7000;
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LUT4 C_d_2_s (
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.F(C_d[2]),
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.I0(A_d[1]),
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.I1(B_d[0]),
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.I2(A_d[0]),
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.I3(B_d[1])
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);
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defparam C_d_2_s.INIT=16'h8000;
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VCC VCC_cZ (
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.V(VCC)
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);
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GND GND_cZ (
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.G(GND)
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);
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endmodule /* halfAdder_0 */
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module mult2bit (
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A,
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B,
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C
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)
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;
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input [1:0] A;
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input [1:0] B;
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output [3:0] C;
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wire [1:0] A_d;
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wire [1:0] B_d;
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wire [0:0] C_d;
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wire [1:1] C_d_0;
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wire [3:2] C_d_1;
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wire VCC;
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wire GND;
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IBUF A_0_ibuf (
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.O(A_d[0]),
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.I(A[0])
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);
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IBUF A_1_ibuf (
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.O(A_d[1]),
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.I(A[1])
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);
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IBUF B_0_ibuf (
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.O(B_d[0]),
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.I(B[0])
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);
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IBUF B_1_ibuf (
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.O(B_d[1]),
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.I(B[1])
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);
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OBUF C_0_obuf (
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.O(C[0]),
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.I(C_d[0])
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);
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OBUF C_1_obuf (
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.O(C[1]),
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.I(C_d_0[1])
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);
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OBUF C_2_obuf (
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.O(C[2]),
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.I(C_d_1[2])
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);
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OBUF C_3_obuf (
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.O(C[3]),
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.I(C_d_1[3])
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||||
);
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LUT2 C_d_0_s (
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.F(C_d[0]),
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.I0(B_d[0]),
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.I1(A_d[0])
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);
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defparam C_d_0_s.INIT=4'h8;
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halfAdder h0 (
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.A_d(A_d[1:0]),
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.B_d(B_d[1:0]),
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||||
.C_d(C_d_0[1])
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||||
);
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halfAdder_0 h1 (
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||||
.A_d(A_d[1:0]),
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.B_d(B_d[1:0]),
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||||
.C_d(C_d_1[3:2])
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||||
);
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VCC VCC_cZ (
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.V(VCC)
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);
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GND GND_cZ (
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.G(GND)
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);
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GSR GSR (
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.GSRI(VCC)
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);
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endmodule /* mult2bit */
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173
labs/lab3/impl/gwsynthesis/lab3_syn.rpt.html
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173
labs/lab3/impl/gwsynthesis/lab3_syn.rpt.html
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@ -0,0 +1,173 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>synthesis Report</title>
|
||||
<style type="text/css">
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 12px; }
|
||||
div#main_wrapper{ width: 100%; }
|
||||
div#content { margin-left: 350px; margin-right: 30px; }
|
||||
div#catalog_wrapper {position: fixed; top: 30px; width: 350px; float: left; }
|
||||
div#catalog ul { list-style-type: none; }
|
||||
div#catalog li { text-align: left; list-style-type:circle; color: #0084ff; margin-top: 3px; margin-bottom: 3px; }
|
||||
div#catalog a { display:inline-block; text-decoration: none; color: #0084ff; font-weight: bold; padding: 3px; }
|
||||
div#catalog a:visited { color: #0084ff; }
|
||||
div#catalog a:hover { color: #fff; background: #0084ff; }
|
||||
hr { margin-top: 30px; margin-bottom: 30px; }
|
||||
h1, h3 { text-align: center; }
|
||||
h1 {margin-top: 50px; }
|
||||
table, th, td { border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { padding: 5px 5px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table.summary_table td.label { width: 24%; min-width: 200px; background-color: #dee8f4; }
|
||||
table.detail_table td.label { min-width: 100px; width: 8%;}
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="main_wrapper">
|
||||
<div id="catalog_wrapper">
|
||||
<div id="catalog">
|
||||
<ul>
|
||||
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
|
||||
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
|
||||
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
|
||||
<ul>
|
||||
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
|
||||
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
|
||||
</ul>
|
||||
</li>
|
||||
</ul>
|
||||
</div><!-- catalog -->
|
||||
</div><!-- catalog_wrapper -->
|
||||
<div id="content">
|
||||
<h1><a name="about">Synthesis Messages</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Report Title</td>
|
||||
<td>GowinSynthesis Report</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Design File</td>
|
||||
<td>C:\cygwin64\home\koray\verilog\lab3\src\fullAdder.v<br>
|
||||
C:\cygwin64\home\koray\verilog\lab3\src\halfAdder.v<br>
|
||||
C:\cygwin64\home\koray\verilog\lab3\src\mult2bit.v<br>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">GowinSynthesis Constraints File</td>
|
||||
<td>---</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Tool Version</td>
|
||||
<td>V1.9.9.02</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Part Number</td>
|
||||
<td>GW2A-LV18PG256C8/I7</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device</td>
|
||||
<td>GW2A-18</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Device Version</td>
|
||||
<td>C</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Created Time</td>
|
||||
<td>Sat May 4 01:07:38 2024
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Legal Announcement</td>
|
||||
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. ALL rights reserved.</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="summary">Synthesis Details</a></h1>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label">Top Level Module</td>
|
||||
<td>mult2bit</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Synthesis Process</td>
|
||||
<td>Running parser:<br/> CPU time = 0h 0m 0.109s, Elapsed time = 0h 0m 0.134s, Peak memory usage = 417.762MB<br/>Running netlist conversion:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/> Optimizing Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Optimizing Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/>Running inference:<br/> Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Inferring Phase 3: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/>Running technical mapping:<br/> Tech-Mapping Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Tech-Mapping Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/> Tech-Mapping Phase 3: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.308s, Peak memory usage = 417.762MB<br/> Tech-Mapping Phase 4: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 417.762MB<br/>Generate output files:<br/> CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.005s, Peak memory usage = 417.762MB<br/></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Total Time and Memory Usage</td>
|
||||
<td>CPU time = 0h 0m 0.234s, Elapsed time = 0h 0m 0.447s, Peak memory usage = 417.762MB</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h1><a name="resource">Resource</a></h1>
|
||||
<h2><a name="usage">Resource Usage Summary</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label"><b>Resource</b></td>
|
||||
<td><b>Usage</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>I/O Port </b></td>
|
||||
<td>8</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>I/O Buf </b></td>
|
||||
<td>8</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    IBUF</td>
|
||||
<td>4</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    OBUF</td>
|
||||
<td>4</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label"><b>LUT </b></td>
|
||||
<td>4</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    LUT2</td>
|
||||
<td>1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">    LUT4</td>
|
||||
<td>3</td>
|
||||
</tr>
|
||||
</table>
|
||||
<h2><a name="utilization">Resource Utilization Summary</a></h2>
|
||||
<table class="summary_table">
|
||||
<tr>
|
||||
<td class="label"><b>Resource</b></td>
|
||||
<td><b>Usage</b></td>
|
||||
<td><b>Utilization</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Logic</td>
|
||||
<td>4(4 LUT, 0 ALU) / 20736</td>
|
||||
<td><1%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">Register</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">  --Register as Latch</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">  --Register as FF</td>
|
||||
<td>0 / 16173</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">BSRAM</td>
|
||||
<td>0 / 46</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
||||
66
labs/lab3/impl/gwsynthesis/lab3_syn_resource.html
Normal file
66
labs/lab3/impl/gwsynthesis/lab3_syn_resource.html
Normal file
@ -0,0 +1,66 @@
|
||||
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
|
||||
<html>
|
||||
<head>
|
||||
<title>Hierarchy Module Resource</title>
|
||||
<style type="text/css">
|
||||
body { font-family: Verdana, Arial, sans-serif; font-size: 14px; }
|
||||
div#main_wrapper{ width: 100%; }
|
||||
h1 {text-align: center; }
|
||||
h1 {margin-top: 36px; }
|
||||
table, th, td { border: 1px solid #aaa; }
|
||||
table { border-collapse:collapse; margin-top: 10px; margin-bottom: 20px; width: 100%; }
|
||||
th, td { align = "center"; padding: 5px 2px 5px 5px; }
|
||||
th { color: #fff; font-weight: bold; background-color: #0084ff; }
|
||||
table td.label { width: 20%; white-space: nowrap; min-width: 20px; background-color: #dee8f4; }
|
||||
</style>
|
||||
</head>
|
||||
<body>
|
||||
<div id="main_wrapper">
|
||||
<div id="content">
|
||||
<h1>Hierarchy Module Resource</h1>
|
||||
<table>
|
||||
<tr>
|
||||
<th class="label">MODULE NAME</th>
|
||||
<th class="label">REG NUMBER</th>
|
||||
<th class="label">ALU NUMBER</th>
|
||||
<th class="label">LUT NUMBER</th>
|
||||
<th class="label">DSP NUMBER</th>
|
||||
<th class="label">BSRAM NUMBER</th>
|
||||
<th class="label">SSRAM NUMBER</th>
|
||||
<th class="label">ROM16 NUMBER</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td class="label">mult2bit (C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v)</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">1</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
</tr>
|
||||
<td class="label">    |--h0
|
||||
(C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v)</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">1</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
</tr>
|
||||
<td class="label">    |--h1
|
||||
(C:/cygwin64/home/koray/verilog/lab3/src/mult2bit.v)</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">2</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
<td align = "center">-</td>
|
||||
</tr>
|
||||
</table>
|
||||
</div><!-- content -->
|
||||
</div><!-- main_wrapper -->
|
||||
</body>
|
||||
</html>
|
||||
5
labs/lab3/impl/gwsynthesis/lab3_syn_rsc.xml
Normal file
5
labs/lab3/impl/gwsynthesis/lab3_syn_rsc.xml
Normal file
@ -0,0 +1,5 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Module name="mult2bit" Lut="1" T_Lut="4(1)">
|
||||
<SubModule name="h0" Lut="1" T_Lut="1(1)"/>
|
||||
<SubModule name="h1" Lut="2" T_Lut="2(2)"/>
|
||||
</Module>
|
||||
Reference in New Issue
Block a user